TWI512971B - 絕緣閘雙極電晶體及其製造方法 - Google Patents

絕緣閘雙極電晶體及其製造方法 Download PDF

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TWI512971B
TWI512971B TW102134200A TW102134200A TWI512971B TW I512971 B TWI512971 B TW I512971B TW 102134200 A TW102134200 A TW 102134200A TW 102134200 A TW102134200 A TW 102134200A TW I512971 B TWI512971 B TW I512971B
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gan layer
gan
layer
gate
substrate
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TW201513340A (zh
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Chih Fang Huang
Tsung Yi Huang
Chien Wei Chiu
Tsung Yu Yang
Ting Fu Chang
Tsung Chieh Hsiao
Ya Hsien Liu
Po Chin Peng
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Richtek Technology Corp
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Priority to US14/971,496 priority patent/US9362381B2/en

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Description

絕緣閘雙極電晶體及其製造方法
本發明係有關一種絕緣閘雙極電晶體(insulated gate bipolar transistor,IGBT)及其製造方法；特別是指一種包含氮化鎵(gallium nitride,GaN)基板的IGBT其製造方法。
第1圖顯示一種習知IGBT 100的剖視示意圖。如第1圖所示，於一矽基板或碳化矽基板中形成IGBT 100，其包含P型陽極11、N型區12、P型區13、N型陰極14、閘極15、與N型緩衝層16。IGBT 100為一種垂直型的雙擴散金屬氧化物半導體(double diffusion metal oxide semiconductor,DMOS)IGBT，其中，由閘極15、並以N型緩衝層16作為汲極(drain)、N型區12作為漂移區(drift region)、P型區13作為井區(well)、N型陰極14作為源極(source)而形成於一垂直型的DMOS元件。另一方面，由P型區13作為射極(emitter)、N型緩衝層16作為基極(base)、P型陽極11做為集極(collector)而形成一雙極接面電晶體(bipolar junction transistor,BJT)。其中，當IGBT 100操作時，由垂直型的DMOS元件控制，使BJT導通或不導通，以實現由DMOS元件快速切換高功率元件BJT的功能。
當IGBT 100操作時，如第1圖所示，閘極15兩邊的N型陰極14與P型區13會形成寄生接面場效電晶體(junction field effect transistor,JFET)，N型陰極14與P型區13所形成的空乏區會使導通電流受限，限制了應用範圍。
有鑑於此，本發明即針對上述先前技術之改善，提出一種IGBT及其製造方法，可提高操作的速度並降低導通阻值。
就其中一觀點言，本發明提供了一種絕緣閘雙極電晶體 (insulated gate bipolar transistor,IGBT)包含：一氮化鎵(gallium nitride,GaN)基板，具有一上表面；一第一GaN層，具有第一導電型，形成於該上表面上，且該第一GaN層具有一側壁，垂直於該上表面；一第二GaN層，具有第一導電型，形成於該上表面上；一第三GaN層，具有與第一導電型相反之第二導電型或純質導電型，形成於該第一GaN層上，且該第三GaN層與該GaN基板間，由該第一GaN層隔開；以及一閘極，形成於該GaN基板上，且該閘極具有一側板，於一橫向上，鄰近或鄰接於該側壁，以控制一通道；其中，該第二GaN層與該第一GaN層之間，由該閘極隔開。
就另一觀點言，本發明提供了一種絕緣閘雙極電晶體(insulated gate bipolar transistor,IGBT)製造方法，包含：提供一氮化鎵(gallium nitride,GaN)基板，具有一上表面；形成一第一GaN層於該上表面上，具有第一導電型，且該第一GaN層具有一側壁，垂直於該上表面；形成一第二GaN層於該上表面上，具有第一導電型；形成一第三GaN層於該第一GaN層上，具有與第一導電型相反之第二導電型或純質導電型，且該第三GaN層與該GaN基板間，由該第一GaN層隔開；以及形成一閘極於該GaN基板上，且該閘極具有一側板，於一橫向上，鄰近或鄰接於該側壁，以控制一通道；其中，該第二GaN層與該第一GaN層之間，由該閘極隔開。
在其中一種較佳的實施型態中，該IGBT更包含一氮化鋁鎵(aluminum gallium nitride,AlGaN)阻障層，形成於該上表面上，並覆蓋該側壁，且該閘極與該GaN基板及該第一GaN層間，由該AlGaN阻障層隔開。
前述的實施例中，該GaN基板、該第一GaN層、該第三GaN層、該AlGaN層、與該閘極可形成一金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)，且該第三GaN層、該第一GaN層、該第二GaN層與該GaN基板可形成一雙極接面電晶體(bipolar junction transistor,BJT)，其中，該MOSFET與該BJT並聯。
在其中一種較佳的實施型態中，該GaN基板、該第一GaN層、該第三GaN層與該閘極形成一接面場效電晶體(junction field effect transistor,JFET)，且該第一GaN層、該第二GaN層與該GaN基板形成一雙極接面電晶體(bipolar junction transistor,BJT)，其中，該JFET與該BJT並聯。
11‧‧‧P型陽極
12‧‧‧N型區
13‧‧‧P型區
14‧‧‧N型陰極
15,24,34‧‧‧閘極
16‧‧‧N型緩衝層
21,31‧‧‧GaN基板
22a,22b,32a,32b‧‧‧GaN層
25,26,27‧‧‧導電層
38‧‧‧二維電子雲(2-D electron gas,2DEG)
39‧‧‧AlGaN阻障層
100,200,300‧‧‧IGBT
211,311‧‧‧上表面
221,321‧‧‧側壁
241,341‧‧‧側板
第1圖顯示一種習知IGBT 100的剖視示意圖。
第2A-2E圖顯示本發明的第一個實施例。
第3A-3D圖顯示本發明的第二個實施例。
本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。
第2A-2E圖顯示本發明的第一個實施例。第2A-2E圖顯示根據本發明之絕緣閘雙極電晶體(insulated gate bipolar transistor,IGBT)200的製造流程剖視示意圖。如第2A圖所示，首先，提供氮化鎵(gallium nitride,GaN)基板21，具有上表面211。GaN基板21例如但不限於為N型或純質導電型。接下來如第2B圖所示，於上表面上211上，形成GaN層22a與GaN層22b，例如但不限於為P型，且GaN層22a具有側壁221垂直於上表面211。接下來如第2C圖所示，於GaN層22a上形成GaN層23，其例如但不限於為導電型與P型相反的N型或純質導電型，且GaN層23與GaN基板21間，由GaN層22a隔開。接下來如第2D圖所示，於GaN基板21上形成閘極24，且閘極24具有側板241(如圖中虛框線所示意)，其於橫向上(如圖中實線箭號所示意)，鄰接於側壁221，以控制通道。接下來如第2E圖所示，形成導電層25、26、27，分別與GaN層22b、GaN層23、與GaN層22電連接，較佳地形成歐姆接觸，以作為GaN層22b、GaN層23、與GaN層22的電性接點。其中，GaN基板21、GaN層22a、GaN層23與閘極24形成接面場效電晶體(junction field effect transistor,JFET)，且GaN層22a、GaN層22b與GaN基板21形成雙極接面電晶體(bipolar junction transistor,BJT)，其中，JFET與BJT並聯。需說明的是，前述側板241所控制之通道係指當IGBT 200中之JFET於導通操作時，所形成的主要電流路徑。本實施例根據本發明，在JFET於導通操作時，會在前述通道中，形成二維電子雲(2-D electron gas,2DEG)(如圖中虛線所示意)，其中之電流即為前述BJT之基極電流，用以控制BJT之射極-集極電流。BJT之基極電流與射極-集極電流為本領域中具有通常知識者所熟知，在此不予贅述。
本發明主要的概念在於，第一，不同於先前技術IGBT是垂直結構，本發明IGBT為橫向結構。相較於垂直結構的IGBT，根據本發明，橫向結構的IGBT可整合於其他半導體元件製程，例如但不限於為蕭特基位障二極體(Schottky-barrier diode,SBD)或高電子遷移率電晶體(high electron mobility transistor,HEMT)等元件之製程中。因此，可節省製造成本並降低產品的尺寸。第二。不同於先前技術IGBT所具有之矽基板或碳化矽基板，根據本發明之IGBT包括GaN基板，可大幅改善操作速度，使得根據本發明之IGBT相較於先前技術，可以更快速切換，而可適用於高頻元件，增加IGBT的應用範圍。
第3A-3D圖顯示本發明的第二個實施例。本實施例旨在說明根據本發明，IGBT 300相較於第一個實施例IGBT 200，可更包含氮化鋁鎵(aluminum gallium nitride,AlGaN)阻障層39，形成於上表面311上，並覆蓋側壁321，且閘極34與GaN基板31及GaN層32a間，由AlGaN阻障層39隔開。第3A-3D圖顯示根據本發明之IGBT 300的製造流程剖視示意圖。如第3A圖所示，首先，提供氮化鎵(gallium nitride,GaN)基板31，具有上表面311。GaN基板31例如但不限於為N型或純質導電型。接下來如第3B圖所示，於上表面上311上，形成GaN層32a與32b，例如但不限於為P型，且GaN層32a具有側壁321垂直於上表面311。接下來如第3C圖所示，於GaN層32a上形成GaN層33，其例如但不限於為導電型與P型相反的N型或純質導電型，且GaN層33與GaN基板31間，由GaN層32a隔開。接下來如第3D圖所示，於GaN基板31上形成AlGaN阻障層39與閘極34，且閘極34具有側板341(如圖中虛框線所示意)，其於橫向上(如圖中實線箭號所示意)，鄰近於側壁321，以控制通道。如圖所示，在橫向上，側板341鄰接AlGaN阻障層39，且AlGaN阻障層39鄰接於GaN層32之側壁321。其中，GaN基板31、GaN層32a、GaN層33、AlGaN阻障層39與閘極34形成金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)，且GaN層32a、GaN層32b與GaN基板31形成BJT，其中，MOSFETFET與BJT並聯。
需說明的是，前述側板341所控制之通道係指當IGBT 200中之MOSFET於導通操作時，所形成的主要電流路徑。本實施例根據本發明，在MOSFET於導通操作時，會在前述通道中，形成二維電子雲(2-D electron gas,2DEG)38(如圖中虛線所示意)，其中之電流即為前述BJT之基極電流，用以控制BJT之射極-集極電流。2DEG 38可大幅改善操作速度，使得IGBT 300相較於先前技術，可以更快速切換；此外，2DEG 38亦可以降低導通阻值，使得IGBT 300操作時有更佳的電子特性
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，本發明所稱「側壁221垂直於上表面211」，並不表示必須絕對無誤差地恰好垂直，而應視為可容許有微幅的偏離；又如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如深井區等。本發明的範圍應涵蓋上述及其他所有等效變化。
21‧‧‧GaN基板
22a,22b‧‧‧P型GaN層
23‧‧‧N型GaN層
24‧‧‧閘極
25,26,27‧‧‧導電層
200‧‧‧IGBT
211‧‧‧上表面

Claims (8)

  1. 一種絕緣閘雙極電晶體(insulated gate bipolar transistor,IGBT)包含：一氮化鎵(gallium nitride,GaN)基板，具有一上表面；一第一GaN層，具有第一導電型，形成於該上表面上，且該第一GaN層具有一側壁，垂直於該上表面；一第二GaN層，具有第一導電型，形成於該上表面上；一第三GaN層，具有與第一導電型相反之第二導電型或純質導電型，形成於該第一GaN層上，且該第三GaN層與該GaN基板間，由該第一GaN層隔開；以及一閘極，形成於該GaN基板上，且該閘極具有一側板，於一橫向上，鄰近或鄰接於該側壁，以控制一通道；其中，該第二GaN層與該第一GaN層之間，由該閘極隔開。
  2. 如申請專利範圍第1項所述之IGBT，更包含一氮化鋁鎵(aluminum gallium nitride,AlGaN)阻障層，形成於該上表面上，並覆蓋該側壁，且該閘極與該GaN基板及該第一GaN層間，由該AlGaN阻障層隔開。
  3. 如申請專利範圍第1項所述之IGBT，其中該GaN基板、該第一GaN層、該第三GaN層與該閘極形成一接面場效電晶體(junction field effect transistor,JFET)，且該第一GaN層、該第二GaN層與該GaN基板形成一雙極接面電晶體(bipolar junction transistor,BJT)，其中，該JFET與該BJT並聯。
  4. 如申請專利範圍第2項所述之IGBT，其中該GaN基板、該第一GaN層、該第三GaN層、該AlGaN層、與該閘極形成一金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)，且該第一GaN層、該第二GaN層與該GaN基板形成一雙極接面電晶體(bipolar junction transistor,BJT)，其中，該MOSFET與該BJT並聯。
  5. 一種絕緣閘雙極電晶體(insulated gate bipolar transistor,IGBT)製造方法，包含：提供一氮化鎵(gallium nitride,GaN)基板，具有一上表面；形成一第一GaN層於該上表面上，具有第一導電型，且該第一GaN層具有一側壁，垂直於該上表面； 形成一第二GaN層於該上表面上，具有第一導電型；形成一第三GaN層於該第一GaN層上，具有與第一導電型相反之第二導電型或純質導電型，且該第三GaN層與該GaN基板間，由該第一GaN層隔開；以及形成一閘極於該GaN基板上，且該閘極具有一側板，於一橫向上，鄰近或鄰接於該側壁，以控制一通道；其中，該第二GaN層與該第一GaN層之間，由該閘極隔開。
  6. 如申請專利範圍第5項所述之IGBT製造方法，更包含：形成一氮化鋁鎵(aluminum gallium nitride,AlGaN)阻障層於該上表面上，並覆蓋該側壁，且該閘極與該GaN基板及該第一GaN層間，由該AlGaN阻障層隔開。
  7. 如申請專利範圍第5項所述之IGBT製造方法，其中該GaN基板、該第一GaN層、該第三GaN層與該閘極形成一接面場效電晶體(junction field effect transistor,JFET)，且該第一GaN層、該第二GaN層與該GaN基板形成一雙極接面電晶體(bipolar junction transistor,BJT)，其中，該JFET與該BJT並聯。
  8. 如申請專利範圍第6項所述之IGBT製造方法，其中該GaN基板、該第一GaN層、該第三GaN層、該AlGaN層、與該閘極形成一金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)，且該第一GaN層、該第二GaN層與該GaN基板形成一雙極接面電晶體(bipolar junction transistor,BJT)，其中，該MOSFET與該BJT並聯。
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