TWI512422B - Output buffer with pvtl compensation and the leakage compensation circuit thereof - Google Patents

Output buffer with pvtl compensation and the leakage compensation circuit thereof Download PDF

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Publication number
TWI512422B
TWI512422B TW103135429A TW103135429A TWI512422B TW I512422 B TWI512422 B TW I512422B TW 103135429 A TW103135429 A TW 103135429A TW 103135429 A TW103135429 A TW 103135429A TW I512422 B TWI512422 B TW I512422B
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Taiwan
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voltage
circuit
output
comparison
type
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Application number
TW103135429A
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Chinese (zh)
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TW201614406A (en
Inventor
Chua-Chin Wang
Tzung-Je Lee
Kai-Wei Ruan
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Univ Nat Sun Yat Sen
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Priority to TW103135429A priority Critical patent/TWI512422B/en
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Publication of TWI512422B publication Critical patent/TWI512422B/en
Publication of TW201614406A publication Critical patent/TW201614406A/en

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Description

Output buffer with process, voltage, temperature and leakage current compensation and leakage current compensation circuit thereof
This invention relates to an output buffer, and more particularly to an output buffer having process, voltage, temperature and leakage current compensation.
With the evolution of the semiconductor process, in order to reduce the power consumption, the supply voltage used by the integrated circuit is getting lower and lower. When the wafers of different processes are integrated on the same printed circuit board, the supply voltage of the wafers of different processes is different. The difference is that the voltages of the various components in different wafers can not be the same, and there is a problem that the data cannot be transferred between the wafers. Therefore, an output buffer of the outside of the wafer must be used between the wafers of different processes. communication.
In addition, the evolution of the semiconductor process also makes the size of the integrated circuit smaller, resulting in reliability, hot-carrier degradation, and leakage current when wafers of different processes are integrated. Wait for many problems to arise. Among them, due to the size reduction of the integrated circuit, the gate oxide layer is thinned, which causes the tunneling effect of electrons. The electron tunneling effect causes some electrons to pass through the oxide layer of the gate terminal to cause leakage current. The generation of the conventional output into the buffer has the problems of voltage drift, gate oxide overvoltage, and increased power consumption, and cannot be applied to advanced processes.
The main purpose of the present invention is to compensate the leakage current of the output buffer by the leakage current compensation circuit to avoid the problem that the output buffer generates voltage drift, gate oxide overvoltage and power consumption, and the output buffer can be Wafer integration for advanced processes.
An output buffer with process, voltage, temperature and leakage current compensation includes a process voltage temperature sensor, a determiner, an output buffer and a leakage current compensation circuit, wherein the process voltage temperature sensor is used for detecting one a PMOS threshold voltage signal, a PMOS threshold voltage process and a temperature signal, and an NMOS threshold voltage signal, the determiner receiving the PMOS threshold voltage signal, the PMOS threshold voltage process and the temperature signal, and the NMOS threshold voltage signal, the determiner Comparing the PMOS threshold voltage signal, the PMOS threshold voltage process and the temperature signal, and the NMOS threshold voltage signal with the plurality of reference signals, respectively, and outputting a plurality of comparison signals, and the comparison signals are encoded into a P by a digital logic circuit. a type of digital signal and an N-type digital signal, the output buffer has a pre-drive circuit, a voltage generating circuit, a first VDDIO detecting circuit and an output stage, the pre-drive circuit receiving the P-type digital signal and the An N-type digital signal, and the pre-driver circuit outputs a plurality of P-type pre-drive signals and a plurality of N-type control signals, The voltage generating circuit receives the P-type pre-drive signals, and the voltage generator outputs a plurality of P-type control signals, and the output stage receives the P-type control signals and the N-type control signals, wherein the output stage has a a P-type output transistor, the P-type output transistor and the voltage generating circuit receive a detection voltage of the first VDDIO detection circuit output, the leakage current compensation circuit is electrically connected to the P-type output power of the output stage a crystal, the leakage current compensation circuit has a leakage current detector and a voltage-controlled current source, the leakage current detector receives the detection voltage, and the leakage current detector compares the detection voltage with a reference detection The magnitude of the voltage outputs a comparison voltage signal to the voltage control current source, and the voltage control current source provides a compensation current to the P-type output transistor according to the comparison voltage signal.
The leakage current compensation circuit compensates the leakage current when the detection voltage is drifted, and the problem of the detection voltage drift can be effectively improved to avoid the overvoltage of the gate oxide layer of the P-type output transistor. The problem occurs and the voltage slew rate of the output buffer is increased.
Referring to FIG. 1 , an output buffer 100 with process, voltage, temperature and leakage current compensation includes a process voltage temperature sensor 200 , a determiner 300 , an output buffer 400 , and a leakage current compensation circuit 500 .
Referring to FIG. 1 , the process voltage temperature sensor 200 has a PMOS threshold voltage detector 210 , a PMOS threshold voltage process and temperature detector 220 , and an NMOS threshold voltage detector 230 . The detector 210 is configured to detect a PMOS threshold voltage signal pout. The PMOS threshold voltage processing and temperature detector 220 is configured to detect a PMOS threshold voltage process and a temperature signal VTout. The NMOS threshold voltage detector 230 For detecting an NMOS threshold voltage signal nout, please refer to FIG. 6 , which is a circuit diagram of the PMOS threshold voltage detector 210. The PMOS threshold voltage detector 210 has an inverter 211 and four P-type transistors. 212, 213, 214, 215, the working principle is that when one of the first reset signals rst1 is input to be high, the P-type transistors 212 and 214 are turned on, and the P-type transistor 212 and the P-type transistor are turned on. A first node N1 between the 213 and the PMOS threshold voltage signal pout will be charged to a high potential. Then, when the first reset signal rst1 is turned from a high potential to a low potential, the inverter 211 outputs a high potential and is turned off. The P-type transistors 212 and 214, and the P-type transistor 213 215 is also turned off because the gate-source voltage is less than the threshold voltage. Therefore, the potential of the first node N1 is discharged, and the PMOS threshold voltage signal pout is discharged to, where is the threshold voltage of the P-type transistor. .
Referring to FIG. 7, the PMOS threshold voltage processing and temperature detector 220 is similar to the circuit of the PMOS threshold voltage detector 210, and has an inverter 221 and four P-type transistors 222 and 223. 224, 225, the PMOS threshold voltage process and temperature detector 220 and the PMOS threshold voltage detector 210 operate in the same principle, the difference is that the PMOS threshold voltage process and the temperature detector 220 The bases of the P-type transistors 223 and 225 are connected to the power source, and the P-type transistors 213 and 215 of the PMOS threshold voltage detector 210 are connected to the respective sources, and thus, similarly, when the first reset When the signal rst1 is turned from a high level to a low level, the PMOS threshold voltage type process and the temperature signal VTout are discharged.
Please refer to FIG. 8 , which is a circuit diagram of the NMOS threshold voltage detector 230. The NMOS threshold voltage detector 230 has two inverters 231 , 232 and four N-type transistors 233 , 234 , 235 , 236 . The working principle is that when the first reset signal rst1 is high, a second node N2 between the N-type transistor 233 and the N-type transistor 234 and the NMOS threshold voltage signal nout are discharged to a low potential. Then, when the first reset signal rst1 is turned from a high potential to a low potential, the inverter 231 outputs a high potential to turn on the N-type transistor 233, and the inverter 232 outputs a low potential to turn off the N-type. The transistors 234 and 236 charge the second node N2 and turn on the N-type transistor 235 to charge the NMOS threshold voltage signal nout, where is the threshold voltage of the N-type transistor.
Referring to FIG. 1 , the determiner 300 has a bias generator 310 , a first comparator 320 , a second comparator 330 , a third comparator 340 , and a digital logic circuit 350 . 310 for providing a first reference signal V REFP1, a second reference signal V REFP2 and a third reference signal V REFN, the first comparator 320 receives the first reference signal V REFP1 and the threshold voltage of the PMOS signal pout, The first comparator 320 outputs a first comparison signal V P1 , the second comparator 330 receives the second reference signal V REFP2 and the PMOS threshold voltage process and the temperature signal VTout, and the second comparator 330 outputs a third comparison signal V P2 , the third comparator 340 receives the third reference signal V REFN and the NMOS threshold voltage signal nout, and the third comparator 340 outputs a third comparison signal V N , the digital logic circuit The receiving, by the 350, the first comparison signal V P1 , the second comparison signal V P2 , the third comparison signal V N , the first reset signal rst1 and a count signal clock, by the process voltage temperature sensor 200 Circuit action can be learned when When the first reset signal rst1 is turned from a high level to a low level, the PMOS threshold voltage signal pout, the PMOS threshold voltage type process and the temperature signal VTout and the NMOS threshold voltage signal none are respectively reached or, therefore, the first reference The signal V REFP1 and the second reference signal V REFP2 are set, and the third reference signal V REFN is sized to pass through the first comparator 320, the second comparator 330, and the third comparator 340. The comparison is performed at the time point when the PMOS threshold voltage signal pout, the PMOS threshold voltage type process and the temperature signal VTout and the NMOS threshold voltage signal nout reach or, and the digital logic circuit 350 counts the counter through a counter (not shown). The counting signal clock obtains the time when the PMOS threshold voltage signal pout, the PMOS threshold voltage type process and the temperature signal VTout and the NMOS threshold voltage signal nout reach or, to determine that the P-type transistor and the N-type transistor are located. The PVT corner, the digital logic circuit 350 encodes the first comparison signal V P1 , the second comparison signal V P2 and the third comparison signal V N into a P-type digital signal P code and an N-type digital signal. No. N code for control of the back end circuit.
Referring to FIG. 2, the output buffer 400 has a pre-drive circuit 410, a voltage generating circuit 420, a first VDDIO detecting circuit 430, and an output stage 440. The pre-drive circuit 410 receives a transmission signal DOUT. The P-type digital signal P code and the N-type digital signal N code are encoded to output a plurality of P-type pre-drive signals PDOUTa, PDOUTb, PDOUTc and a plurality of N-type control signals V g4a , V g4b , V g4c .
Referring to FIGS. 2 and 5, the voltage generating circuit 420 receives the P-type pre-drive signals PDOUTa, PDOUTb, PDOUTc and a detection voltage V g2 output by the first VDDIO detection circuit 430, and the voltage generator 420 output a plurality of P-type control signal V g1a, V g1b, V g1c , the output stage 440 has a P-type output transistor 441, an N-type output transistor 442, a plurality of P type compensation transistors 443 and a plurality of N The type compensation transistor 444, each of the P-type compensation transistors 443 receives each of the P-type control signals to provide a compensation voltage to the P-type output transistor 441, and each of the N-type compensation transistors 444 receives each of the N-type control signals. A compensation voltage is applied to the N-type output transistor 442 to boost the voltage slew rate of the output buffer 400.
Referring to FIG. 5, in the embodiment, the voltage generating circuit 420 has three sets of the same voltage level converter 421 of FIG. 5, and each of the P-type pre-drive signals PDOUTa, PDOUTb, and PDOUTc is regulated by each voltage. bit converter 421 receives, by 421 output respective voltage level converter of each of the P-type control signal V g1a, V g1b, V g1c , since the circuit 3 voltage level converter 421 of actuating the same and are each independent actuation of Therefore, in FIG. 5, only one voltage level converter 421 is taken as an example, wherein each of the P-type pre-drive signals PDOUTa, PDOUTb, and PDOUTc is represented as PDOUTx (x=a, b, c), and each of the P-type controls signal V g1a, V g1b, V g1c expressed as V g1x (x = a, b , c), in the present embodiment interest, when an external voltage VDDIO is 1.8 V, the voltage level converter 421 PDOUTx (0 V~1 V) is converted to V g1x (1 V~1.8 V) to turn on or off each of the P-type compensation transistors 443, so that the P-type compensation transistors 443 are compensated for the P-type output transistor 441. At the same time, the problem of overvoltage of the gate oxide layer of each of the P-type compensation transistors 443 can be avoided.
Referring to FIG. 4, the first VDDIO detecting circuit 430 has a second voltage dividing circuit 431, a determining circuit 432, a second output circuit 433, a stacking inverter circuit 434, and a third partial piezoelectric. The second voltage dividing circuit 431 receives the external voltage VDDIO, and the second voltage dividing circuit 431 provides a bias voltage to the determining circuit 432 and the second output circuit 433. The determining circuit 432 receives the external voltage. VDDIO, the determining circuit 432 is configured to determine the potential of the external voltage VDDIO to selectively turn on or off a second output transistor 433b of the second output circuit 433, and output an output of the second output transistor 433b. The voltage is output to the P-type output transistor 441 via the stacked inverter circuit 434, and the third voltage dividing circuit 435 is used to bias the stacked inverter circuit 434, wherein when the voltage of the external voltage VDDIO is At 1.8 V, a P-type transistor 432b, an N-type transistor 432c, and an N-type transistor 432d of the determining circuit 432 are turned on, so that the second output transistor 433b of the second output circuit 433 is turned on, so that A third node N3 is discharged to a low potential, at this time, the third section After the potential of the point N3 is clamped by the stacking inverter circuit 434 and the third voltage dividing circuit 435 is clamped, the detected voltage V g2 outputted by the stacked inverter circuit 434 is 0.6 V. Referring to FIG. 2, the detection voltage V g2 is used to bias the P-type output transistor 441 to prevent the P-type output transistor 441 from over-voltage of the gate oxide layer. Referring to FIG. 4, when the voltage of the external voltage VDDIO is 1.2/1.0 V, the P-type transistor 432b and the second output transistor 433b are turned off, and a P-type transistor 432a and the second output circuit 433 are turned off. A third load transistor 433a is turned on, so that the third node N3 is charged to a high potential. At this time, after the potential of the third node N3 is commutated via the stacked inverter circuit 434, the stacked inverter The circuit 434 outputs the detection voltage V g2 to 0 V. The first VDDIO detecting circuit 430 enables the output buffer 400 to transmit signals at different potentials of the external voltage VDDIO, and can avoid the gate caused by the difference in potential between the external voltage VDDIO and the power supply VDD. Extreme oxide layer overpressure.
Referring to FIG. 2 , the first VDDIO detection circuit 430 can provide the detection voltage V g2 to the P-type output transistor 441 of the output stage 440 to bias the P-type output transistor 441 to avoid The gate electrode oxide layer of the P-type output transistor 441 is over-pressurized, but since the thickness of the gate terminal of the transistor is thinner and thinner in an advanced process, the P-type output transistor 441 generates a leakage current I leakage. The situation occurs, which causes the voltage of the detection voltage V g2 used to bias the P-type output transistor 441 to drop, causing the gate oxide layer of the P-type output transistor 441 to over-press and burn, although a thick gate is used. The process of the polar oxide layer can improve this problem, but it also increases the manufacturing cost of the overall circuit.
Referring to Figures 1, 2 and 3, the leakage current compensation circuit 500 is electrically connected to the P-type output transistor 441 of the output stage 440. The leakage current compensation circuit 500 has a leakage current detector 510 and a voltage. The current source 520 is controlled, the leakage current detector 510 receives the detection voltage V g2 , and the leakage current detector 510 compares the detection voltage V g2 with a reference detection voltage V g2REF and outputs a comparison voltage. The signal V comp is applied to the voltage-controlled current source 520. Since the reference detection voltage V g2REF is not affected by the leakage current I leakage of the P-type output transistor 441, the reference voltage V g2 can be output when the detection voltage V g2 drifts. The voltage signal V comp is compared, and the voltage control current source 520 provides a compensation current Icomp to the P-type output transistor 441 according to the comparison voltage signal V comp to improve the drift of the detection voltage V g2 .
Referring to FIGS. 2 and 3, in the present embodiment, the leakage current detector 510 has a comparison circuit 511, a second VDDIO detection circuit 512, a first voltage dividing circuit 513, and a first output circuit. 514 and a reset transistor 515, the first voltage dividing circuit 513 is configured to provide a bias voltage to the comparison circuit 511 and the first output circuit 514, and the second VDDIO detection circuit 512 is configured to provide the reference detector The voltage V g2REF is measured, wherein the circuit structure of the second VDDIO detecting circuit 512 is the same as that of the first VDDIO detecting circuit 430. Therefore, under the same external voltage VDDIO as the first VDDIO detecting circuit 430, the first The VDDIO detection circuit 512 can provide the reference detection voltage V g2REF of the same potential level , and since the second VDDIO detection circuit 512 is not electrically connected to the P-type output transistor 441 of the output stage 440, The reference detection voltage V g2REF output by the second VDDIO detection circuit 512 is not affected by the leakage current I leakage of the P-type output transistor 441, and can be used as a reference for comparison.
Referring to FIG. 3, the comparison circuit 511 receives the detection voltage V g2 and the reference detection voltage V g2REF and outputs a comparison potential Vo. When the detection voltage V g2 is greater than the reference detection voltage V g2REF , The comparison potential Vo is at a high potential. When the detection voltage V g2 is less than the reference detection voltage V g2REF , the comparison potential Vo is low. In the embodiment, the comparison circuit 511 has a first load transistor 511a. a P-type differential pair 511b and a current mirror 511c, the first load transistor 511a receives the bias voltage of the first voltage dividing circuit 513, and the P-type differential pair 511b is electrically connected to the first load power crystal 511a, 511c of the current mirror is electrically connected to the P-type differential pair 511b, wherein the P-type differential receives the detection voltage V g2 and 511b for detecting the reference voltage V g2REF and providing the comparison voltage Vo.
Referring to FIG. 3, the first output circuit 514 is configured to output the comparison voltage signal Vcomp . In the embodiment, the first output circuit 514 has a second load transistor 514a and a first output transistor 514b. The first output transistor 514b receives the bias voltage of the first voltage dividing circuit 513, and the first output transistor 514b receives the comparison potential Vo. When the comparison potential Vo is high, the first output power The crystal 514b is turned on to lower the comparison voltage signal Vcomp to a low potential. When the comparison potential Vo is low, the first output transistor 514b is turned off, and the comparison voltage signal Vcomp is raised to a high potential. And the reset transistor 515 is electrically connected to the first output transistor 514b, and the reset transistor 515 receives a second reset signal to reset the potential rst2 the comparison voltage V comp signal is.
Referring to FIG. 3, the voltage-controlled current source 520 has a first current mirror 521 and a second current mirror 522. The first current mirror 521 and the second current mirror 522 are overlapped with each other. The first current mirror the comparator 521 receives a voltage signal V comp, the second current mirror 522 is electrically connected to the P-type output transistor 441, the second current mirror 522 for providing the compensation current Icomp output to the P-type transistor 441.
Referring to FIG. 3, the circuit of the leakage current compensation circuit 500 is activated when the detection voltage V g2 is less than the reference detection voltage V g2REF (that is, the detection voltage V g2 output by the first VDDIO detection circuit 430). When the leakage current I leakage is decreased, the comparison potential Vo is discharged to a low potential. Therefore, the first output transistor 514b of the first output circuit 514 is turned off, and the comparison voltage signal V comp is charged to a high potential. The first current mirror 521 is turned on, so that the compensation current Icomp can be controlled by the magnitude of the comparison voltage signal Vcomp and flows through the first current mirror 521 and the second current mirror 522 to leak the output buffer 400. Current compensation to improve the drift of the detection voltage V g2 .
The leakage current compensation circuit 500 compensates for the leakage current when the detection voltage V g2 drifts, which can effectively improve the drift of the detection voltage V g2 to avoid the gate of the P-type output transistor 441. The problem of extreme oxide overvoltage occurs and increases the voltage slew rate of the output buffer 400.
The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
100‧‧‧ Output buffer with process, voltage, temperature and leakage current compensation
200‧‧‧Processing voltage temperature sensor
210‧‧‧ PMOS threshold voltage detector
211‧‧‧Inverter
212‧‧‧P type transistor
213‧‧‧P type transistor
214‧‧‧P type transistor
215‧‧‧P type transistor
220‧‧‧ PMOS threshold voltage process and temperature detector
221‧‧‧Inverter
222‧‧‧P type transistor
223‧‧‧P type transistor
224‧‧‧P type transistor
225‧‧‧P type transistor
230‧‧‧ NMOS threshold voltage detector
231‧‧‧Inverter
232‧‧‧Inverter
233‧‧‧N type transistor
234‧‧‧N type transistor
235‧‧‧N type transistor
236‧‧‧N type transistor
300‧‧‧Determinator
310‧‧‧ bias generator
320‧‧‧First comparator
330‧‧‧Second comparator
340‧‧‧ third comparator
350‧‧‧Digital logic circuit
400‧‧‧Output buffer
410‧‧‧Front drive circuit
420‧‧‧Voltage generation circuit
421‧‧‧Voltage level converter
430‧‧‧First VDDIO detection circuit
431‧‧‧Second voltage divider circuit
432‧‧‧Judgement circuit
432a‧‧‧P type transistor
432b‧‧‧P type transistor
432c‧‧‧N type transistor
432d‧‧‧N type transistor
432e‧‧‧N type transistor
433‧‧‧second output circuit
433a‧‧‧ third load transistor
433b‧‧‧second output transistor
434‧‧‧Stacked inverter circuit
435‧‧‧ Third voltage divider circuit
440‧‧‧Output level
441‧‧‧P type output transistor
442‧‧‧N type output transistor
443‧‧‧P type compensation transistor
444‧‧‧N type compensation transistor
500‧‧‧Leakage current compensation circuit
510‧‧‧Leakage current detector
511‧‧‧Comparative circuit
511a‧‧‧First load transistor
511b‧‧‧P type differential pair
511c‧‧‧current mirror
512‧‧‧Second VDDIO detection circuit
513‧‧‧First voltage divider circuit
514‧‧‧First output circuit
514a‧‧‧Second load transistor
514b‧‧‧First output transistor
515‧‧‧Reset the transistor
520‧‧‧voltage controlled current source
521‧‧‧First current mirror
522‧‧‧second current mirror
DOUT‧‧‧ transmission signal
Pout‧‧‧ PMOS threshold voltage signal
VTout‧‧‧ PMOS threshold voltage process and temperature signal
PAD‧‧‧Output pad
Nout‧‧‧ NMOS threshold voltage signal
Rst1‧‧‧First reset signal
Rst2‧‧‧second reset signal
V REFP1 ‧‧‧First reference signal
V REFP2 ‧‧‧second reference signal
V REFN ‧‧‧ third reference signal
V P1 ‧‧‧ first comparison signal
V P2 ‧‧‧Second comparison signal
V N ‧‧‧ third comparison signal
Clock‧‧‧counting signal
P code ‧‧‧P type digital signal
N code ‧‧‧N type digital signal
PDOUTa‧‧‧P type front drive signal
PDOUTb‧‧‧P type front drive signal
PDOUTc‧‧‧P type front drive signal
V g4a ‧‧‧N type control signal
V g4b ‧‧‧N type control signal
V g4c ‧‧‧N type control signal
V g1a ‧‧‧P type control signal
Type control signal V g1b ‧‧‧P
V g1c ‧‧‧P type control signal
Detection voltage V g2 ‧‧‧
V g2REF ‧‧‧ reference detection voltage
I leakage ‧‧‧ leakage current
Comparison voltage V comp ‧‧‧ signal
Icomp‧‧‧compensation current
Vo‧‧‧Comparative potential
VDDIO‧‧‧ external voltage
Figure 1 is a block diagram of an output buffer for process, voltage, temperature and leakage current compensation in accordance with an embodiment of the present invention. Figure 2 is a circuit diagram of an output buffer in accordance with an embodiment of the present invention. Figure 3 is a circuit diagram of a leakage current compensation circuit in accordance with an embodiment of the present invention. Figure 4 is a circuit diagram of a first VDDIO detection circuit in accordance with an embodiment of the present invention. Figure 5 is a circuit diagram of a voltage level shifter in accordance with an embodiment of the present invention. Figure 6 is a circuit diagram of a PMOS threshold voltage detector in accordance with an embodiment of the present invention. Figure 7 is a circuit diagram of a PMOS threshold voltage process and temperature detector in accordance with an embodiment of the present invention. Figure 8 is a circuit diagram of an NMOS threshold voltage detector in accordance with an embodiment of the present invention.
100‧‧‧ Output buffer with process, voltage, temperature and leakage current compensation
200‧‧‧Processing voltage temperature sensor
210‧‧‧ PMOS threshold voltage detector
220‧‧‧ PMOS threshold voltage process and temperature detector
230‧‧‧ NMOS threshold voltage detector
300‧‧‧Determinator
310‧‧‧ bias generator
320‧‧‧First comparator
330‧‧‧Second comparator
340‧‧‧ third comparator
350‧‧‧Digital logic circuit
400‧‧‧Output buffer
500‧‧‧Leakage current compensation circuit
510‧‧‧Leakage current detector
520‧‧‧voltage controlled current source
Rst1‧‧‧First reset signal
Rst2‧‧‧second reset signal
Pout‧‧‧ PMOS threshold voltage signal
V REFP1 ‧‧‧First reference signal
VTout‧‧‧ PMOS threshold voltage process and temperature signal
V REFP2 ‧‧‧second reference signal
Nout‧‧‧ NMOS threshold voltage signal
V REFN ‧‧‧ third reference signal
V P1 ‧‧‧ first comparison signal
V P2 ‧‧‧Second comparison signal
V N ‧‧‧ third comparison signal
Clock‧‧‧counting signal
P code ‧‧‧P type digital signal
N code ‧‧‧N type digital signal
DOUT‧‧‧ transmission signal
PAD‧‧‧Output pad
V comp ‧‧‧Compare voltage signal
Icomp‧‧‧compensation current

Claims (13)

  1. An output buffer with process, voltage, temperature and leakage current compensation, comprising: a process voltage temperature sensor for detecting a PMOS threshold voltage signal, a PMOS threshold voltage process and a temperature signal, and an NMOS threshold a voltage signal; a determiner receiving the PMOS threshold voltage signal, the PMOS threshold voltage process and the temperature signal, and the NMOS threshold voltage signal, the determiner, the PMOS threshold voltage signal, the PMOS threshold voltage process, and the temperature signal The NMOS threshold voltage signal is compared with a plurality of reference signals to output a plurality of comparison signals, and the comparison signals are encoded into a P-type digital signal and an N-type digital signal via a digital logic circuit; and an output buffer having a a pre-driver circuit, a voltage generating circuit, a first VDDIO detecting circuit and an output stage, the pre-driver circuit receiving the P-type digital signal and the N-type digital signal, and the pre-driver circuit outputs a plurality of P a type of pre-drive signal and a plurality of N-type control signals, the voltage generating circuit receives the P-type pre-drive signals, and the voltage is generated And outputting a plurality of P-type control signals, the output stage receiving the P-type control signals and the N-type control signals, wherein the output stage has a P-type output transistor, and the P-type output transistor and the voltage generating circuit receive The first VDDIO detection circuit outputs a detection voltage; and a leakage current compensation circuit electrically connected to the P-type output transistor of the output stage, the leakage current compensation circuit has a leakage current detector and a a voltage-controlled current source, the leakage current detector receives the detection voltage, and the leakage current detector compares the detection voltage with a reference detection voltage and outputs a comparison voltage signal to the voltage-controlled current source, The voltage controlled current source provides a compensation current to the P-type output transistor according to the comparison voltage signal.
  2. The output buffer with process, voltage, temperature and leakage current compensation as described in claim 1, wherein the leakage current detector has a comparison circuit and a second VDDIO detection circuit, and the second VDDIO detection The circuit structure of the circuit is the same as the first VDDIO detection circuit, and the reference detection voltage is output by the second VDDIO detection circuit, and the comparison circuit receives the detection voltage and the reference detection voltage and outputs a comparison potential .
  3. An output buffer with process, voltage, temperature, and leakage current compensation as described in claim 2, wherein the comparison circuit has a first load transistor, a P-type differential pair, and a current mirror, the P The differential pair is electrically connected to the first load transistor, and the current mirror is electrically connected to the P-type differential pair, and the P-type differential pair receives the detection voltage and the reference detection voltage, wherein the detection When the voltage is greater than the reference detection voltage, the comparison potential is a high potential, and when the detection voltage is less than the reference detection voltage, the comparison potential is a low potential.
  4. An output buffer with process, voltage, temperature and leakage current compensation according to claim 3, wherein the leakage current detector has a first voltage dividing circuit and a first output circuit, the first point The voltage circuit is configured to provide a bias voltage to the comparison circuit and the first output circuit, the first output circuit has a second load transistor and a first output transistor, and the first output transistor receives the comparison potential When the comparison potential is high, the first output transistor is turned on to lower the comparison voltage signal to a low potential, and when the comparison potential is low, the first output transistor is turned off, so that the comparison voltage signal is Rise to high potential.
  5. An output buffer with process, voltage, temperature, and leakage current compensation as described in claim 4, wherein the leakage current detector further has a reset transistor electrically connected to the first An output transistor to reset the potential of the comparison voltage signal.
  6. The output buffer with process, voltage, temperature and leakage current compensation according to claim 4, wherein the voltage control current source has a first current mirror and a second current mirror, the first current mirror and The second current mirrors are overlapped with each other, the first current mirror receives the comparison voltage signal, the second current mirror is electrically connected to the P-type output transistor, and the second current mirror is configured to provide the compensation current to the P Type output transistor.
  7. An output buffer with process, voltage, temperature, and leakage current compensation as described in claim 1, wherein the output stage of the output buffer has an N-type output transistor, a plurality of P-type compensation transistors, and a plurality of N-type compensation transistors, each of the P-type compensation transistors receiving each of the P-type control signals to provide a compensation voltage to the P-type output transistors, and each of the N-type compensation transistors receives each of the N-type control signals to A compensation voltage is provided to the N-type output transistor.
  8. An output buffer with process, voltage, temperature, and leakage current compensation as described in claim 1, wherein the first VDDIO detection circuit has a second voltage dividing circuit, a determining circuit, and a second output. a circuit, a stacked inverter circuit, a third voltage dividing circuit, the second voltage dividing circuit receives an external voltage, and the second voltage dividing circuit provides a bias voltage to the determining circuit and the second output circuit The determining circuit receives the external voltage, and the determining circuit is configured to determine a potential of the external voltage to selectively turn on or off a second output transistor of the second output circuit to output the second output transistor An output voltage is output to the P-type output transistor via the stacked inverter circuit, and the third voltage dividing circuit is configured to bias the stacked inverter circuit.
  9. A leakage current compensation circuit for providing a compensation current to an output buffer, the leakage current compensation circuit comprising: a leakage current detector having a first voltage dividing circuit, a VDDIO detecting circuit, and a comparison a first output circuit, the first voltage dividing circuit is configured to provide a bias voltage to the comparison circuit and the first output circuit, the VDDIO detection circuit outputs a reference signal, and the comparison circuit receives the reference signal and The output buffer circuit outputs one of the detection voltages and outputs a comparison potential, the first output circuit receives the comparison potential and outputs a comparison voltage signal, wherein when the comparison potential is high, the comparison voltage signal is lowered to a low level. a potential, when the comparison potential is low, the comparison voltage signal rises to a high potential; and a voltage control current source receives the comparison voltage signal, and the voltage control current source provides the compensation current to the output according to the comparison voltage signal Buffer circuit.
  10. The leakage current compensation circuit of claim 9, wherein the comparison circuit has a first load transistor, a P-type differential pair and a current mirror, and the P-type differential is electrically connected to the transistor. a first load transistor, the current mirror is electrically connected to the P-type differential pair, and the P-type differential pair receives the detection voltage and the reference voltage, wherein when the detection voltage is greater than the reference voltage, the comparison potential When the detection voltage is lower than the reference voltage, the comparison potential is low.
  11. The leakage current compensation circuit of claim 10, wherein the first output circuit has a second load transistor and a first output transistor, and the first output transistor receives the comparison potential when the comparison When the potential is high, the first output transistor is turned on to lower the comparison voltage signal to a low potential. When the comparison potential is low, the first output transistor is turned off, and the comparison voltage signal is raised to a high potential.
  12. The leakage current compensation circuit of claim 9, wherein the voltage control current source has a first current mirror and a second current mirror, wherein the first current mirror and the second current mirror are overlapped with each other, The first current mirror receives the comparison voltage signal, and the second current mirror is electrically connected to the output buffer, and the second current mirror is configured to provide the compensation current to the output buffer.
  13. The leakage current compensation circuit of claim 9, wherein the first VDDIO detection circuit has a second voltage dividing circuit, a determining circuit, a second output circuit, and a stacked inverter circuit. a third voltage dividing circuit, the second voltage dividing circuit receives an external voltage, and the second voltage dividing circuit provides a bias voltage to the determining circuit and the second output circuit, the determining circuit receiving the external voltage, The determining circuit is configured to determine a potential of the external circuit to selectively turn on or off a second output transistor of the second output circuit, so that an output voltage of the second output transistor output is via the stacked inverter Output to the comparison circuit, the third voltage dividing circuit is configured to bias the stacked inverter.
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