TW201407958A - Self-calibration of output buffer driving strength - Google Patents

Abstract

An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output and a set of control inputs. the output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. the control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

Description

Automatically correct the drive capability of the output buffer

The present invention relates to digital circuits, and more particularly to output buffers for digital circuits.

An output buffer in an integrated circuit can be used to receive internal data at low currents and present to external loads at high current levels. The output timing of this output buffer varies with process boundary, voltage, and temperature (PVT) conditions. Changes in output timing due to process boundary, voltage, and temperature (PVT) conditions may reduce the correct range of data. At higher operating speeds, the reduced data correct interval is more likely to affect the performance or even reliability of the integrated circuit.

Accordingly, it is desirable to provide an output buffer that is insensitive to process boundary, voltage, temperature (PVT) conditions, and thus provides reliable performance of integrated circuits at high speeds.

The techniques described herein provide an integrated circuit that includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffering delay and adjusts its driving capability in response to a control signal applied to the set of control inputs. The control circuit is coupled to the set of control inputs of the output buffer, the control circuit generating the control signals using the first and second timing signals, and including a reference delay circuit for generating the first timing signal having a reference delay And a delayed analog power generating the second timing signal having a delay analog associated with the output buffer delay road.

Other objects and advantages of the present invention will be described in conjunction with the drawings in the following embodiments and the scope of the claims.

To further illustrate the various embodiments, embodiments of the present invention are provided with Figures 1 through 13 of the drawings. The drawings are a part of the disclosure of the present invention, and are mainly used to explain the embodiments, and the operation of the embodiments may be explained in conjunction with the related description of the specification. With reference to such content, those of ordinary skill in the art should be able to understand other possible embodiments and advantages of the present invention.

FIG. 1A shows a design example of a conventional output buffer 160. The output buffer includes an N-type MOS transistor 140 and a PMOS 120 connected in series. The NMOS 140 has a control terminal, a drain terminal and a source terminal and a ground potential connection. The PMOS 120 has a control terminal, a drain terminal connected to a source terminal and a fixed reference voltage VDD. An input signal IN is coupled in parallel with the control terminals of both transistors 120 and 140. An output signal OUT1 is coupled to the drain terminals of both transistors 120 and 140. A capacitor 180 represents the external load of this output buffer 160.

Fig. 1B shows a waveform diagram relating to the output buffer 160 in Fig. 1A, showing a waveform diagram of the input signal IN and the output signal OUT1. Tdat is the correct window for the input signal IN. The output buffer 160 can provide the same data correct window Tdat as the input signal IN to the output signal OUT1 under certain process boundary, temperature, and voltage conditions. However, process boundaries, temperatures, and voltages under other conditions At least one of them changes, the driving capability of the output buffer 160 is reduced/increased, the pulse rising and falling edges of the output signal OUT1 are lengthened/accelerated, and thus the data correct window of the output signal OUT1 is reduced from Tdat to Tvalid. The difference between Tvalid and Tdat for each pulse is twice that of Tinvalid, because its rising edge reduces Tinvalid and the falling edge also reduces Tinvalid.

FIG. 2A shows a block diagram of a sample integrated circuit 200. The example integrated circuit 200 includes an output buffer 260 and a control circuit 300. The output buffer 260 includes a signal input, a signal output, and a set of control inputs. The output buffer 260 has an output buffer stage and a drive capability enable block tunable in response to a control signal CTRL applied to the set of control inputs. An input signal IN is coupled to the signal input of the output buffer 260. An output signal OUT is coupled to the signal output of the output buffer 260. A capacitor 280 is coupled to the signal output of the output buffer 260 to represent the capacitive load of the output buffer 260. The control circuit 300 is electrically coupled to a reference signal REF.

The arrows in the first transistor 240 and the second transistor 220 indicate that the driving capability of the output buffer 260 is adjustable. The marking of the two resistors in series with the first transistor 240 and the second transistor 220 indicates that the driving capability of the output buffer can be adjusted using the output resistance.

This output buffer 260 includes a plurality of output drivers. Each of the output buffers 260 includes a first transistor 240 and a second transistor 220. The first transistor 240 of the output buffer 260 has a first conductive terminal electrically coupled to a first fixed reference voltage GND, and a second conductive terminal electrically coupled to an output terminal of the output buffer 260. And a control terminal is electrically coupled to the input terminal of the output buffer 260. The first transistor has a first channel type State, in one application, includes an N-type metal oxide semi-transistor (NMOS).

The second transistor 220 of the output buffer 260 has a first conductive terminal electrically coupled to a second fixed reference voltage VDD, and a second conductive terminal electrically coupled to the output terminal of the output buffer 260. And a control terminal is electrically coupled to the input terminal of the output buffer 260. The second transistor has a channel type opposite the channel pattern of the first transistor and, in one application, a P-type metal oxide semiconductor (PMOS).

Figure 2B shows an output buffer 260 comprising a plurality of parallel output drivers. The control signal CTRL enables and disables the selected output driver to adjust the drive capability of the output buffer 260. The input signal IN is provided to a plurality of parallel output drivers. How to select the output driver for the control signal CTRL will be described in conjunction with Figure 9.

In Figure 2B, each of the output drivers is a 180 ohm output driver, and four such output drivers are connected in parallel in each of the output buffers 260. According to Ohm's law, the drive capability of the output buffer 260 will decrease/increase with the higher/lower overall resistance of the output buffer 260, respectively. The overall resistance of the output buffer 260 is determined by how many output drivers are turned on. In general, the overall resistance of the output buffer 260 is the sum of the resistances of each of the open output drivers. If the output drivers have the same resistance, then the sum of the resistors of all output drivers is the number of resistors that open each of the output drivers divided by the number of open output drivers. For example, for a 180 ohm output driver, if the 1, 2, 3, or 4 output drivers are turned on, the overall resistance of the output buffer 260 is 180, 90, 60, or 45 ohms, respectively. Therefore, the overall resistance output buffer 260 with 45 ohms has the strongest driving capability and has an overall resistance of 180 ohms. Output buffer 260 has the weakest drive capability.

The resolution of the adjustment drive capability is related to the number of output drivers in each output buffer 260. A larger number of output drivers have higher resolution. When there are four output drivers, the drive capability adjustment of this output buffer can have four classes. Assuming that each of the output drivers has the same size, when there are 16 output drivers, the drive capacity adjustment of this output buffer can have 16 classes. In other embodiments, the size of the drive can vary, including, for example, a 1x driver, a 2x driver, a 4x driver, and an 8x driver, and the decoding circuitry can be used to select a driver combination with optimally adjusted overall drive capability. Moreover, in other embodiments, the driver can also use analog control signals to adjust its drive capability.

Figure 2C shows a waveform diagram associated with output buffer 260 in Figure 2A. For the purpose of comparison, it shows a waveform diagram of the same input signal IN and output signal OUT1 as in FIG. 1B. The waveform diagram of the output signal OUT1 generated by the output buffer 260 shown in the figure has a data correct window Tvalid2. Tvalid2 is adjusted by output buffer 260 according to specific process boundary, voltage, temperature (PVT) conditions. As a result, Tvalid2 is wider than the narrower data correct window Tvalid1 produced by output signal OUT1, which is not adjusted by output buffer 160 according to a particular process boundary, voltage, temperature (PVT) condition, in FIG. 1B. Tvalid2 is closer to Tdat than Tvalid1 but still twice the difference between Tinvalid2 and Tdat, because its rising edge reduces Tinvalid2 and the falling edge also reduces Tinvalid2.

Fig. 3 is a block diagram of a control circuit 300 used in the integrated circuit 200 in Fig. 2A. This control circuit 300 is coupled to the set of control inputs of the output buffer 260. The control circuit 300 uses the first and second time The sequence signals TS1 and TS2 generate control signals and include a reference delay circuit 400 that generates a first timing signal TS1 having a reference delay and a delay associated with the output buffer delay that produces a second timing signal TS2 having an analog delay. Analog circuit 310.

The reference delay circuit 400 is responsive to a reference signal to generate a first timing signal TS1 having a reference delay, and wherein the reference delay circuit 400 is substantially insensitive to process boundary, voltage, temperature (PVT) conditions. The delay analog circuit 310 generates a second timing signal TS2 having an analog delay at its output in response to its input reference signal REF, and wherein the delay simulation is a process boundary, voltage, temperature (PVT) condition or process boundary, voltage, temperature A change in one of the (PVT) results in a corresponding output buffer delay.

The control circuit 300 also includes a delay line 320 and logic 330. The logic 330 has a first input terminal electrically coupled to the first timing signal TS1 and has a second input terminal electrically coupled to the second timing signal TS2 via the delay line 320. This logic 330 compares the arrival time of the first timing signal TS1 from the reference delay circuit 400 with the arrival time of the second timing signal TS2 of the self-delay analog circuit 310 to generate the control signal CTRL.

This reference signal REF must have similar electrical characteristics at input signal IN and output buffer 260 such that reference signal REF in conjunction with delay analog circuit 310 can produce timing associated with the timing of this output buffer 260. These electrical characteristics can include the timing and voltage amplitude of the active edges. The effective edge can be a rising edge or a falling edge. This reference signal REF can be generated from sources internal or external to the integrated circuit. The reference signal REF can have a frequency or frequency range suitable for self-output drive capability of the output buffer in an integrated circuit. Correction.

Fig. 4 is a block diagram of the reference delay circuit 400 in Fig. 3. The reference delay circuit 400 includes a first delay sub-circuit 410 having an input terminal electrically coupled to the reference signal REF and having an output terminal. The reference delay circuit 400 also includes a second delay sub-circuit 460 having an input terminal electrically coupled to the output terminal of the first delay sub-circuit 410 and having an output terminal electrically coupled to the first timing signal TS1. Pick up.

The first delay sub-circuit 410 can include a resistor-capacitor (RC) delay circuit, and the second delay sub-circuit 460 can include a MOS delay circuit. Alternatively, the first delay sub-circuit 410 may include a MOS delay circuit, and the second delay sub-circuit 460 may include a resistor-capacitor (RC) delay circuit.

The resistor-capacitor (RC) delay circuit may include a PMOS transistor 412 and an NMOS transistor 414 connected in series. The PMOS 412 has a control terminal, a drain terminal connected to a source terminal and a second reference voltage VDD2. The NMOS 414 has a control terminal, a drain terminal and a source terminal. The control terminals of the PMOS transistor 412 and the NMOS transistor 414 are electrically coupled in parallel with the input terminals of the first delay sub-circuit 410. The PMOS transistor 412 and the drain terminal of the NMOS transistor 414 are electrically coupled to the output terminal of the first delay sub-circuit 410 and a signal 450. A second NMOS transistor 416 has a control terminal electrically coupled to a bias voltage, a drain terminal coupled to the source terminal of the NMOS transistor 414, and a source terminal coupled to a ground potential. This bias voltage can be generated by an analog circuit and provides a certain current. A capacitor 418 is coupled to the PMOS transistor 412 and the NMOS terminal of the NMOS transistor 414 via signal 450.

The MOS delay circuit can include a plurality of delay elements connected in series. Signal 450 is coupled to the input terminal of first delay element 462 of the plurality of series connected delay elements. An output terminal of the last one of the plurality of series connected delay elements 468 is coupled to an output terminal of the second delay sub-circuit 460. As described in FIGS. 5A-5C, the resistor-capacitor (RC) delay circuit and the MOS delay circuit compensate each other such that the overall delay through the reference delay circuit 400 is at varying process boundaries, voltages, and temperatures (PVT). Under the conditions, the value remains roughly constant.

Figures 5A-5C include a set of illustrations depicting how the reference delay circuit in Figure 4 compensates for timing variations due to varying process boundary, voltage, temperature (PVT) conditions. Nominal process boundary, voltage, temperature (PVT) conditions include nominal process boundaries, nominal voltages, and nominal temperatures. A nominal voltage is associated with the integrated circuit. For example, the nominal voltage in an integrated circuit may be 3.3V and the nominal voltage in another integrated circuit may be 1.5V. A nominal temperature can be 25 degrees Celsius. A nominal process boundary can be typical-typical (TT). The process boundary will be described in Figure 5C.

One nominal delay of this delay analog circuit 310 is the delay through this delay analog circuit 310 under nominal process boundary, voltage, temperature (PVT) conditions. In general, the delay through this delay analog circuit 310 will vary with process boundary, voltage, temperature (PVT) conditions and is greater or less than the nominal delay. The overall delay of the reference delay circuit 400 preferably remains substantially constant under varying process boundary, voltage, temperature (PVT) conditions, as described in Figures 5A-5C below. A noun used to describe a reference delay circuit, a reference to a time-delayed reference for self-correction of the output buffer output drive capability Considering the delay circuit 400, if the delay of the reference delay circuit 400 is over a period of time in a variable process boundary, voltage, temperature (PVT) condition, relative to a process boundary of an analog circuit such as the output buffer, Voltage, temperature (PVT) conditional components are small at the same process boundary, voltage, temperature (PVT) conditions, and can be referred to as "roughly fixed" or the circuit is "substantially insensitive." In reality, a reference delay circuit should provide a reference delay that is less sensitive to changes in one or more of the process boundary, voltage, temperature (PVT) than the analog circuit of the output buffer being calibrated. A less sensitive reference delay can improve its performance even if the delay of the reference delay circuit 400 is not constant.

Figure 5A shows that as the temperature increases, the RC delay through the RC delay circuit decreases, while the MOS delay through the MOS delay circuit increases. Therefore, the net effect of the RC delay reduction and the MOS delay increase due to the temperature variation is such that the overall delay of the RC delay circuit and the MOS delay circuit is substantially constant, resulting in the circuit being substantially insensitive to temperature variations.

Fig. 5B shows that as the supply voltage increases, the RC delay through the RC delay circuit increases, while the MOS delay through the MOS delay circuit decreases. Therefore, the net effect of the RC delay reduction and the MOS delay increase due to variations in the supply voltage is such that the overall delay of the RC delay circuit and the MOS delay circuit is substantially constant, resulting in the circuit being substantially insensitive to fluctuations in the supply voltage.

Figure 5C shows the effect of process boundaries on RC delay and MOS delay. The process boundary represents the variation of the parameters in the integrated circuit process. Circuits fabricated in different process boundaries can operate at faster or slower speeds. A method for naming process boundaries to N-channel MOS The boundary is represented by the first letter and the P channel MOS boundary is represented by the second letter. In general, letters such as S, T, and F represent slow, typical, and fast boundaries, respectively. For example, the FF boundary represents a fast N-channel MOS device and a fast P-channel MOS device.

Figure 5C shows that the RC delay through the RC delay circuit in the slow-slow (SS) process boundary is less than the RC delay through the RC delay circuit in the fast-fast (FF) process boundary, while in the slow-slow (SS) process The MOS delay through the MOS delay circuit in the boundary is greater than the MOS delay through the MOS delay circuit in the fast-fast (FF) process boundary. Therefore, the net effect of the RC delay increase and the MOS delay reduction due to variations in the process boundary is such that the overall delay of the RC delay circuit and the MOS delay circuit is substantially constant, resulting in the circuit being substantially insensitive to variations in process boundaries.

If the first timing signal TS1 is within a time interval between the first delay threshold and the second delay threshold with respect to the second timing signal TS2, the control signal CTRL has a first value; if the first timing signal TS1 is relative to The second timing signal TS2 occurs earlier than the first delay threshold, and the control signal CTRL has a second value; if the first timing signal TS1 occurs later than the second delay threshold with respect to the second timing signal TS2, then control Signal CTRL has a third value.

In an embodiment, the first value may indicate that there is no need to increase or decrease the drive capability of the output buffer 260. The second value may indicate that the drive capability of the output buffer 260 needs to be increased, while the third value may indicate that the drive capability of the output buffer 260 needs to be reduced. This control circuit 300 continuously observes process boundary, voltage, temperature (PVT) conditions and generates a control signal CTRL. Output buffer 260 then adjusts its output strength based on the value of control signal CTRL.

Fig. 6 is a more detailed circuit diagram of the control circuit 300 in Fig. 3. In addition to this reference delay circuit 400 and delay analog circuit 310, control circuit 300 also includes a delay line 320 and logic 330. The delay line 320 has an input coupled to the delay analog circuit 310. The delay line 320 has a first junction TP1 corresponding to a first delay threshold and a second junction TP2 corresponding to a second delay threshold. The logic 330 is coupled to the first connector TP1 and the second connector TP2 of the delay line 320 and coupled to the reference delay circuit 400. This logic 330 produces a control signal CTRL.

The delay line 320 includes a first delay buffer circuit 610 and a second delay buffer circuit 620. The first delay buffer circuit 610 has an input terminal electrically coupled to the output terminal of the delay analog circuit 310 via the second timing signal TS2. The second delay buffer circuit 620 has an input terminal electrically coupled to the output terminal of the first buffer circuit 610 via the first connector TP1, and has an input terminal electrically coupled to the second connector TP2.

The first delay buffer circuit 610 has a first time delay through the first delay buffer circuit. The second delay buffer circuit 620 has a second time delay through the second delay buffer circuit. The first delay buffer circuit 610 performs signal recovery to make the rising or falling edge of the second timing signal TS2 steeper. This makes the first delay time as short as possible. The second delay defines the timing interval of logic 330. This timing interval can be determined by measuring the delay from the rising edge of the first joint TP1 to the next rising edge of the second joint TP2, or between their respective falling edges. The second delay buffer circuit 620 can include, for example, 8 or 10 series inverters. If these inverters have the same delay, the overall delay is doubled if the number of inverters in the second delay buffer circuit 620 is doubled. Timing will be described in Figures 11~13 The timing relationship between the interval, the first timing signal TS1, and the second timing signal TS2.

The logic 330 in the control circuit 300 includes a first storage circuit 615, a second storage circuit 625, and a decoder 650. The first storage circuit 615 has a clock input terminal C electrically coupled to the reference delay circuit 400 to receive the first timing signal TS1, and a data input terminal D is electrically coupled to the first connector TP1 of the delay line 320, and Has an output terminal. The second storage circuit 625 has a clock input terminal C electrically coupled to the reference delay circuit 400 to receive the first timing signal TS1, a data input terminal D and the second connector TP2 of the delay line 320 are electrically coupled, and Has an output terminal. This decoder 650 is coupled to the outputs of the first storage circuit 615 and the second storage circuit 625 to generate a control signal CTRL.

For example, the storage circuit of the first storage circuit 615 or the second storage circuit 625 stores the logic level of the signal coupled to the data input terminal D when the clock signal coupled to the clock input terminal C is at the rising edge or the falling edge. And at its output terminal Y continues to output its logic level until the next rising edge or falling edge of the clock signal to which its clock input terminal C is coupled.

As shown in FIG. 6, the reduction circuit 326 of the output buffer 260 is located in the delay analog circuit 310, and includes the first reduction circuit 324 and the second transistor 220 of the first transistor 240 of the output buffer 260. The second reduction circuit 322.

The first reduction circuit 324 has a first conductive terminal electrically coupled to the first fixed reference voltage GND, the second conductive terminal is electrically coupled to the output terminal of the delay analog circuit 310, and the control terminal and the delayed analog power The input terminal of the path 310 is electrically coupled. The second reduction circuit 322 has a first conductive terminal electrically coupled to the second fixed reference voltage VDD2, the second conductive terminal is electrically coupled to the output terminal of the delay analog circuit 310, and the input of the control terminal and the delay analog circuit 310. The terminal is electrically coupled. For ease of design, the second fixed reference voltage VDD2 to the output buffer 260 (FIG. 2A) may be equal to the fixed reference voltage VDD. In addition, if the delay analog circuit 310 (FIG. 6) can simulate the behavior of the output buffer 260 (FIG. 2A), the second fixed reference voltage VDD2 can also be different from the fixed reference voltage VDD.

As shown in FIG. 6, the first reduction circuit 324 and the second reduction circuit 322 of the delay analog circuit 310 include a reduced NMOS transistor and a reduced PMOS transistor, respectively outputting the first transistor 240 in the buffer 260 and The second transistor 220. The reference signal REF is coupled to the input terminal of the delay analog circuit 310. The second timing signal TS2 is coupled to the output terminal of the delay analog circuit 310.

The delay analog circuit 310 also includes a capacitor 328 coupled to the output terminal of the delay analog circuit 310. This capacitor 328 has a reduced capacitance value that will be represented by capacitor 280 (Fig. 2A) at the capacitive load of the output terminal of output buffer 260. For example, capacitor 280 at the output terminal of output buffer 260 in FIG. 2A has a capacitance value of 30 pF and output buffer 260 has a resistance value of 30 ohms, resulting in a time constant of 900 pS. Correspondingly, in Fig. 6, the capacitor 328 at the output terminal of the reduction circuit 326 is reduced to a capacitance value of 5 pF and the resistance value of the reduction circuit 326 is amplified to 180 ohms to simulate a time constant of 900 pS.

Figure 7 is an example truth table associated with control circuit 300 of Figure 6, showing an example decoding operation. When signals FY1 and FY2 The control signal CTRL indicates that the driving capability (intensity) of the output buffer 260 does not need to be increased or decreased at the logic high level and the low level, respectively. When both signals FY1 and FY2 are at a logic high level, control signal CTRL indicates that the drive capability of output buffer 260 needs to be reduced. When both signals FY1 and FY2 are at a logic low level, control signal CTRL indicates that the drive capability of output buffer 260 needs to be increased.

The control circuit 300 shown in FIG. 6 and the truth table shown in FIG. 7 show an embodiment of the technology disclosed herein. There are many variations to this embodiment for those skilled in the art. For example, the first storage circuit 615 and the second storage circuit 625 can store data when the clock input terminal C descends the edge instead of the rising edge. The decoder 650 can use different decoding mechanisms, such as a decoding mechanism that does not change the driving capability when the signals FY1 and FY2 are at a logic low level and a high level, respectively, rather than at logic high and low levels, respectively.

The control circuit 800 in Fig. 8 is an alternative embodiment of the control circuit 300 in Fig. 6. The description of delay line 320 and logic 330 in FIG. 6 is also generally applicable to control circuit 800 of FIG. The alternate control circuit 800 includes a timing interval indicating that a first timing signal in the plurality of timing intervals occurs relative to the second timing signal, and the logic 900 generates a control signal CTRL in response to the indicated timing interval.

The alternate control circuit 800 includes a delay line 880 and logic 890. The delay line 880 has an input coupled to the delay analog circuit 310 (FIG. 6) via the second timing signal TS2. The delay line 320 has a plurality of connectors. For example, a connector TP1, TP2, TP3, and TP4 respectively correspond to a plurality of timing intervals. This logic 890 is connected to a plurality of connections on the delay line 880. The head is coupled and coupled to the reference delay circuit 400 (FIG. 6) via the first timing signal TS1. This logic 890 generates a control signal CTRL.

The plurality of timing intervals and the plurality of joints provide more precise control of the adjustment output drive capability than the single timing interval and the two joints described in FIG. The replacement control circuit 800 includes a first delay buffer circuit 810, a second delay buffer circuit 820, a first storage circuit 815, a second storage circuit 825, and a decoder 850, respectively, and a first delay buffer circuit 610 in FIG. 6, The second delay buffer circuit 620, the first storage circuit 615, the second storage circuit 625, and a decoder 650 correspond to each other. The signals TP1, TP2, FY1, and FY2 in Fig. 8 correspond to TP1, TP2, FY1, and FY2 in Fig. 6, respectively.

In addition, the alternative control circuit 800 includes a third buffer circuit 830, a fourth buffer circuit 840, a third storage circuit 835, and a fourth storage circuit 845. The third buffer circuit 830 has an input terminal electrically coupled to the second timing signal TS2 and has an output terminal electrically coupled to the third connector TP3. The first buffer circuit 810 has an input terminal electrically coupled to the third connector TP3, and has an output terminal electrically coupled to the first connector TP1. The second buffer circuit 820 has an input terminal electrically coupled to the first connector TP1 and has an output terminal electrically coupled to the second connector TP2. The fourth buffer circuit 840 has an input terminal electrically coupled to the second connector TP2, and has an output terminal electrically coupled to the fourth connector TP4.

The third buffer circuit 830 performs signal recovery to make the rising or falling edge of the second timing signal TS2 steeper. This makes the delay time by the third buffer circuit 830 as short as possible.

The first time interval of the plurality of time intervals is passed through the second buffer The delay time of circuit 820 is defined. This first time interval may be determined by the delay from the rising edge of the first joint TP1 to the next rising edge of the second joint TP2 or between their respective falling edges.

The second timing interval of the plurality of timing intervals is defined by the delay time through the first buffer circuit 810. This second time interval may be determined by the delay from the rising edge of the third joint TP3 to the next rising edge of the fourth joint TP4 or between their respective falling edges. For example, if the first buffer circuit 810, the second buffer circuit 820, and the fourth buffer circuit 840 having four inverters, eight inverters, and four inverters have the same delay, the second timing The interval will be twice as wide as the first time interval.

More timing intervals can be defined by the delay time of adding more pairs of series buffer circuits. With one timing interval, the drive capability of the output buffer 260 can be increased or decreased by one step in response to detecting a timing interval. With two timing intervals, the drive capability of the output buffer 260 can be increased or decreased by two steps in response to detecting two timing intervals. In general, multiple timing intervals can take multiple steps and more accurately adjust the drive capability of the output buffer.

Similar to the control circuit 300, the first storage circuit 815 has a clock input terminal C electrically coupled to the first timing signal TS1, a data input terminal D is electrically coupled to the first connector TP1, and has an output terminal. . The second storage circuit 825 has a clock input terminal C electrically coupled to the first timing signal TS1, a data input terminal D electrically coupled to the second connector TP2, and an output terminal.

In addition, in the alternative control circuit 800 shown in FIG. 8, the third storage circuit 835 has a clock input terminal C and a first timing signal. The TS1 is electrically coupled, and the data input terminal D is electrically coupled to the third connector TP3 and has an output terminal electrically coupled to the signal FY3. The fourth storage circuit 845 has a clock input terminal C electrically coupled to the first timing signal TS1, a data input terminal D is electrically coupled to the fourth connector TP4, and has an output terminal electrically coupled to the signal FY4. Pick up.

This logic 890 has a decoder 850. The decoder 850 is coupled to the outputs of the first storage circuit 815, the second storage circuit 825, the third storage circuit 835, and the fourth storage circuit 845 to generate a control signal CTRL. The decoder 850 generates a control signal CTRL based on the signals provided by the decoding of the four storage circuit output terminals. This control signal CTRL indicates one of three conditions: the output drive capability of one or more of the output buffers 260 is to be increased, decreased, or not changed.

Figure 9 shows an example circuit diagram of the drive capability adjustment of a control output buffer. In one embodiment, the output buffer 260 has a plurality of parallel output drivers 960, such as output drivers 961, 962, 963, and 964, and an output driver in the plurality of parallel output drivers 960 that enable and disable the control signal CTRL. To adjust the output drive capability of the output buffer 260.

The control signal CTRL includes a leftward offset signal SL and a rightward offset signal SR. The leftward offset signal SL and the rightward offset signal SR are coupled to the multi-order left-to-right offset register 910. For simplicity of description, the example left-to-right offset register 910 in FIG. 9 has a four-bit width. However, other applications such as 8, 16, 32, 64 bits, etc. can also be used. As an example, the left-to-right offset register 910 has a four-bit width output terminal coupled to the four-bit enable signal SET<1:4>. The four tristate buffers are coupled to the multi-order left-to-right offset register 910 and the input signal IN. This tristate buffer can be Reverse or non-inverting buffer. Each of the tristate buffers has a data input coupled to the input signal IN, a control input coupled to the corresponding enable signal, and an output terminal. When the tristate buffer is turned on by a corresponding bit of the four bit enable signal SET<1:4> of its control input, the tristate buffer transmits the input signal IN to its output terminal. For example, when the tristate buffer 923 is turned on by the corresponding bit SET<3> of its control input, the tristate buffer 923 transmits the input signal IN to its output terminal.

As an example, the initial state of the four-bit wide signal SET<1:4> is "1100", where "1" stands for "on" and "0" stands for "off" to turn the output buffer on or off. Corresponding output driver of 260. In an alternative embodiment, "1" may represent "off" and "0" represents "on". When having an initial state of "1100", the two output drivers in this output buffer 260 are turned on and the two output drivers are turned off. For two 180 ohm output drivers, the overall resistance of this output buffer 260 is therefore 90 ohms.

When the logic 330 detects the need to increase the output drive capability, the logic generates a pulse at the signal SR. In response, the state of the four-bit wide signal SET<1:4> changes from "1100" to "1110", and one of the output buffers 260 is turned on and the three output drivers are turned off. For three 180 ohm output drivers, the overall resistance of this output buffer 260 is therefore 60 ohms. As a result, the output drive capability increases due to the decrease in the overall resistance value.

When the logic 330 detects the need to reduce the output drive capability, the logic generates a pulse at the signal SR. In response, the state of the four-bit wide signal SET<1:4> changes from "1100" to "1000", and three output drivers in the output buffer 260 are turned on and an output driver shut down. For a 180 ohm output driver, the overall resistance of this output buffer 260 is therefore 180 ohms. As a result, the output drive capability is reduced due to an increase in the overall resistance value.

When the output buffer 260 is not in an operation mode or does not drive a signal, the four-bit wide signal SET<1:4> can be changed to adjust the output drive capability of the output buffer 260 to avoid the output buffer. Switching noise. In an embodiment, when the data line is turned off, for example, an integrated circuit is in an intensity adjustment mode instead of an operation mode, the four-bit wide signal SET<1:4> can be changed to adjust the output. The output drive capability of the buffer 260. In an operational mode, this output buffer is enabled only when needed, and the signals SET<1:4> are not allowed to be changed during signal transmission. The integrated circuit must receive the command at a command cycle before the output buffer is enabled. Some commands may need to specify which output buffer is enabled. In a second embodiment, the signal SET<1:4> may be allowed to be changed at the command cycle to cause the output buffer to self-correct for its drive capability. In a third embodiment, the signal SET<1:4> may also be allowed to be changed when the integrated circuit is deselected or not selected.

FIG. 10 shows a wafer arrangement diagram of the example integrated circuit 200 of this example. The integrated circuit 200 includes a write terminal configured to connect the circuit to the integrated circuit 200, and wherein the output of the output buffer is coupled to the write terminal. The write terminal may include a wire pad of the integrated circuit package, and the "bump" of the flip chip package is configured to stack the output of the output buffer by off-chip by stacking the via holes in the integrated circuit and other terminals. communication. The integrated circuit 200 in this example includes a memory array 1020 coupled to an output buffer 260 via a wire pad 1040. In other examples, the integrated circuit 200 can include a processor, logic, analog power Roads and the like exist alone or in combination with other integrated circuit components. Circle 1090 shows that the output of output buffer 260 is coupled to write terminal 1080.

This integrated circuit 200 has a plurality of output buffers including an output buffer 260. These output buffers adjust the output drive capability of the output buffer based on the control signal CTRL. These control signals CTRL are generated by control circuit 300 to control the plurality of output buffers. These control signals CTRL generated by a control circuit 300 can be sent to a group control input of more than one of the output buffers of the plurality of output buffers. As shown in FIG. 2A, a control circuit 300 is coupled to an output buffer 260. In general, one control circuit 300 can be coupled to one or more output buffers 260. Additionally, integrated circuit 200 can have multiple control circuits, each coupled to one or more output buffers. The number of output buffers coupled to one control circuit may be different from the number of output buffers coupled to another control circuit.

Figures 11 through 13 show a method of controlling an output buffer in which the output buffer has an output buffer delay. The method includes generating a first timing signal TS1 having a reference delay D1 and generating a second timing signal TS2 having an analog delay D2 associated with an output buffer delay. The method also includes adjusting an output drive capability of the output buffer in response to the first timing signal TS1 and the second timing signal TS2.

The waveforms shown in Figs. 11 to 13 are related to the decoding operation of the control circuit 300 in Fig. 6 and the truth table in Fig. 7. For the sake of simplicity of description, the signal transition occurs at the rising edge of Figures 11-13. It will also be appreciated by those skilled in the art that the techniques of the present invention can also be applied to falling edges.

Accordingly, the method disclosed herein includes using a reference delay circuit 400 responsive to generating a reference signal REF of the first timing signal TS1, and wherein the reference delay circuit 400 is substantially for process boundary, voltage, temperature (PVT) conditions, or at least Not sensitive to one of the process boundaries, voltage, and temperature. The method also includes using a delay analog circuit 310 in response to generating a reference signal REF of the second timing signal TS2, and wherein the analog delay is associated with a process boundary, voltage, temperature (PVT) condition or at least a process boundary, voltage, The change in output buffer delay caused by one of the temperatures is related.

The method further includes generating a control signal CTRL in response to the first timing signal TS1 and the second timing signal TS2, and using the control signal CTRL to adjust an output drive capability of the output buffer. If the first timing signal TS1 is within the time interval W1 between the first delay threshold and the second delay threshold relative to the second timing signal TS2, the control signal CTRL has a first value, if the first timing signal TS1 Relative to the second timing signal TS2 occurring earlier than the first delay threshold, the control signal CTRL has a second value, if the first timing signal TS1 occurs later than the second delay threshold with respect to the second timing signal TS2, then The control signal CTRL has a third value.

The method can include coupling the one of the first timing signal and the second timing signal using the delay line 320. The delay line 320 has a first junction TP1 corresponding to a first delay threshold and a second junction TP2 corresponding to a second delay threshold. The method can include generating a control signal CTRL using the first joint TP1 of the delay line 320 and a second joint TP2. The time interval W1 is between a first delay threshold corresponding to the first joint TP1 and a second delay critical corresponding to the second joint TP2.

The method also includes providing a clock to the first timing signal TS1 a storage circuit 615, the data input of the first storage circuit 615 is input to the first connector TP1 of the delay line, the second timing signal TS2 is used to provide the clock to the second storage circuit 625, and the data input of the second storage circuit 625 is received by the delay line. The second connector TP2, and the outputs of the first storage circuit 615 and the second storage circuit 625 are used to generate the control signal CTRL.

In Figures 11-13, at time t0, all of the signals in the waveform in Figure 11 are at a logic low level. At time t1, the reference signal REF as indicated by the rising edge 1110 transitions from a logic low level to a logic high level. At time t2, in response to rising edge 1110, after reference delay D1 is passed through reference delay circuit 400, first timing signal TS1, as indicated by rising edge 1120, transitions from a logic low level to a logic high level. Also in response to rising edge 1110, after analog delay D2 passes reference delay circuit 400, second timing signal TS2, as indicated by rising edge 1130, transitions from a logic low level to a logic high level. In response to rising edge 1130 of second timing signal TS2, first junction TP1 and second junction TP2 transition from a logic low level to a logic high level as indicated by rising edges 1140 and 1150, respectively.

At the rising edge 1120 of the first timing signal TS1, the first storage circuit 615 and the second storage circuit 625 provide clocks to the first header TP1 and the second header TP2, respectively. The logic levels received at the data input terminal D of the first connector TP1 and the second connector TP2 are supplied to the outputs FY1 and FY2 of the first storage circuit 615 and the second storage circuit 625, respectively.

As shown in FIG. 11, the rising edge 1120 of the first timing signal TS1 occurs at a first delay threshold corresponding to the rising edge 1140 of the first joint TP1 and a second delay corresponding to the rising edge 1150 of the second joint TP2. Within the time interval between the thresholds W1. Therefore, at time t2, the first connector TP1 is at a logic high level and the second connector TP2 is at a logic low. Level. As a result, the output FY1 of the first storage circuit 615 transitions to a logic high level after the rising edge 1160 of time t2, while the output FY2 of the second storage circuit 625 remains at the logic low level.

In an example shown in the truth table of Figure 7, when FY1 is at a logic high level and FY2 is at a logic low level, the drive capability of the output buffer does not need to be increased or decreased. Therefore, this method can generate a control signal having a first value to indicate that the driving capability of the output buffer does not need to be increased or decreased. For example, the control signal may include a leftward offset signal SL and a rightward offset signal SR, as described in FIG. The first value can be represented by the left offset signal SL and the rightward offset signal SR without a pulse.

As shown in FIG. 12, the first timing signal TS1 occurs at a first delay threshold corresponding to the rising edge 1140 of the first joint TP1 with respect to the second timing signal TS2. Therefore, at time t2, the first tap TP1 is at a logic low level and the second tap TP2 is at a logic low level. As a result, at time t2, the output FY1 of the first storage circuit 615 and the output FY2 of the second storage circuit 625 are both maintained at a logic low level.

In an example shown in the truth table of Figure 7, when both FY1 and FY2 are at a logic low level, the drive capability of the output buffer needs to be increased. Therefore, this method can generate a control signal having a second value to indicate that the drive capability of the output buffer needs to be increased. For example, the second value may have a pulse to the left offset signal SL and a pulse to the right offset signal SR.

As shown in FIG. 13, the first timing signal TS1 occurs later than the second delay signal corresponding to the rising edge 1150 of the second joint TP2 with respect to the second timing signal TS2. Therefore, at time t2, the first joint TP1 It is a logic high level and the second connector TP2 is a logic high level. As a result, at time t2, the output FY1 of the first storage circuit 615 and the output FY2 of the second storage circuit 625 are at a logic high level at the rising edge 1160 and the rising edge 1170, respectively.

In an example shown in the truth table of Figure 7, when both FY1 and FY2 are at a logic high level, the drive capability of the output buffer needs to be reduced. Therefore, this method can generate a control signal having a third value to indicate that the drive capability of the output buffer needs to be reduced. For example, the third value may be represented by a pulse having both the leftward offset signal SL and the rightward offset signal SR.

The method also includes determining when a first timing signal occurs relative to the second timing signal over a time interval of the plurality of time intervals, and generating a control signal in response to the determined time interval. For example, the first time interval can be defined by the delay of the second buffer circuit 820 in FIG. 8, and the second time interval can be passed through the first buffer circuit 810, the second buffer circuit 820, and The overall delay definition of the third buffer circuit 830. The method also includes generating a control signal in response to the first time interval, or the second time interval, or both.

The method also includes using a delay line coupled to one of the first timing signal and the second timing signal, and having a plurality of joints corresponding to the plurality of time intervals, and generating a control signal using the plurality of joints. For example, the delay line 880 is coupled to the second timing signal TS2 and has a plurality of connectors TP1, TP2, TP3, and TP4 as shown in FIG. The delay between TP1 and TP2 corresponds to the first time interval, and the delay between TP3 and TP4 corresponds to the second time interval.

These output buffers include a plurality of parallel output drivers The output driver of the control signal enable and disable can be used to adjust the drive capability of the output buffer. As shown in FIG. 9, output evaluator 260 includes a plurality of parallel output drivers 960, such as drivers 961, 962, 963, and 964. This method can use the control signal CTRL including the left shift signal SL and the right shift signal SR to enable and disable the selected output driver to adjust the drive capability of the output buffer.

These output buffers may include an output of the output buffer to the write terminal, including a method in which the write terminal is configured to connect the circuit to an integrated circuit other than the integrated circuit 200. As shown in FIG. 10, the integrated circuit 200 includes a memory array 1020 coupled to, for example, an output buffer 260. The output buffer 260 is located above the integrated circuit 200 including the write terminal 1080 configured to connect the circuit to the integrated circuit 200. This method can present the output of output buffer 260 to this write terminal 1080.

The method can include using a control signal generated by control circuit 300 to adjust the drive capability of more than one of the plurality of output buffers, and controlling a plurality of output buffers including the output buffer. These control signals are generated by the control circuit to control a plurality of output buffers. The correspondence between the control circuit and the plurality of output buffers may be one-to-one or one-to-many. As shown in FIG. 2A, a control circuit 300 is coupled to an output buffer 260. In general, one control circuit 300 can be coupled to one or more output buffers 260. Further, the integrated circuit may include a plurality of control circuits, and each control circuit is coupled to one or more output buffers. The number of one control circuit coupled to the output buffer can be different from the number of other control circuits coupled to the output buffer.

The preferred embodiments and examples of the present invention are disclosed in detail above, but it should be understood that the above examples are merely exemplary and are not intended to limit the scope of the patent. For those skilled in the art, the related art can be modified and combined easily according to the scope of the following patent application.

120, 220, 412‧‧‧P type MOS semi-transistor (PMOS)

140, 240, 414, 416‧‧‧N type MOS semi-transistor (NMOS)

160, 260‧‧‧ output buffer

180, 280, 418, 328‧ ‧ capacitors

200‧‧‧ integrated circuit

300, 800‧‧‧ control circuit

310‧‧‧delay analog circuit

320, 880‧‧‧ delay line

322, 324, 326‧‧‧ reduce the circuit

330, 890‧‧ ‧ Logic

400‧‧‧reference delay circuit

410‧‧‧First delay subcircuit

450‧‧‧ signal

460‧‧‧second delay subcircuit

462, 468‧‧‧ delay elements

610, 620‧‧‧ delay buffer circuit

615, 625‧‧‧ storage circuits

650‧‧‧Decoder

810, 820, 830, 840‧‧‧ delay buffer circuit

815, 825, 835, 845‧‧‧ storage circuits

850‧‧‧Decoder

910‧‧‧Left-to-right offset register

921, 922, 923, 924‧‧‧ tristate buffers

960, 961, 962, 963, 964‧‧‧ output drivers

1020‧‧‧ memory array

1040‧‧‧Line mat

1080‧‧‧Output and write terminal

Figure 1A shows a design example of a conventional output buffer. .

Figure 1B shows a waveform diagram associated with the output buffer of Figure 1A.

Figure 2A shows a block diagram of a sample integrated circuit. This example integrated circuit includes an output buffer with self-correcting output drive capability.

Figure 2B shows an output buffer that includes a plurality of parallel output drivers.

Figure 2C shows a waveform diagram associated with the output buffer in Figure 2A.

Fig. 3 is a block diagram showing a control circuit used in the integrated circuit in Fig. 2A.

Fig. 4 is a block diagram of the reference delay circuit in Fig. 3.

Figures 5A-5C include a set of illustrations depicting how the reference delay circuit in Figure 4 compensates for timing variations due to varying process boundary, voltage, temperature (PVT) conditions.

Fig. 6 is a more detailed circuit diagram of the control circuit in Fig. 3.

Figure 7 is an example truth table associated with the control circuit of Figure 6.

Figure 8 shows an alternative control circuit.

Figure 9 shows an example circuit diagram of the drive capability adjustment of a control output buffer.

Figure 10 shows a wafer arrangement diagram of the integrated circuit of this example.

Figures 11 through 13 show example waveform diagrams associated with controlling an output buffer method.

300‧‧‧Control circuit

310‧‧‧delay analog circuit

320‧‧‧delay line

330‧‧‧Logic

400‧‧‧reference delay circuit

Claims (20)

An integrated circuit comprising: an output buffer having a signal input, a signal output, and a set of control inputs, the output buffer having an output buffer delay and adjusting the drive in response to a control signal applied to the set of control inputs And a control circuit coupled to the set of control inputs of the output buffer, the control circuit generating the control signals using the first and second timing signals, and including a reference delay circuit, the reference delay circuit generating a reference delay The first timing signal, and a delay analog circuit, the delay analog circuit generates the second timing signal with a delay analog, the delay simulation being related to the output buffer delay. The integrated circuit of claim 1, wherein: the reference delay circuit is responsive to a reference signal to generate the first timing signal having a reference delay, and wherein the reference delay circuit substantially corresponds to a process boundary, a voltage, At least one of temperature (PVT) conditions is insensitive; the delay analog circuit is responsive to its input of the reference signal to produce the second timing signal having a delayed analog at its output, and wherein the analog delay is based on the process boundary, At least one of the voltage, temperature (PVT) conditions corresponds to a change in the output buffer delay. The integrated circuit of claim 1, wherein the control signal has a first value if the first timing signal is generated between a first delay threshold and a second delay threshold relative to the second timing signal In the first time interval, if the first timing signal occurs with respect to the second timing signal, the control signal has a second value earlier than the first delay threshold, if the first timing signal is relative to the The second timing signal occurs later than the second delay threshold and the control signal has a third value. The integrated circuit of claim 3, wherein the control circuit comprises: a delay line having an input coupled to the delay analog circuit, and having a first connector corresponding to the first delay threshold and a second The connector is coupled to the second delay threshold; and the logic is coupled to the first connector and the second connector of the delay line and coupled to the reference delay circuit, the logic generating the control signal. The integrated circuit of claim 4, wherein the logic comprises: a first storage circuit having a clock input terminal electrically coupled to the reference delay circuit to receive the first timing signal, a data input terminal Electrically coupled to the first terminal of the delay line and having an output terminal; a second storage circuit having a clock input terminal electrically coupled to the reference delay circuit to receive the first timing signal, The data input terminal is electrically coupled to the second terminal of the delay line and has an output terminal; and a decoder is coupled to the output of the first storage circuit and the second storage circuit to generate the control signal. The integrated circuit of claim 1, wherein the control circuit indicates a time when the first timing signal occurs in the time interval of the plurality of time intervals relative to the second timing signal, and the logic sounds The control signal should be generated for the indicated time interval. The integrated circuit of claim 6, wherein the control circuit comprises: a delay line having an input coupled to the delay analog circuit, and having a plurality of joints corresponding to the plurality of time intervals; and a logical AND The plurality of connectors of the delay line are coupled and associated with the reference The late circuit is coupled and the logic generates the control signal. The integrated circuit of claim 1, wherein the output buffer comprises a plurality of parallel output drivers, and the output driver selected by the control signal is enabled and disabled to adjust the driving capability of the output buffer. The integrated circuit of claim 1, comprising a write terminal configured to connect the circuit to the integrated circuit, and wherein the output of the output buffer and the write terminal connection. The integrated circuit of claim 1, comprising a plurality of output buffers including an output buffer responsive to the control signal for adjusting its driving capability, wherein the control signal is applied to the plurality of output buffers More than one of the set of control inputs on the output buffer. A method of controlling an output buffer, wherein the output buffer has an output buffer delay, comprising: generating a first timing signal, the first timing signal having a reference delay; generating a second timing signal, the second The timing signal has a delay analog associated with the output buffer delay; and the drive capability of the output buffer is adjusted in response to the first timing signal and the second timing signal. The method of claim 11, comprising: responsive to a reference signal using a reference delay circuit to generate the first timing signal, and wherein the reference delay circuit is substantially compliant with process boundary, voltage, temperature (PVT) conditions At least one is insensitive; and responding to the reference signal using a delay analog circuit to generate the second timing a signal, and wherein the analog delay corresponds to a change in the output buffer delay based on at least one of the process boundary, voltage, temperature (PVT) conditions. The method of claim 11, further comprising: generating a control signal in response to the first timing signal and the second timing signal, and using the control signal to adjust a driving capability of the output buffer, wherein the controlling The signal has a first value, if the first timing signal is generated in a first time interval between a first delay threshold and a second delay threshold with respect to the second timing signal; a second value, If the first timing signal occurs earlier than the first delay threshold with respect to the second timing signal; a third value, if the first timing signal occurs later than the second timing signal The second delay is critical. The method of claim 13, further comprising: using a delay line coupled to one of the first timing signal and the second timing signal, the delay line having a first connector and the first A delay critical correspondence and a second joint correspond to the second delay threshold, and the first joint and the second joint using the delay line generate the control signal. The method of claim 14, further comprising: using the first timing signal to provide a clock to a first storage circuit, the first storage circuit having a data input terminal to receive the first connector of the delay line Using the second timing signal to provide a clock to a second storage circuit, the second storage circuit having a data input terminal to receive the delay line a second connector; and generating the control signal using the output of the first storage circuit and the second storage circuit. The method of claim 11, further comprising: determining a time period of the first timing signal relative to the second timing signal in a time interval of the plurality of time intervals, and responding to the indicated time interval The control signal is generated. The method of claim 16, further comprising: coupling a delay line to one of the first timing signal and the second timing signal; and generating the control signal using the plurality of connectors of the delay line. The method of claim 11, wherein the output buffer comprises a plurality of parallel output drivers, and the output driver selected by the control signal enabling and disabling is used to adjust the driving capability of the output buffer. The method of claim 11, wherein the output buffer is in an integrated circuit, the integrated circuit including a write terminal configured to connect the circuit to the integrated circuit, and provide the output This output of the buffer is to the write terminal. The method of claim 13, comprising controlling a plurality of output buffers including the output buffer, and using the control signal to adjust a drive capability of the output buffers of more than one of the plurality of output buffers.