TWI772240B - Mixed-voltage output buffer - Google Patents

Abstract

A mixed-voltage output buffer includes a VDDIO voltage detector, a voltage-level converter, a non-overlap circuit, a process detector, an output stage, a voltage slew rate feedback circuit, and a digital logic circuit. The voltage slew rate feedback circuit detects the voltage slew rate of an output voltage of the output stage and controls the compensation control signal output by the digital logic circuit so that the voltage slew rate of the output voltage of the output stage can meet the requirements.

Description

Multiple Voltage Output Buffers

The present invention relates to an output buffer, particularly to a multiple voltage output buffer.

The output buffer is used to transmit signals between two circuits with different voltage levels, so that the internal circuit of the input buffer may receive voltages of different voltage levels. pressure. In addition, the relevant parameters of the signal output by the output buffer under different specifications are specified. For example, DDR4, the mainstream specification of memory, has restrictions on the slew rate and duty cycle of the output signal. Therefore, in order to make the output buffer suitable for DDR4 Specifications, the voltage slew rate, duty cycle and related circuits for system voltage control must be set in the circuit.

The main purpose of the present invention is to provide a multiple voltage output buffer that can meet the DDR4 specification.

A multiple voltage output buffer of the present invention includes an external voltage detector, a voltage level converter, a non-overlapping circuit, a process drift detector, an output stage, and a voltage slew rate feedback circuit and a digital logic circuit, the external voltage detector receives a power supply voltage and an external voltage, the external voltage detector is used to detect the voltage level of the power supply voltage and the external voltage and output a detection voltage, the voltage level The quasi converter is electrically connected to the external voltage detector, the voltage level converter receives the detection voltage and a data signal, and the voltage level converter converts the voltage level of the data signal to a high level according to the detection voltage high-level data signal and a low-level data signal, the non-overlapping circuit is electrically connected to the voltage level converter to receive the high-level data signal and the low-level data signal, the non-overlapping circuit is used for the high-level data signal and the low-level data signal The low-level data signal is converted into a non-overlapping first non-overlapping signal and a second non-overlapping signal, the process drift detector receives a clock signal and a plurality of reference signals, and the process drift detector is based on The clock signal and the reference signals output a P-type process detection signal and an N-type process detection signal, the output stage is electrically connected to the external voltage detector to receive the detection voltage, and the output stage outputs an output voltage, the voltage slew rate feedback circuit is electrically connected to the output stage to receive the output voltage, the voltage slew rate feedback circuit receives a first slew rate reference voltage and a second slew rate reference voltage, the voltage The slew rate feedback circuit judges the slew rate of the output voltage according to the first slew rate reference voltage and the second slew rate reference voltage and outputs a slew rate control signal, the digital logic circuit is electrically connected to the non-overlapping circuit, the Process drift detector, the voltage slew rate feedback circuit and the output stage, the digital logic circuit receives the first non-overlapping signal, the second non-overlapping signal, the P-type process detection signal, the N-type For the process detection signal and the slew rate control signal, the digital logic circuit outputs a plurality of compensation control signals to the output stage to control the voltage slew rate of the output voltage.

The present invention uses the voltage slew rate feedback circuit to detect the voltage slew rate of the output voltage, so as to know whether the voltage slew rate of the output voltage meets the requirements and output the slew rate control signal to the digital logic circuit, The compensation control signal output by the digital logic circuit is adjusted so that the voltage slew rate of the output voltage output by the output stage can meet the requirements.

Please refer to FIG. 1 , which is a circuit diagram of a multiple voltage output buffer 100 according to an embodiment of the present invention. The multiple voltage output buffer 100 includes an external voltage detector 110 , a voltage level converter 120 , a Non-overlapping circuit 130 , a duty cycle corrector 140 , a process drift detector 150 , an output stage 160 , a voltage slew rate feedback circuit 170 , a digital logic circuit 180 and a floating N-well 190 .

Please refer to FIG. 1, the external voltage detector 110 receives a power supply voltage VDD and an external voltage VDDIO, the external voltage detector 110 is used for detecting the voltage levels of the power supply voltage VDD and the external voltage VDDIO and outputs a Detection voltage V _D . Please refer to FIG. 2 , which is a circuit diagram of the external voltage detector 110 of this embodiment. The external voltage detector 110 has a first P-type switching transistor M _P21 and a second P-type switching transistor M _P24 , a load group 111 and a transistor pair 112 . The first P-type switching transistor _MP21 receives the power supply voltage VDD and the external voltage VDDIO, and the first P-type switching transistor _MP21 outputs a control voltage _Vctr , and the second P-type switching transistor _MP24 is electrically The first P-type switching transistor _{MP21 is electrically connected, and the second P-type switching transistor MP24 receives} the power supply voltage VDD and the control voltage _Vctr . The load group 111 is electrically connected to the first P-type switching transistor _MP21 to receive the control voltage V _ctr , and the load group 111 has two P-type transistors M _P22 , M _P23 and three N-type transistors M _N21 , _MN22 , _MN23 , and the load group 111 outputs the detection voltage V _D . The transistor pair 112 has a first N-type transistor _MN24 and a second N-type transistor _MN25 , the first N-type transistor _MN24 and the second N-type transistor _MN25 are electrically connected to the load The group 111 and the second P-type switching transistor M _P24 .

Please refer to FIG. 2 again, when the potential of the external voltage VDDIO is 1.5 times the potential of the power supply voltage VDD, the first P-type switching transistor MP21 is turned on, and the second P-type switching transistor _MP24 is _turned off , the voltage of the load group 111 rises, so that the second N-type transistor M _N25 of the transistor pair 112 is turned on, and the potential of the node V2 drops to a low potential, so that the first N-type transistor M of the transistor pair 112 is turned on. _N24 is turned off, at this time, through the voltage division of the load group 111, the potential of the control voltage V _ctr output by the first P-type switching transistor _MP21 is the same as the potential of the power supply voltage VDD, and the voltage output by the load group 111 The potential of the detection voltage V _D is 0.5 times the potential of the power supply voltage VDD.

On the contrary, when the potential of the external voltage VDDIO is the same as the potential of the power supply voltage VDD, the first P-type switching transistor _{MP21 is turned off, the second P-type switching transistor MP24 is} turned on, and the potential of the node V2 is increased , the first N-type transistor _MN24 of the transistor pair 112 is turned on, the potential of the node V1 drops to a low potential, and the second N-type transistor _MN25 of the transistor pair 112 is turned off. At this time, the load group 111 is grounded via the first N-type transistor _MN24 , so that the control voltage V _ctr and the detection voltage V _D are both low potentials.

Please refer to FIG. 1, the voltage level converter 120 is electrically connected to the external voltage detector 110, the voltage level converter 120 receives the detection voltage V _D , the control voltage V _ctr and a data signal Data, The voltage level converter 120 converts the voltage level of the data signal into a high-level data signal DP1 and a low-level data signal DN1 according to the detection voltage V _D and the control voltage V _ctr . In this embodiment, when the potential of the external voltage VDDIO is the potential of the power supply voltage VDD, the voltage level converter 120 converts the low level and the high level of the data signal Data into the high level data signal DP1 and the high level data signal DP1 and the The potentials of the low-level data signal DN1 are both 0 and the power supply voltage VDD. When the potential of the external voltage VDDIO is 1.5 times the potential of the power supply voltage VDD, the voltage level converter 120 converts the low potential and the high potential of the data signal Data into the potentials of the high level data signal DP1 which are respectively the For the power voltage VDD and the external voltage VDDIO, the voltage level converter 120 converts the low level and the high level of the data signal Data into the low level data signal DN1. The levels are 0 and the power supply voltage VDD, respectively.

In this embodiment, in order to prevent the transistors of the output stage 160 from being short-circuited and overvoltage during the transition state, the switching time of the two control signals is staggered by the non-overlapping circuit 130. In this embodiment, the non-overlapping circuit 130 The circuit 130 is electrically connected to the voltage level converter 120 to receive the high level data signal DP1 and the low level data signal DN1, and the non-overlapping circuit 130 is used for converting the high level data signal DP1 and the low level data signal DN1 are a non-overlapping first non-overlapping signal DP2 and a second non-overlapping signal DN2. Wherein, since the voltage levels of the high-level data signal DP1 and the low-level data signal DN1 may be different, the non-overlapping circuit 130 has a high-level non-overlapping circuit 131 and a low-level non-overlapping circuit 132 to The high-level data signal DP1 and the low-level data signal DN1 are processed respectively.

Please refer to FIG. 1, the duty cycle corrector 140 is electrically connected to the non-overlapping circuit 130 to receive the first non-overlapping signal DP2 and the second non-overlapping signal DN2, and the duty cycle corrector 140 is used for correcting the The duty cycle of the first non-overlapping signal DP2 and the second non-overlapping signal DN2. Since the voltage levels of the first non-overlapping signal DP2 and the second non-overlapping signal DN2 may be different, in this embodiment, the duty cycle corrector 140 has a high-level duty cycle correction circuit 141 and A low-level duty cycle correction circuit 142, the high-level duty cycle correction circuit 141 is electrically connected to the high-level non-overlapping circuit 131 to receive the first non-overlapping signal DP2, and the high-level duty cycle correction circuit 141 is used for correction The duty cycle of the first non-overlapping signal DP2 outputs a first duty cycle calibration signal DP3. The low-level duty cycle calibration circuit 142 is electrically connected to the low-level non-overlapping circuit 132 to receive the second non-overlapping signal. DN2, the low-level duty period correction circuit 142 is used for correcting the duty period of the second non-overlapping signal DN2 to output a second duty period correction signal DN3.

Please refer to FIG. 3 , which is a circuit diagram of the high-level duty cycle correction circuit 141 of this embodiment. The high-level duty cycle correction circuit 141 has a first inverter 141 a , a first charging capacitor 141 b , a second inverter The inverter 141c, a third inverter 141d, a voltage divider circuit 141e, a second charging capacitor 141f and a current mirror circuit 141g. In this embodiment, the first inverter 141a has a P-type transistor _MP61 and an N-type transistor _MN61 , and the gates of the P-type transistor _MP61 and the N-type transistor _MN61 receive the the first non-overlapping signal DP2. The first charging capacitor 141b and the second inverter 141c are electrically connected to the first inverter 141a, and the second inverter 141c outputs the first duty cycle correction signal DP3 to the digital logic circuit 180. In this embodiment, the first charging capacitor 141b is electrically connected to the drains of the P-type transistor _MP61 and the N-type transistor _MN61 , and the second inverter 141c has a P-type transistor _MP62 and a N-type transistor M _N62 , the P-type transistor M _P62 and the gate of the N-type transistor M _N62 are electrically connected to the drain of the P-type transistor M _P61 and the N-type transistor M _N61 , the P-type transistor M P62 The source of the transistor M _P62 receives the external voltage VDDIO, the source of the N-type transistor M _N62 is connected to a low potential terminal, and the drains of the P-type transistor M _P62 and the N-type transistor M _N62 output The first duty cycle correction signal DP3. In this embodiment, the low potential terminal is the detection voltage V _D .

The third inverter 141d has a P-type transistor M _P63 and an N-type transistor M _N63 , and the gates of the P-type transistor M _P63 and the N-type transistor M _N63 receive the first non-overlapping signal DP2, the source of the P-type transistor M _P63 receives the external voltage VDDIO, and the source of the N-type transistor M _N63 is connected to the low potential terminal. The voltage dividing circuit 141e is electrically connected to the third inverter 141d, and the voltage dividing circuit 141e has a P-type transistor _MP64 , a _first voltage dividing resistor R1 and a _second voltage dividing resistor R2, The gate of the P-type transistor M _P64 is electrically connected to the drains of the P-type transistor M _P63 and the N-type transistor M _N63 , and both ends of the first voltage dividing resistor R ₁ respectively receive the external voltage VDDIO and The source of the P-type transistor M _P64 is electrically connected, and both ends of the second voltage dividing resistor R ₂ are electrically connected to the drain of the P-type transistor M _P64 and the low-potential terminal, respectively. The second charging capacitor 141f is electrically connected to the _second voltage dividing resistor R2 of the voltage dividing circuit 141e and the drain of the P-type transistor _MP64 .

The current mirror circuit 141g is electrically connected to the second charging capacitor 141f and the first inverter 141a. The current mirror circuit 141g is controlled by a charging voltage V12 of the second charging capacitor 141f to change its effect on the first charging capacitor A charge and discharge current size of 141b. In this embodiment, the current mirror circuit 141g has a fourth inverter 141h, a first current mirror switch _MP67 , a first current mirror reference transistor _MP66 , and a first current mirror radio transistor _MP68 , a second current mirror switch _MN66 , a second current mirror reference transistor _MN65 and a second current mirror radio transistor _MN67 . The fourth inverter 141h is electrically connected to the second charging capacitor 141f to receive the charging voltage V12. In this embodiment, the fourth inverter _141h has a P-type transistor MP65 and an N-type transistor M _N64 , the gates of the P-type transistor M _P65 and the N-type transistor M _N64 are electrically connected to the second charging capacitor 141f , and the gate of the first current mirror switch M _P67 is electrically connected to the second charging capacitor 141f, the source of the first current mirror switch _MP67 is electrically connected to the _{drains of the P-type transistor MP65 and the N-type transistor MN64, and the drain of the first current mirror switch MP67 is connected} to the low potential terminal, and the first current mirror switch _MP67 is controlled to be turned on or off by the charging voltage V12 of the second charging capacitor 141f. The gate and drain of the first current mirror reference transistor _MP66 are electrically connected to the source of the P-type transistor _MP65 , and the source of the first current mirror reference transistor _MP66 receives the external voltage VDDIO. The gate of the first current mirror-radio transistor _MP68 is electrically connected to the gate and drain of the first current-mirror reference transistor _MP66 , and the source of the first current-mirror-radio transistor _MP68 receives the external voltage VDDIO, the drain of the first current mirror-radio transistor M _P68 is electrically connected to the source of the P-type transistor M _P61 . The gate of the second current mirror switch _MN66 is electrically connected to the second charging capacitor 141f, and the source of the second current mirror switch _MN66 is electrically connected to the P-type transistor M _P65 and the N-type transistor M _N64 The drain of the second current mirror switch _MP66 receives the external voltage VDDIO, and the second current mirror switch _MP66 is controlled to be turned on or off by the charging voltage V12 of the second charging capacitor 141f. The gate and drain of the second current mirror reference transistor _MN65 are electrically connected to the source of the N-type transistor _MP65 , and the source of the second current mirror reference transistor _MN65 is connected to the low potential terminal. The gate of the second current mirror radio transistor _MN67 is electrically connected to the gate and drain of the second current mirror reference transistor _MN65 , and the source of the second current mirror radio transistor _MN67 is connected to the low potential At the terminal, the drain of the second current mirror-mirror transistor _MN67 is electrically connected to the source of the N-type transistor _MN61 .

The circuit operation of the high-level duty cycle correction circuit 141 for correcting the first non-overlapping signal DP2 is as follows: the first inverter 141a and the third inverter 141d of the high-level duty cycle correction circuit 141 receive the first The non-overlapping signal DP2, wherein when the first non-overlapping signal DP2 is at a high level, the N-type transistor _MN63 is turned on, so that the P-type transistor M _P64 is connected to the low-level terminal to be turned on, and the external voltage VDDIO passes through The _first voltage dividing resistor R1 and the P-type transistor M _P64 charge the second charging capacitor 141f. When the duty cycle of the first non-overlapping signal DP2 is small, the charging voltage V12 of the second charging capacitor 141f is small because the charging time is short. At this time, the P-type transistors M _P65 and M _P67 And M _P66 is turned on for a long time, a first current mirror current flows from the external voltage VDDIO to the low voltage terminal through the P-type transistors M _P66 , M _P65 and M _P67 , and the first current mirror current is mirrored to The first current mirror mirror radio transistor M _P68 is transmitted to the first charging capacitor 141b through the P-type transistor M _P61 for charging to generate a charging voltage V11 , so that the charging voltage V11 is increased by a faster charging speed. Faster, the first duty cycle correction signal DP3 output by the second inverter 141c can have a larger duty cycle. Conversely, when the duty cycle of the first non-overlapping signal DP2 is larger, the charging voltage V12 of the second charging capacitor 141f is larger due to the longer charging time. At this time, the N-type transistors _MN64 , _MN66 and _MN65 are turned on for a long time, a second current mirror current flows from the external voltage VDDIO to the low voltage terminal through the P-type transistors _MN66 , _MN64 and _MN65 , and the second current mirror current flows through the P-type transistors MN66, MN64 and MN65 The current mirror radiates to the second current mirror radio transistor _MN67 and forms the discharge path of the first charging capacitor 141b together with the N-type transistor _MN61 so that the charging voltage V11 decreases. When the charging voltage V11 drops faster due to the faster discharging speed, the first duty period correction signal DP3 output by the second inverter 141c can have a smaller duty period.

Please refer to FIG. 1 , the difference between the low-level duty cycle correction circuit 142 and the high-level duty cycle correction circuit 141 is only that the high level received by the low-level duty cycle correction circuit 142 is the power supply voltage VDD and the received low level If it is 0, the other circuits and actions are the same, so they are not repeated here.

Please refer to FIG. 1, the process drift detector 150 receives a clock signal Clk and a plurality of reference signals V _ref1-4 , and the process drift detector 150 receives the clock signal Clk and the reference signals V _ref1-4 according to the process drift detector 150 _4. Output a P-type process detection signal P _code [2:1] and an N-type process detection signal N _code [2:1]. Please refer to FIGS. 4 and 5. In this embodiment, the process drift detector 150 has a P-type transistor process drift detection circuit 151 and an N-type transistor process drift detection circuit 152, which are used to detect the circuit drift respectively. Process drift of P-type transistors and N-type transistors is detected.

Please refer to FIG. 4, the P-type transistor process drift detection circuit 151 has a PMOS inverter 151a, a charging capacitor 151b, a first comparator 151c, a first register 151d, and a second comparator 151e and a second register 151f. The PMOS inverter 151a has a P-type transistor M _P41 and an N-type transistor M _N41 . The gates of the P-type transistor M _P41 and the N-type transistor M _N41 receive the clock signal Clk, and the P The source of the P-type transistor M _P41 receives the power supply voltage VDD, the drain of the P-type transistor M _P41 is electrically connected to the drain of the N-type transistor _MN41 , and the source of the N-type transistor _MN41 is grounded. One end of the charging capacitor 151b is electrically connected to the _{drains of the P-type transistor MP41 and the N-type transistor MN41 ,} the other end of the charging capacitor 151b is grounded, and the charging capacitor 151b generates a charging voltage V _C1 , the The first comparator 151c is electrically connected to the charging capacitor 151b to receive the charging voltage V _C1 and the first reference signal V _ref1 , and a first comparison signal output by the first comparator 151c is transmitted to the charging voltage V ref1 through an inverter The first register 151d, the first register 151d outputs a first bit P _code [1] of the P-type process detection signal P _code [2:1], the second comparator 151e is electrically connected The charging capacitor 151b receives the charging voltage and the second reference signal V _ref2 , and a second comparison signal output by the second comparator 151e is transmitted to the second register 151f through an inverter. The register 151f outputs a second bit P _code [2] of the P-type process detection signal P _code [2:1].

Please refer to FIG. 5, the N-type transistor process drift detection circuit 152 has an NMOS inverter 152a, a charging capacitor 152b, a first comparator 152c, a first register 152d, and a second comparator 152e and a second register 152f. The NMOS inverter 152a has an inversion unit Inv and two N-type transistors _{MN51 and 52.} The gate of the N-type transistor _MN51 receives the inverted clock signal Clk through the inversion unit Inv, The gate of the N-type transistor _MN52 receives the clock signal Clk, the drain of the N-type transistor _MN51 receives the power supply voltage VDD, and the source of the N-type transistor M _P51 is electrically connected to the N-type transistor The drain of the crystal _MN52 , and the source of the N-type transistor _MN52 is grounded. The charging capacitor 152b is electrically connected to the source of the N-type transistor _{MN51 and the drain of the N-type transistor MN52 ,} and the charging capacitor 152b generates a charging voltage V _C2 , and the first comparator 152c is electrically connected The charging capacitor 152b receives the charging voltage V _C2 and the third reference signal V _ref3 , and a first comparison signal output by the first comparator 152c is transmitted to the first register 152d through an inverter. The first register 152d outputs a first bit _Ncode [1] of the N-type process detection signal _Ncode [2:1], and the second comparator 152e is electrically connected to the charging capacitor 152b to receive the charging The voltage V _C2 and a fourth process drift reference voltage V _ref4 , and a second comparison signal output by the second comparator 152e is transmitted to the second register 152f through an inverter, and the second register 152f A second bit N _code [2] of the N-type process detection signal N _code [2:1] is output.

The process drift detector 150 triggers the P-type transistor M _P41 of the P-type transistor process drift detection circuit 151 and the N-type transistor process drift detection circuit 152 respectively by the negative edge of the clock signal Clk and the N-type transistor _MN51 to charge the charging capacitors 151 and 152 to increase the charging voltages V _C1 and V _C2 . When the process is located in a fast corner, the P-type transistor M _P41 and the N-type transistor M _N51 charge the charging capacitors 151 and 152 faster, on the contrary, when the process is located in a fast corner, the P The charging speed of the charging capacitors 151 and 152 is relatively slow by the N-type transistor M _P41 and the N-type transistor M _N51 . Therefore, after the comparison between the two comparators and the reference signals V _ref1-4 , the The process corners of the PMOS transistor and the NMOS transistor in the circuit are known from the 4 bits of the P-type process detection signal P _code [2:1] and the N-type process detection signal N _code [2:1] .

Please refer to FIG. 1 , the digital logic circuit 180 is electrically connected to the duty cycle corrector 140 , the process drift detector 150 and the voltage slew rate feedback circuit 170 to receive the first output from the duty cycle corrector 140 A duty cycle calibration signal DP3 and the second duty cycle calibration signal DN3, the P-type process detection signal P _code [2:1] and the N-type process detection signal N _code [ output by the process drift detector 150 2:1] and the voltage slew rate feedback circuit 170 outputs a first slew rate control signal Ctr1 and a second slew rate control signal Ctr2, and the digital logic circuit 180 outputs a plurality of compensation control signals by these signals Vgp[5:1], Vgn[5:1] to the output stage 160 to control the voltage slew rate of an output voltage V _PAD of the output stage 160 due to the digital logic circuit 180 to the output stage 160 The control of the compensation transistor is not a limitation of this case, so it is not described in detail in this case. In this embodiment, the compensation control signals Vgp[5:1] and Vgn[5:1] are respectively transmitted to the output stage 160 through the two gate driving circuits 181 and 182 .

In another embodiment, if the system specification used does not specify the size of the duty cycle of the signal, the duty cycle corrector 140 does not need to be set, and the digital logic circuit 180 directly receives the first signal from the non-overlapping circuit 130 The non-overlapping signal DP2 and the second non-overlapping signal DN2.

Please refer to FIG. 1, the output stage 160 is electrically connected to the external voltage detector 110 and the two gate driving circuits 181, 182 to receive the detection voltage V _D and the compensation control signals Vgp[5: 1], Vgn[5:1], and the output stage 160 outputs the output voltage V _PAD . In this embodiment, the output stage 160 has a P-type output transistor M _P11 , a plurality of P-type compensation transistors M _P12-16 , an N-type output transistor MN11 and a plurality of _N -type compensation transistors M _{N12 -16} . The gate of the P-type output transistor M _P11 is electrically connected to the external voltage detector 110 to receive the detection voltage V _D , and the drain of the P-type output transistor M _P11 is electrically connected to the N-type output transistor The drain of M _N11 , the source of the P-type output transistor M _P11 is electrically connected to the drains of the P-type compensation transistors M _P12-16 , and the sources of the P-type compensation transistors M _P12-16 receive For the external voltage VDDIO, the gates of the P-type compensation transistors M _P12-16 receive the compensation control signals Vgp[5:1] from the gate driving circuit 181 . The gate of the N-type output transistor MN11 receives the power supply voltage VDD, the source of the N-type output transistor _MN11 is electrically connected to the _{drains of the N-type compensation transistors MN12-16 ,} and the N-type The sources of the compensation transistors _MN12-16 are grounded, and the gates of the N-type compensation transistors _MN12-16 receive the compensation control signals Vgn[5:1] from the gate driving circuit 182, and the P-type output The transistor M _P11 and the drain of the N-type output transistor M _N11 output the output voltage _VPAD . The turn-on numbers of the P-type compensation transistors M _P12-16 and the N-type compensation transistors _MN12-16 are used to increase the magnitude of the output current to adjust the voltage slew rate of the output voltage _VPAD .

Please refer to Figures 1 and 6, since the potential of the external voltage VDDIO may be 1 times the power supply voltage VDD or 1.5 times the power supply voltage VDD, the P-type output transistor M _P11 will be caused by the parasitic diode of P+/N Well The body is turned on and exceeds the maximum threshold voltage, resulting in the generation of a leakage current path. Therefore, preferably, the base of the P-type output transistor M _P11 is electrically connected to the floating N-type well 190, and the floating N-type well 190 receives the The power supply voltage VDD and the output voltage V _PAD , and the floating N-type well 190 outputs a base voltage V _NW to the base of the P-type output transistor _MP11 . Please refer to FIG. 5 , the floating N-type well 190 has a first P-type transistor M _P31 , a second P-type transistor M _P32 and an M-type transistor M _N31 , the first P-type transistor M _P31 The source of the first P-type transistor MP32 and the gate of the second P-type transistor MP32 receive the output voltage V _PAD , the gate of the first P-type transistor _MP31 and the source of the second P-type transistor _MP32 receive the output voltage _VPAD The power supply voltage VDD, the gate and drain of the N-type transistor _MN31 receive the output voltage V _PAD , the drain of the first P-type transistor M _P31 , the drain of the second P-type transistor M _P32 and The N-type transistor _MN31 outputs the base voltage V _NW . Wherein, when the output voltage V _PAD is the potential of the power supply voltage VDD, the first P-type transistor M _P31 and the second P-type transistor M _P32 are turned off, and the N-type transistor M _N31 is turned on. At this time, The potential of the base voltage V _NW is VDD-V _th , and the leakage current path of the P-type output transistor _MP11 is closed. When the output voltage V _PAD is 1.5 times the potential of the power supply voltage VDD, the first P-type transistor M _P31 is turned on, and the base voltage V _NW has a potential of 1.5 times VDD, and the P-type output transistor The parasitic diode of M _P11 is turned off, which can also close the leakage current path of the P-type output transistor M _P11 to reduce power consumption.

Please refer to FIG. 1 , since the compensation of the voltage slew rate of the output voltage V _PAD by the output stage 160 may be too much or too little, which may not meet the requirements, therefore, in this embodiment, the voltage slew rate feedback circuit 170 is used to detect the output The voltage slew rate of the voltage V _PAD is fed back to the slew rate control signals Ctr1 and Ctr2 to the digital logic circuit 180 to adjust the output compensation control signal. The voltage slew rate feedback circuit 170 is electrically connected to the output stage 160 to receive the output voltage _VPAD , and the voltage slew rate feedback circuit 170 receives a first slew rate reference voltage SR _r1 and a second slew rate reference voltage SR _r2 , the voltage slew rate feedback circuit 170 determines the slew rate of the output voltage according to the first slew rate reference voltage SR _r1 and the second slew rate reference voltage SR _r2 and outputs the slew rate control signals Ctr1 and Ctr2 .

Referring to FIGS. 1 and 7, in this embodiment, the voltage slew rate feedback circuit 170 has a first comparator 171, a second comparator 172, an XOR gate 173, a first delay unit 174, a The second delay unit 175 , a third delay unit 176 and a logic gate circuit 177 . The first comparator 171 electrically connects the output stage 160, the first comparator 171 receives the output voltage V _PAD and the first slew rate reference voltage SR _r1 , and the first comparator 171 outputs a first comparison signal Cmp1 , the second comparator 172 electrically connects the output stage 160 , the second comparator 172 receives the output voltage V _PAD and the second slew rate reference voltage SR _r2 , and the second comparator 172 outputs a second comparison signal Cmp2. The XOR gate 173 is electrically connected to the first comparator 171 and the second comparator 172 to receive the first comparison signal Cmp1 and the second comparison signal Cmp2, and the XOR gate 173 outputs an XOR signal Dxor.

Please refer to FIG. 8, which is a timing diagram of the circuit operation of the voltage slew rate feedback circuit 170. In this embodiment, the potential of the first slew rate reference voltage SR _r1 is 0.8 times the external voltage VDDIO, the The potential of the second slew rate reference voltage SR _r2 is 0.2 times the external voltage VDDIO. The output voltage _VPAD is compared with 0.8VDDIO and 0.2VDDIO through the first comparator 171 and the second comparator 172 respectively, and then outputs the first comparison signal Cmp1 and the second comparison signal Cmp2 to the XOR gate 173, the XOR The gate 173 outputs the XOR signal Dxor according to the first comparison signal Cmp1 and the second comparison signal Cmp2. It can be seen from Figure 8 that when the voltage slew rate of the output voltage V _PAD is higher, that is, when the rising and falling edges are steeper, the two pulse widths of the XOR signal Dxor will be narrower, and the output voltage V The lower the voltage slew rate of the _PAD , that is, the smoother the rising and falling edges of the PAD, the wider the two pulse widths of the XOR signal Dxor, thereby measuring the voltage slew rate of the output voltage V _PAD .

Next, please refer to FIG. 7, the first delay unit 174 receives the first duty cycle correction signal DP3 and outputs a first delay signal Ddy1, and the second delay unit 175 receives the first duty cycle correction signal DP3 and outputs a For the second delay signal Ddy2, the third delay unit 175 receives the reversed first duty cycle correction signal DP3b and outputs a third delay signal Ddy3. The logic gate circuit 177 is electrically connected to the first delay unit 174 and the second delay unit 174. The delay unit 175 and the third delay unit 176 receive the first delay signal Ddy1, the second delay signal Ddy2 and the third delay signal Ddy3, and the logic gate circuit 177 outputs a first slew rate control signal Ctr1 and a The second slew rate control signal Ctr2 is sent to the digital logic circuit 180, wherein the respective delay amounts of the first delay unit 174, the second delay unit 175 and the third delay unit 176 are different.

In this embodiment, the logic gate circuit 177 has a first and gate 177a, a second and gate 177b, a third and gate 177c, a fourth and gate 177d, a first latch 177e and a first Two latches 177f, the first and gate 177a receive the XOR signal Dxor and the first delay signal Ddy1 and output a first logic signal DG1, the second and gate 177b receive the XOR signal Dxor and the second delay signal Ddy2 outputs a second logic signal DG2, the third gate 177c receives the first logic signal DG1 and the third delay signal Ddy3 and outputs a third logic signal DG3, and the fourth gate 177d receives the second logic The signal DG2 and the third delay signal Ddy3 output a fourth logic signal DG4, the first latch 177e receives the first duty cycle correction signal DP3 and the third logic signal DG3 and outputs the first slew rate control signal Ctr1, the second latch 177f receives the first duty cycle correction signal DP3 and the fourth logic signal DG3 and outputs the second slew rate control signal Ctr2.

Please refer to FIG. 9, which is a timing diagram showing that the voltage slew rate of the output voltage V _PAD meets the requirements, wherein the pulse width of the XOR signal Dxor is normal, so that the intersection of the XOR signal Dxor and the first delay signal Ddy1 obtains the The first logic signal DG1 has two pulses, but the second logic signal DG2 obtained by intersecting the second delay signal Ddy2 has only one pulse. Therefore, the third logic signal DG3 and the fourth logic signal DG4 obtained after the intersection of the first logic signal DG1 and the second logic signal DG2 and the third delay signal Ddy3 have 1 pulse and 0 pulses, respectively. And it means that the voltage slew rate of the output voltage _VPAD meets the requirements.

Please refer to FIG. 10, which is a timing diagram of the voltage slew rate of the output voltage V _PAD being too small, wherein the pulse width of the XOR signal Dxor is too wide, so that the XOR signal Dxor and the first delay signal Ddy1 are intersected to obtain the The first logic signal DG1 has two pulses, and the second logic signal DG2 obtained by intersecting the second delay signal Ddy2 also has two pulses. Therefore, the third logic signal DG3 and the fourth logic signal DG4 obtained after the intersection of the first logic signal DG1 and the second logic signal DG2 and the third delay signal Ddy3 have one pulse respectively, indicating that the The voltage slew rate of the output voltage _VPAD is too small.

Please refer to FIG. 11, which is a timing diagram of the voltage slew rate of the output voltage V _PAD being too large, wherein the pulse width of the XOR signal Dxor is too narrow, so that the XOR signal Dxor and the first delay signal Ddy1 and the second delay signal Ddy1 The intersection of the delayed signal Ddy2 can only get one pulse. Therefore, the third logic signal DG3 and the fourth logic signal DG4 obtained after the intersection of the first logic signal DG1 and the second logic signal DG2 and the third delay signal Ddy3 do not have a pulse, which indicates the output voltage The voltage slew rate of V _PAD is too large.

Please refer to FIG. 7, the third logic signal DG3 and the fourth logic signal DG4 are stored by the first latch 177e and the second latch 177f and output the first slew rate control signal Ctr1 and the first slew rate control signal Ctr1 The potential of the second slew rate control signal Ctr2 can be used by the digital logic circuit 180 to control the turn-on number of the compensation transistors of the output stage 160, so that the voltage slew rate of the output voltage _VPAD can meet the requirements.

In the present invention, the voltage slew rate of the output voltage is detected by the voltage slew rate feedback circuit, so as to know whether the voltage slew rate of the output voltage _VPAD meets the requirements and output the slew rate control signal to the digital logic The circuit is used to adjust the compensation control signal output by the digital logic circuit 180 so that the voltage slew rate of the output voltage _VPAD output by the output stage 160 can meet the requirements.

The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by anyone who is familiar with the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

100: Multiple voltage output buffers 110: External voltage detector M _P21 : First P-type switching transistor M _P24 : Second P-type switching transistor 111: Load group M _P22 , M _P23 : P-type transistor M _N21 , _MN22 , _MN23 : N-type transistor 112: transistor pair _MN24 : first N-type transistor _MN25 : second N-type transistor 120: voltage level converter 130: non-overlapping circuit 131: high Quasi-non-overlapping circuit 132: low-level non-overlapping circuit 140: duty cycle corrector 141: high-level duty cycle correction circuit 141a: first inverter M _P61 : P-type transistor M _N61 : N-type transistor 141b: The first charging capacitor 141c: the second inverter M _P62 : the P-type transistor M _N62 : the N-type transistor 141d: the third inverter M _P63 : the P-type transistor M _N63 : the N-type transistor 141e: the voltage divider Circuit M _P64 : P-type transistor R ₁ : First voltage dividing resistor R ₂ : Second voltage dividing resistor 141f : Second charging capacitor 141g : Current mirror circuit 141h : Fourth inverter M _P65 : P-type transistor M _N64 : N-type transistor M _P67 : The first current mirror switch M _P66 : The first current mirror reference transistor M _P68 : The first current mirror radio transistor M _N66 : The second current mirror switch M _N65 : The second current mirror Reference transistor _MN67 : second current mirror mirror radio transistor 142: low level duty cycle correction circuit 150: process drift detector 151: P-type transistor process drift detection circuit 151a: PMOS inverter M _P41 : P-type Transistor _MN41 : N-type transistor 151b: Charging capacitor 151c: First comparator 151d: First register 151e: Second comparator 151f: Second register 152: N-type transistor process drift detection circuit 152a: NMOS inverter _{MN51 , 52} : N-type transistor Inv: inverter unit 152b: charging capacitor 152c: first comparator 152d: first register 152e: second comparator 152f: second register 160: Output stage M _P11 : P-type output transistor M _P12-16 : P-type compensation transistor M _N11 : N-type output transistor M _N12-16 : N-type compensation transistor 170: Voltage slew rate feedback circuit 171: first comparator 172: second comparator 173: XOR gate 174: first delay unit 175: second delay unit 176: third delay unit 177: logic gate circuit 177a: first and gate 177b: second and gate 177c : third and gate 177d: fourth and gate 177e: first latch 177f: second latch 180: digital logic circuit 181, 182: gate driver circuit 190: floating N-well _MP31 : first P Type electricity Crystal M _P32 : Second P-type transistor _MN31 : First N-type transistor VDD: Power supply voltage VDDIO: External voltage V _D : Detection voltage Data: Data signal DP1: High level data signal DN1: Low level data signal DP2 : The first non-overlapping signal DN2: The second non-overlapping signal DP3: The first duty cycle calibration signal DN3: The second duty cycle calibration signal Clk: The clock signal V _ref1-4 : The reference signal P _code [2:1] : P-type process detection signal P _code [1]: The first bit P _code [2]: The second bit N _code [2:1]: N-type process detection signal N _code [1]: The first bit Element N _code [2]: second bit _VPAD : output voltage SR _r1 : first slew rate reference voltage SR _r2 : second slew rate reference voltage Vgp[5:1], Vgn[5:1]: compensation control Signal Ctr1: First slew rate control signal Ctr2: Second slew rate control signal Cmp1: First comparison signal Cmp2: Second comparison signal V _ctr : Control voltage V _NW : Base voltage Dxor: XOR signal Ddy1: First delay signal Ddy2: Second delay signal Ddy3: Third delay signal DG1: First logic signal DG2: Second logic signal DG3: Third logic signal DG4: Fourth logic signal V1, V2: Nodes V11, V12: Charging voltage V _C1 , V _C2 : Charging voltage DP3b : Reverse first duty cycle correction signal

FIG. 1 is a functional block diagram of a multiple voltage output buffer according to an embodiment of the present invention. Figure 2: A circuit diagram of an external voltage detector according to an embodiment of the present invention. Figure 3: A circuit diagram of a high-level duty cycle correction circuit according to an embodiment of the present invention. FIG. 4 is a circuit diagram of a P-type transistor process drift detection circuit according to an embodiment of the present invention. FIG. 5 is a circuit diagram of an N-type transistor process drift detection circuit according to an embodiment of the present invention. Figure 6: A circuit diagram of a floating N-well in accordance with one embodiment of the present invention. Figure 7: A circuit diagram of a voltage slew rate feedback circuit according to an embodiment of the present invention. Fig. 8 is a timing diagram of the circuit operation of the voltage slew rate feedback circuit according to an embodiment of the present invention. Fig. 9 is a timing diagram of circuit operation of the voltage slew rate feedback circuit according to an embodiment of the present invention. Fig. 10 is a timing diagram of the circuit operation of the voltage slew rate feedback circuit according to an embodiment of the present invention. FIG. 11 is a timing diagram of the circuit operation of the voltage slew rate feedback circuit according to an embodiment of the present invention.

100: Multiple voltage output buffers

110: External voltage detector

120: Voltage level converter

130: Non-overlapping circuits

131: High-level non-overlapping circuit

132: Low-level non-overlapping circuit

140: Duty Cycle Corrector

141: High level duty cycle correction circuit

142: Low level duty cycle correction circuit

150: Process Drift Detector

160: output stage

M _P11 : P-type output transistor

M _P12-16 : P-type compensation transistor

M _N11 : N-type output transistor

M _N12-16 : N-type compensation transistor

170: Voltage slew rate feedback circuit

180: Digital Logic Circuits

181, 182: Gate drive circuit

190: Floating N-well

V _NW : base voltage

VDD: Power supply voltage

VDDIO: External voltage

V _D : Detection voltage

Data: data signal

DP1: High level data signal

DN1: low level data signal

DP2: The first non-overlapping signal

DN2: Second non-overlapping signal

DP3: The first duty cycle correction signal

DN3: Second duty cycle correction signal

Clk: Clock signal

V _ref1-4 : Reference signal

P _code [2:1]: P-type process detection signal

N _code [2:1]: N-type process detection signal

V _PAD : output voltage

SR _r1 : first slew rate reference voltage

SR _r2 : second slew rate reference voltage

Vgp[5:1], Vgn[5:1]: Compensation control signal

Ctr1: The first slew rate control signal

Ctr2: The second slew rate control signal

V _ctr : Control voltage

Claims (10)

A multiple voltage output buffer comprising: an external voltage detector, receiving a power supply voltage and an external voltage, the external voltage detector is used for detecting the voltage magnitudes of the power supply voltage and the external voltage and outputting a detection voltage; A voltage level converter is electrically connected to the external voltage detector, the voltage level converter receives the detection voltage and a data signal, and the voltage level converter converts the voltage level of the data signal according to the detection voltage quasi is a high-level data signal and a low-level data signal; a non-overlapping circuit electrically connected to the voltage level converter to receive the high-level data signal and the low-level data signal, and the non-overlapping circuit is used for converting the high-level data signal and the low-level data signal into a non-overlapping circuit overlapping a first non-overlapping signal and a second non-overlapping signal; a process drift detector, receiving a clock signal and a plurality of reference signals, the process drift detector outputs a P-type process detection signal and an N-type process detection signal according to the clock signal and the reference signals; an output stage electrically connected to the external voltage detector to receive the detection voltage, and the output stage outputs an output voltage; A voltage slew rate feedback circuit is electrically connected to the output stage to receive the output voltage, the voltage slew rate feedback circuit receives a first slew rate reference voltage and a second slew rate reference voltage, the voltage slew rate feedback circuit The transmission circuit determines the slew rate of the output voltage according to the first slew rate reference voltage and the second slew rate reference voltage and outputs a slew rate control signal; and a digital logic circuit electrically connected to the non-overlapping circuit, the process drift detector, the voltage slew rate feedback circuit and the output stage, the digital logic circuit receives the first non-overlapping signal, the second non-overlapping signal The stack signal, the P-type process detection signal, the N-type process detection signal and the slew rate control signal, the digital logic circuit outputs a plurality of compensation control signals to the output stage to control the voltage slew rate of the output voltage. The multiple voltage output buffer of claim 1, wherein the external voltage detector has a first P-type switching transistor, a second P-type switching transistor, a load group and a transistor pair, the first P-type switching transistor The switching transistor receives the power supply voltage and the external voltage, and the first P-type switching transistor outputs a control voltage, the second P-type switching transistor is electrically connected to the first P-type switching transistor, and the second P-type switching transistor is electrically connected to the first P-type switching transistor. The P-type switching transistor receives the power supply voltage and the control voltage, the load group is electrically connected to the first P-type switching transistor to receive the control voltage, and the load group outputs the detection voltage, and the transistor pair is electrically connected the load group and the second P-type switching transistor. The multi-voltage output buffer of claim 2, wherein when the external voltage is greater than the power supply voltage, the first P-type switching transistor is turned on, the second P-type switching transistor is turned off, and the potential of the control voltage is the power supply voltage The potential of the detection voltage is 0.5 times the potential of the power supply voltage. When the external voltage is equal to the power supply voltage, the first P-type switching transistor is turned off, the second P-type switching transistor is turned on, and the control The potential of the voltage and the detection voltage is zero. The multiple voltage output buffer of claim 1, wherein the output stage has a P-type output transistor, a plurality of P-type compensation transistors, an N-type output transistor and a plurality of N-type compensation transistors, the P-type output transistor The transistor is electrically connected to the external voltage detector, the N-type output transistor and the P-type compensation transistors, the P-type output transistor receives the detection voltage, and the N-type output transistor is electrically connected to these The N-type compensation transistor, the P-type output transistor and the N-type output transistor output the output voltage. The multiple voltage output buffer of claim 4, comprising a floating N-type well electrically connected to a base of the P-type output transistor, the floating N-type well receiving the power supply voltage VDD and the output voltage, and the floating N-type well outputs a base voltage to the base of the P-type output transistor. The multiple voltage output buffer of claim 1, wherein the process drift detector has a P-type transistor process drift detection circuit, and the P-type transistor process drift detection circuit has a PMOS inverter, a charging capacitor, a first comparator, a first register, a second comparator and a second register, the PMOS inverter receives the clock signal, the charging capacitor is electrically connected to the PMOS inverter, and The charging capacitor generates a charging voltage, the first comparator is electrically connected to the charging capacitor to receive the charging voltage and a first reference signal, and the first comparator outputs a first comparison signal to the first register , the first register outputs a first bit of the P-type process detection signal, the second comparator is electrically connected to the charging capacitor to receive the charging voltage and a second reference signal, and the second comparator The device outputs a second comparison signal to the second register, and the second register outputs a second bit of the P-type process detection signal. The multiple voltage output buffer of claim 1, which has a high-level duty cycle correction circuit and a low-level duty cycle correction circuit, the high-level duty cycle correction circuit is electrically connected to the non-overlapping circuit to receive the first non-overlapping circuit an overlapping signal, the high-level duty cycle correction circuit is used for correcting the duty cycle of the first non-overlapping signal and outputs a first duty-cycle correction signal to the digital logic circuit, and the low-level duty-cycle correction circuit is used for correcting the first duty cycle correction circuit The duty cycle of the two non-overlapping signals outputs a second duty cycle correction signal to the digital logic circuit. The multiple voltage output buffer of claim 7, wherein the high-level duty cycle correction circuit has a first inverter, a first charging capacitor, a second inverter, a third inverter, and a voltage divider circuit, a second charging capacitor and a current mirror circuit, the first inverter receives the first non-overlapping signal, the first charging capacitor and the second inverter are electrically connected to the first inverter , and the second inverter outputs the first duty cycle correction signal to the digital logic circuit, the third inverter receives the first non-overlapping signal, and the voltage divider circuit is electrically connected to the third inverter The second charging capacitor is electrically connected to the voltage divider circuit, the current mirror circuit is electrically connected to the second charging capacitor and the first inverter, wherein the current mirror circuit is charged by the second charging capacitor The voltage is controlled to change the magnitude of a charging and discharging current for the first charging capacitor. The multiple voltage output buffer of claim 8, wherein the current mirror circuit has a fourth inverter, a first current mirror switch, a first current mirror reference transistor, a first current mirror radio transistor, a A second current mirror switch, a second current mirror reference transistor and a second current mirror radio transistor, the fourth inverter is electrically connected to the second charging capacitor to receive the charging voltage, the first current mirror switch The second charging capacitor and the fourth inverter are electrically connected, and the first current mirror switch is controlled by the charging voltage to be turned on or off, and the first current mirror reference transistor is electrically connected to the fourth inverter , the first current mirror radio transistor is electrically connected to the first current mirror reference transistor and the first inverter, the second current mirror switch is electrically connected to the second charging capacitor and the fourth inverter, And the second current mirror switch is controlled by the charging voltage to be turned on or off, the second current mirror reference transistor is electrically connected to the fourth inverter, and the second current mirror radio transistor is electrically connected to the second current A mirror reference transistor and the first inverter. The multiple voltage output buffer of claim 7, wherein the voltage slew rate feedback circuit has a first comparator, a second comparator, an XOR gate, a first delay unit, a second delay unit, a first Three delay units and a logic gate circuit, the first comparator electrically connects the output stage, the first comparator receives the output voltage and the first slew rate reference voltage, and the first comparator outputs a first comparison signal , the second comparator is electrically connected to the output stage, the second comparator receives the output voltage and the second slew rate reference voltage, and the second comparator outputs a second comparison signal, and the XOR gate is electrically connected to the The first comparator and the second comparator receive the first comparison signal and the second comparison signal, the XOR gate outputs an XOR signal, and the first delay unit receives the first duty cycle correction signal and outputs a first delay signal, the second delay unit receives the first duty cycle correction signal and outputs a second delay signal, the third delay unit receives the reversed first duty cycle correction signal and outputs a third delay signal, the logic The gate circuit is electrically connected to the first delay unit, the second delay unit and the third delay unit to receive the first delay signal, the second delay signal and the third delay signal, and the logic gate circuit outputs a first delay signal The slew rate control signal and a second slew rate control signal are sent to the digital logic circuit.

Images