TWI511206B - 藉由三維整合技術製造高效能碳奈米管電晶體積體電路的方法 - Google Patents
藉由三維整合技術製造高效能碳奈米管電晶體積體電路的方法 Download PDFInfo
- Publication number
- TWI511206B TWI511206B TW100123694A TW100123694A TWI511206B TW I511206 B TWI511206 B TW I511206B TW 100123694 A TW100123694 A TW 100123694A TW 100123694 A TW100123694 A TW 100123694A TW I511206 B TWI511206 B TW I511206B
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- substrate
- layer
- carbon nanotubes
- oxide
- Prior art date
Links
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims description 110
- 229910021393 carbon nanotube Inorganic materials 0.000 title claims description 109
- 239000002041 carbon nanotube Substances 0.000 title claims description 109
- 238000000034 method Methods 0.000 title claims description 45
- 238000005516 engineering process Methods 0.000 title description 10
- 230000010354 integration Effects 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims description 62
- 239000002184 metal Substances 0.000 claims description 60
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 238000000151 deposition Methods 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 239000012808 vapor phase Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 59
- 239000002071 nanotube Substances 0.000 description 17
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 239000000243 solution Substances 0.000 description 10
- 230000008021 deposition Effects 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000002547 anomalous effect Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002238 carbon nanotube film Substances 0.000 description 1
- 238000000224 chemical solution deposition Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- NRHMKIHPTBHXPF-TUJRSCDTSA-M sodium cholate Chemical compound [Na+].C([C@H]1C[C@H]2O)[C@H](O)CC[C@]1(C)[C@@H]1[C@@H]2[C@@H]2CC[C@H]([C@@H](CCC([O-])=O)C)[C@@]2(C)[C@@H](O)C1 NRHMKIHPTBHXPF-TUJRSCDTSA-M 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 238000005199 ultracentrifugation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1094—Conducting structures comprising nanotubes or nanowires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01025—Manganese [Mn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Nanotechnology (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Carbon And Carbon Compounds (AREA)
Description
本發明係關於碳奈米管技術,且更特定言之,本發明係關於製造基於碳奈米管之裝置之技術。
碳奈米管具有對高速且高效能的電路具吸引力之異常電子性質。在使用涉及碳奈米管之裝置及複雜電路中一個主要挑戰在於,碳奈米管生長條件與當前互補金氧半導體(complementary metal-oxide-semiconductor;CMOS)技術之製程限制不相容。例如,化學氣相沈積(chemical vapor deposition;CVD)生長碳奈米管需要至少600℃之生長條件以供產生高品質奈米管,該溫度超過CMOS製程之約350℃至約400℃之溫度容量。
關於該溫度限制之一個可能的解決方案為,將預成形的碳奈米管自溶液沈積於基板上。然而,在後續處理期間,經沈積的碳奈米管可經由氧化而被破壞,且碳奈米管之性質亦由於表面處理而可改變。
實現基於碳奈米管之積體電路之另一實際挑戰為,將碳奈米管對準於電路部件中之其餘部分。儘管在控制奈米管之生長定向及/或沈積位置上已取得很大進展,但尚未解決將奈米管對準於電路中之其餘部分。
因此,基於三維碳奈米管之積體電路裝置整合技術將為需要的。
本發明提供用於製造基於碳奈米管之裝置之技術。在本發明之一個態樣中,提供一種用於製造基於碳奈米管之積體電路之方法。該方法包含以下步驟。提供包含碳奈米管之第一晶圓。提供包含一或更多裝置元件之第二晶圓。藉由將第一晶圓與第二晶圓結合在一起,使碳奈米管中之一或更多者與裝置元件中之一或更多者連接。
可將碳奈米管沈積於第一基板上。可將第一氧化物層沈積於覆蓋碳奈米管之基板上。可形成一或更多第一電極,該等第一電極至少部分地延伸穿過第一氧化物層且該等第一電極與碳奈米管中之一或更多者接觸。可在第二基板上製造一或更多裝置元件。可將第二氧化物層沈積於裝置元件上。可形成一或更多第二電極,該等第二電極至少部分地延伸穿過第二氧化物層,該第二氧化物層連接至裝置元件中之一或更多者。
在本發明之另一態樣中,提供一種基於碳奈米管之積體電路。該基於碳奈米管之積體電路包括:第一晶圓,該第一晶圓包含碳奈米管;以及第二晶圓,該第二晶圓包含一或更多裝置元件,其中第一晶圓結合至第二晶圓以使得碳奈米管中之一或更多者與裝置元件中之一或更多者連接。
藉由參閱以下詳細描述及圖式,將獲得對本發明以及本發明之其他特徵結構及優點之更完全的理解。
為成功地將碳奈米管用作實際裝置及/或電路中主動元件,需要新製造方案結合現有的互補金氧半導體(CMOS)技術及碳奈米管。本教示提供此種製造方案。
第1圖至第15圖為圖示用於製造基於碳奈米管之積體電路之示例性方法的圖式。在該特定實例中,藉由以下操作形成基於碳奈米管之電晶體:提供製造於一個基板(本文中稱為碳奈米管晶圓)上之碳奈米管及製造於另一基板(本文中稱為裝置晶圓)上之CMOS裝置元件(及相關聯佈線),隨後經由使用面對面結合來將碳奈米管晶圓與裝置晶圓以三維配置結合在一起,連接碳奈米管與裝置元件中之一或更多者。
三維整合成為極有潛力的候選者以實現用於基於碳奈米管之電子設備之封裝及積體電路(integrated circuit;IC)技術差距。已證實堆疊CMOS當前技術之主動裝置層之能力。即使在沒有放大縮小(scaling)之情況下,三維整合技術亦可增加系統效能。具體而言,三維整合提供了減小的總佈線長度(及相應降低的互連延遲時間)、顯著增大數目個晶片間之互連以及允許相異材料、製程技術及功能成功整合之能力。另外,應注意,在基於碳奈米管之電路中,互連之寄生電容及電阻大大地影響了系統效能。
如第1圖橫截面圖中所示,可藉由首先將碳奈米管102沈積於氧化物覆蓋的基板上形成碳奈米管晶圓。根據示例性實施例,氧化物覆蓋的基板包括覆蓋有氧化物105之矽(Si)基板104。在該實例中,將碳奈米管102沈積於氧化物105上。可使用化學氣相沈積(CVD)製程生長該等碳奈米管,或將該等碳奈米管自溶液進行沈積。該等CVD及溶液沈積製程為本領域中所熟知。根據使用CVD製程之示例性實施例,首先將金屬催化劑(例如,鉬(Mo)、鐵(Fe)、鎳(Ni))沈積於氧化物覆蓋的基板上,隨後使高溫(例如,介於約450攝氏度(℃)與約900℃之間)含碳氣體(諸如,乙醇或甲烷)在基板表面上流動以形成碳奈米管。
對將碳奈米管用作電路(諸如,電晶體通道)中主動部件之應用而言,需要半導體奈米管。實務上,通常獲得半導體碳奈米管與金屬碳奈米管之混合物。在該實例中,使用具有高純度(高於百分之九十九(99%))之半導體奈米管之碳奈米管薄膜,將該等半導體奈米管自純化的奈米管溶液進行沈積。本文所用之術語純度代表半導體碳奈米管與金屬碳奈米管之間的比率。在溶液中分離金屬碳奈米管輿半導體碳奈米管之方法為熟習此項技術者所熟知。在一個實例中,在用適當的介面活性劑(諸如,膽酸鈉)進行官能化之後,水溶液中金屬奈米管與半導體奈米管之間的浮力密度差可用以分離具有超離心之兩種類型的奈米管。可藉由該方法製備含有高純度(高於99.9%)之半導體碳奈米管之溶液。
在第2圖中圖示碳奈米管晶圓之俯視圖(自有利位置A)。如第2圖中所示,碳奈米管102沿(氧化物覆蓋的基板)之氧化物105之頂表面對準。然而,沒有必要將所有奈米管對準。在第2圖中,僅為了清楚起見而平行繪製該等碳奈米管。
如第3圖橫截面圖中所示,隨後將氧化物層106沈積於覆蓋碳奈米管102之經氧化物覆蓋的基板上。該氧化物層將用於兩個目的。第一,氧化物層106將用作碳奈米管之閘極介電質。第二,氧化物層106稍後將用於製造程序中以保護碳奈米管免受後續處理之損壞。可使用原子層沈積(atomic layer deposition;ALD)或由低溫(300℃以下)CVD或由兩種沈積製程之組合,來沈積氧化物層106。低溫氧化物CVD製程比高溫CVD製程較佳,以最小化對奈米管品質之潛在不良影響。
如第4圖橫截面圖中所示,將遮罩層108沈積於氧化物層106上。遮罩層108可包含諸如聚甲基丙烯酸甲酯(PMMA)之光阻材料(亦即,電子束(e-beam)抗蝕劑),或硬光罩(金屬)材料。隨後,以數個通孔之覆蓋區(footprint)及位置佈局圖樣遮罩層108,該等通孔將用以界定基於碳奈米管之電晶體之源極電極及汲極電極(參見下文)。用於沈積且佈局圖樣遮罩層之製程為熟習此項技術者所已知,且因此本文不再進一步描述該等製程。
如第5圖橫截面圖中所示,使用濕式蝕刻製程蝕刻氧化物層106穿過經佈局圖樣之遮罩層108,從而形成通孔110,該等通孔110曝露碳奈米管102之區域以接收金屬電極(參見下文)。在完成濕式蝕刻之後,使用例如丙酮移除經佈局圖樣之遮罩層108。
如第6圖橫截面圖中所示,將金屬沈積於氧化物層106上,從而填充通孔110。根據示例性實施例,金屬係由兩個層組成。首先經沈積的層(亦即,金屬層112)為用以能夠較好地與碳奈米管接觸之薄金屬層,且該層包含諸如鈀(Pd)之金屬。金屬層112具有約1奈米(nm)至約100 nm之厚度,且如第6圖中所示,該金屬層112作為氧化物層106之頂表面/碳奈米管102之曝露區域的襯裡。沈積於金屬層112上之第二層(亦即,金屬層114)用以允許晶圓結合步驟(參見下文)中之黏附性,且該第二層包含銅(Cu)。將金屬層114沈積於金屬層112上且金屬層114填充通孔110。如第6圖中所示,金屬層114可在氧化物層106之表面上方延伸。金屬層114具有約5 nm至約300微米(μm)之厚度。僅舉例而言,可藉由熱蒸發形成金屬層112,而可藉由電化學沈積形成金屬層114以形成更厚的金屬薄膜。
如第7圖橫截面圖中所示,隨後,(例如,使用化學機械拋光(chemical mechanical polishing;CMP))拋光金屬層112及金屬層114,以使金屬層114變薄至所要厚度。該拋光製程亦將自金屬層112移除任何過量金屬,且該拋光製程可進一步使氧化物層106變薄。根據示例性實施例,在變薄之後,氧化物層106具有約5 nm至約1 μm之厚度。由CMP製程之持續時間控制所移除的氧化物層106之數量。在製程之該步驟中,界定不同的電晶體接觸區115。在第7圖中標示圖示示例性源極電極區及汲極電極區。結果為完成的碳奈米管晶圓,將使用面對面結合使該碳奈米管晶圓結合至裝置晶圓(參見下文)。
隨後提供裝置晶圓。如第8圖橫截面圖中所示,可藉由首先在(亦即)絕緣層上矽晶(silicon-on-insulator;SOI)基板120上製造一或更多裝置元件118來形成裝置晶圓,該絕緣層上矽晶基板120具有SOI層122及Si層116,該SOI層122位於埋藏氧化物(buried oxide;BOX) 124上。根據示例性實施例,每一裝置元件包含源極區118s及閘極區118g,該源極區118s由通道118c連接至汲極區118d,並連接至位於通道上之該閘極區118g。根據示例性實施例,裝置元件118包含矽基CMOS裝置部件,諸如記憶體及/或邏輯電晶體。用於製造SOI基板中此類裝置元件之技術為熟習此項技術者所已知,且因此本文不再進一步描述該等技術。如第9圖橫截面圖中所示,將氧化物層126沈積於裝置元件118上。在下文詳述之晶圓結合步驟期間,氧化物層126將用作結合氧化物層。隨後,在與裝置元件118接觸之氧化物層126中形成一或更多金屬層128。
接著,在與金屬層128(金屬層128連接裝置元件118與電極130)接觸之氧化物層126中形成一或更多電極130。電極130形成裝置元件118之源極電極/汲極電極/閘極電極,且電極130包含Cu。在第9圖中標示圖示源極(S)電極/汲極(D)電極/閘極(G)電極之示例性配置。
如第10圖橫截面圖中所示,翻轉裝置晶圓以達成與碳奈米管晶圓之面對面結合(亦即,對準晶圓以允許每一晶圓之頂表面或「面」與另一晶圓之相應頂表面或「面」結合)。儘管在該實例中翻轉裝置層,但可替代地藉由翻轉碳奈米管晶圓來執行相同製程。第11圖橫截面圖中圖示在將兩個晶圓結合在一起後的所得裝置佈局。此處,結合方法係同時基於Cu與Cu結合(介於碳奈米管晶圓之接觸區115與裝置晶圓之源極電極/汲極電極/閘極電極130之間)與氧化物與氧化物結合(oxide-to-oxide bond)(介於碳奈米管晶圓之氧化物層106與裝置晶圓之氧化物層126之間)。所使用的結合溫度低於400℃,以便在結合製程期間不破壞裝置層中之部件。Cu與Cu結合製程及氧化物與氧化物結合製程為熟習此項技術者所已知,且因此本文不再進一步描述該等製程。
在將兩個晶圓結合在一起後,下一步驟為基板移除製程。由於在結合後現存在來自兩個晶圓之兩個基板,所以選擇移除哪個基板依賴於電路設計(亦即,以允許製造額外結構層)。在第12圖橫截面圖中,使基板120變薄(亦即,自裝置晶圓移除Si層116)。根據示例性實施例,使用CMP或其他類似拋光及/或研磨製程移除所要基板。如上強調,基板120為SOI基板,且同樣地BOX 124為CMP製程之終止層。
在第13圖橫截面圖中,自碳奈米管晶圓移除基板104,從而留下氧化物105。如上強調,碳奈米管晶圓係基於氧化物覆蓋的Si基板。在基板移除期間,氧化物可充當終止層。可藉由使用移除矽而非氧化物之蝕刻製程來達成該類型之選擇性蝕刻。
可在結合的晶圓結構上製造額外裝置層或下一金屬層Mn。進行製造所在之表面可取決於以上移除哪個基板。具體而言,若已移除基板120(參見如上所述之第12圖),則在BOX 124附近形成由層132示意性表示的額外裝置層/金屬層。在第14圖橫截面圖中圖示了該配置。另一方面,若已移除基板104(參見如上所述之第13圖),則在氧化物層105附近形成由層134示意性表示的額外裝置層/金屬層。在第15圖橫截面圖中圖示了該配置。應注意,在第15圖中所示之配置中,翻轉結合的晶圓結構以允許由上至下製造額外裝置層/金屬層。
總之,本技術為基於三維碳奈米管之IC裝置整合提供了成功且易於實施的解決方案。本技術之優點包括(但不限於):(1)可由各式各樣不同方法來製備碳奈米管,該等方法包括(但不限於)CVD生長奈米管、來自溶液沈積之奈米管、奈米管薄膜;(2)可在標準的清潔室設施中預製複雜電路,而不存在來自碳奈米管及金屬催化劑之潛在污染;(3)晶圓結合製程之對準確保奈米管始終併入電路之理想位置;(4)仍可保持現有CMOS裝置之需求,諸如在製程期間之溫度、濕式蝕刻環境、周圍氣體,因為在另一晶圓上單獨製造奈米管;以及(5)可顯著降低電路延遲時間,在碳奈米管電路之情況下該電路延遲時間由互連支配。
儘管本文已描述本發明之說明性實施例,但應理解本發明不限於彼等精確實施例,且在不脫離本發明之範疇的情況下,熟習此項技術者可進行各種其他改變及修改。
102...碳奈米管
104...矽基板/基板
105...氧化物層/氧化物
106...氧化物層
108...遮罩層
110...通孔
112...金屬層
114...金屬層
115...電晶體接觸區
116...Si層
118...裝置元件
118c...通道
118d...汲極區
118g...閘極區
118s...源極區
120...絕緣層上矽晶基板/基板
122...SOI層
124...埋藏氧化物/BOX
126...氧化物層
128...金屬層
130...電極
132...層
134...層
第1圖為圖示根據本發明之實施例之碳奈米管晶圓的橫截面圖,其中將碳奈米管沈積於氧化物覆蓋的基板上;
第2圖為圖示根據本發明之實施例之第1圖之碳奈米管晶圓之俯視圖的圖式;
第3圖為根據本發明之實施例之碳奈米管晶圓的橫截面圖,該圖圖示將氧化物層沈積於覆蓋碳奈米管之氧化物覆蓋的基板上;
第4圖為根據本發明之實施例之碳奈米管晶圓的橫截面圖,該圖圖示將遮罩層沈積於氧化物層上且佈局圖樣遮罩層;
第5圖為根據本發明之實施例之碳奈米管晶圓的橫截面圖,該圖圖示蝕刻氧化物層穿過經佈局圖樣之遮罩層從而形成通孔,該等通孔曝露碳奈米管之區域以接收金屬電極;
第6圖為根據本發明之實施例之碳奈米管晶圓的橫截面圖,該圖圖示將金屬沈積於氧化物層上且填充通孔;
第7圖為根據本發明之實施例之碳奈米管晶圓的橫截面圖,該圖圖示將金屬拋光直至所要厚度;
第8圖為圖示根據本發明之實施例之裝置晶圓的橫截面圖,其中在絕緣層上矽晶(SOI)基板上製造一或更多裝置元件;
第9圖為根據本發明之實施例之裝置晶圓的橫截面圖,該圖圖示將氧化物層沈積於裝置元件上、在與裝置元件接觸之氧化物層中形成一或更多金屬層及在與金屬層接觸之氧化物層中形成一或更多電極;
第10圖為圖示根據本發明之實施例之裝置晶圓的橫截面圖,翻轉該裝置晶圓以達成與碳奈米管晶圓之面對面結合;
第11圖為圖示根據本發明之實施例在將裝置晶圓與碳奈米管晶圓結合在一起後所得裝置佈局的橫截面圖;
第12圖為圖示根據本發明之實施例自裝置晶圓移除大部分基板的橫截面圖;
第13圖為圖示根據本發明之實施例自碳奈米管晶圓移除基板的橫截面圖;
第14圖為圖示根據本發明之實施例在裝置晶圓附近形成額外裝置層/金屬層的橫截面圖;以及
第15圖為圖示根據本發明之實施例在碳奈米管晶圓附近形成額外裝置層/金屬層的橫截面圖。
102...碳奈米管
104...矽基板/基板
105...氧化物層/氧化物
106...氧化物層
116...Si層
120...絕緣層上矽晶基板/基板
124...埋藏氧化物/BOX
126...氧化物層
Claims (13)
- 一種用於製造一基於碳奈米管之積體電路之方法,包含以下步驟:提供包含碳奈米管之一第一晶圓,形成該第一晶圓係藉由沈積該等碳奈米管於一第一基板上、沈積一第一氧化層至覆蓋該等碳奈米管之該第一基板上及形成一或更多個第一電極,該等第一電極至少部分地延伸穿過該第一氧化物層且與該等碳奈米管中之一或更多者接觸;提供包含一或更多裝置元件之一第二晶圓,形成該第二晶圓係藉由製造該等裝置元件於一第二基板上、沈積一第二氧化層於該等裝置元件之上及形成一或更多個第二電極,該等第二電極至少部分地延伸穿過連接至該等裝置元件之一或更多者之該第二氧化物層;以及藉由將該第一晶圓與該第二晶圓結合在一起,連接該等碳奈米管中之一或更多者與該等裝置元件中之一或更多者。
- 如請求項1所述之方法,進一步包含以下步驟:在與該等裝置元件接觸之該第二氧化物層中形成一或更多金屬層。
- 如請求項1所述之方法,其中該等第一電極與該等第二電極皆包含銅,且其中該連接該等碳奈米管與該等裝置元件之步驟進一步包含以下步驟:在該第一氧化物層與該第二氧化物層之間形成一氧化物與氧化物結合(oxide-to-oxide bond);以及在該等第一電極與該等第二電極之間形成一銅與銅結合(copper-to-copper bond)。
- 如請求項1所述之方法,其中該第一基板包含一經氧化物覆蓋的基板;或其中該第二基板包含一絕緣層上矽晶(silicon-on-insulator)基板;或其中使用化學氣相沈積將該等碳奈米管沈積於該第一基板上;或其中將該等碳奈米管自一溶液沈積於該第一基板上;或其中該等碳奈米管包含半導體碳奈米管與金屬碳奈米管之一混合物,且其中該混合物含有高於百分之九十九之半導體碳奈米管。
- 如請求項1所述之方法,進一步包含以下步驟:形成穿過該第一氧化物層之通孔,該等通孔曝露該等碳奈米管之區域;沈積一第一金屬層,該第一金屬層作為該等碳奈米管之該等曝露區域之襯裡;以及將一第二金屬層沈積於該第一金屬層上且填充該等通孔。
- 如請求項5所述之方法,其中該形成穿過該第一氧化物層之該等通孔之步驟進一步包含以下步驟:將一遮罩層沈積於該第一氧化物層上;以該等通孔中之每一者之一覆蓋區(footprint)及位置在該遮罩層上佈局圖樣;蝕刻該第一氧化物層穿過該經佈局圖樣之遮罩層以形成該等通孔;以及移除該遮罩層;或其中使用一濕式蝕刻製程來執行以下步驟,蝕刻該第一氧化物層穿過該經佈局圖樣之遮罩層以形成該等通孔;或其中該第一金屬層包含鈀;或其中該第一金屬層具有約1奈米至約100奈米之一厚度;或其中該第二金屬層包含銅。
- 如請求項5所述之方法,進一步包含以下步驟:使該第二金屬層變薄;或其中使用化學機械拋光使該第二金屬層變薄。
- 如請求項1所述之方法,進一步包含以下步驟:翻轉該第一晶圓或該第二晶圓中之一者,以允許該第一晶圓與該第二晶圓之間的面對面結合。
- 如請求項1所述之方法,進一步包含以下步驟:使該第一基板或該第二基板中之一者變薄。
- 一種基於碳奈米管之積體電路,包含:一第一晶圓,該第一晶圓包含碳奈米管,該第一晶圓具有:一第一基板,該等碳奈米管係置於該第一基板上,一第一氧化層,該第一氧化層覆蓋該等碳奈米管,以及一或更多個第一電極,該等第一電極至少部分地延伸穿過該第一氧化物層且與該等碳奈米管中之一或更多者接觸;以及一第二晶圓,該第二晶圓包含一或更多裝置元件,該第二晶圓具有:一第二基板,該等裝置元件係製造於該第二基板上,一第二氧化層,該第二氧化層於該等裝置元件之上,以及一或更多個第二電極,該等第二電極至少部分地延伸穿過連接至該等裝置元件之一或更多者之該第二氧化物層,其中該第一晶圓結合至該第二晶圓以使得該等碳奈米管中之一或更多者與該等裝置元件中之一或更多者連接。
- 如請求項10所述之基於碳奈米管之積體電路,其中該第二晶圓進一步包含:一或更多金屬層,該等金屬層位於與該等裝置元件接觸之該第二氧化物層中。
- 如請求項10所述之基於碳奈米管之積體電路,其中該等第一電極與該等第二電極皆包含銅,且其中藉由該第一氧化物層與該第二氧化物層之間的一氧化物與氧化物結合及該等第一電極與該等第二電極之間的一銅與銅結合,使該等碳奈米管與該等裝置元件中之一或更多者連接。
- 如請求項10所述之基於碳奈米管之積體電路,其中該第一基板包含一氧化物覆蓋的基板;或其中該第二基板包含一絕緣層上矽晶基板。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/831,656 US8455297B1 (en) | 2010-07-07 | 2010-07-07 | Method to fabricate high performance carbon nanotube transistor integrated circuits by three-dimensional integration technology |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201218285A TW201218285A (en) | 2012-05-01 |
TWI511206B true TWI511206B (zh) | 2015-12-01 |
Family
ID=44626983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW100123694A TWI511206B (zh) | 2010-07-07 | 2011-07-05 | 藉由三維整合技術製造高效能碳奈米管電晶體積體電路的方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8455297B1 (zh) |
CN (1) | CN102986014B (zh) |
TW (1) | TWI511206B (zh) |
WO (1) | WO2012004068A1 (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9502152B2 (en) * | 2010-11-01 | 2016-11-22 | Samsung Electronics Co., Ltd. | Method of selective separation of semiconducting carbon nanotubes, dispersion of semiconducting carbon nanotubes, and electronic device including carbon nanotubes separated by using the method |
US8748885B2 (en) * | 2012-02-10 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Soft material wafer bonding and method of bonding |
US9443758B2 (en) | 2013-12-11 | 2016-09-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Connecting techniques for stacked CMOS devices |
JP6330415B2 (ja) * | 2014-03-27 | 2018-05-30 | 富士通株式会社 | 半導体装置の製造方法 |
CN105081490B (zh) * | 2014-04-23 | 2017-09-12 | 北京富纳特创新科技有限公司 | 线切割电极丝及线切割装置 |
US10103540B2 (en) * | 2014-04-24 | 2018-10-16 | General Electric Company | Method and system for transient voltage suppression devices with active control |
US9859394B2 (en) | 2014-12-18 | 2018-01-02 | Agilome, Inc. | Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids |
US9857328B2 (en) | 2014-12-18 | 2018-01-02 | Agilome, Inc. | Chemically-sensitive field effect transistors, systems and methods for manufacturing and using the same |
US10020300B2 (en) | 2014-12-18 | 2018-07-10 | Agilome, Inc. | Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids |
US10006910B2 (en) | 2014-12-18 | 2018-06-26 | Agilome, Inc. | Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same |
US9618474B2 (en) | 2014-12-18 | 2017-04-11 | Edico Genome, Inc. | Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids |
US10429342B2 (en) | 2014-12-18 | 2019-10-01 | Edico Genome Corporation | Chemically-sensitive field effect transistor |
WO2017201081A1 (en) | 2016-05-16 | 2017-11-23 | Agilome, Inc. | Graphene fet devices, systems, and methods of using the same for sequencing nucleic acids |
CN113035781B (zh) * | 2021-03-09 | 2022-06-28 | 中国科学院微电子研究所 | 一种晶圆级二维材料的转移方法及器件制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050156320A1 (en) * | 2000-12-29 | 2005-07-21 | Stmicroelectronics S.R.I. | Integrated device including connections on a separate wafer |
US20060290343A1 (en) * | 2005-06-24 | 2006-12-28 | Crafts Douglas E | Temporary planar electrical contact device and method using vertically-compressible nanotube contact structures |
US20070205450A1 (en) * | 2004-10-22 | 2007-09-06 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5756395A (en) | 1995-08-18 | 1998-05-26 | Lsi Logic Corporation | Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures |
DE10036897C1 (de) | 2000-07-28 | 2002-01-03 | Infineon Technologies Ag | Feldeffekttransistor, Schaltungsanordnung und Verfahren zum Herstellen eines Feldeffekttransistors |
US7084507B2 (en) | 2001-05-02 | 2006-08-01 | Fujitsu Limited | Integrated circuit device and method of producing the same |
US6933222B2 (en) | 2003-01-02 | 2005-08-23 | Intel Corporation | Microcircuit fabrication and interconnection |
WO2005019104A2 (en) | 2003-08-18 | 2005-03-03 | President And Fellows Of Harvard College | Controlled nanotube fabrication and uses |
DE102004035368B4 (de) | 2004-07-21 | 2007-10-18 | Infineon Technologies Ag | Substrat mit Leiterbahnen und Herstellung der Leiterbahnen auf Substraten für Halbleiterbauteile |
JP4405427B2 (ja) | 2005-05-10 | 2010-01-27 | 株式会社東芝 | スイッチング素子 |
US7626257B2 (en) | 2006-01-18 | 2009-12-01 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
-
2010
- 2010-07-07 US US12/831,656 patent/US8455297B1/en active Active
-
2011
- 2011-06-01 CN CN201180033207.3A patent/CN102986014B/zh active Active
- 2011-06-01 WO PCT/EP2011/059133 patent/WO2012004068A1/en active Application Filing
- 2011-07-05 TW TW100123694A patent/TWI511206B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050156320A1 (en) * | 2000-12-29 | 2005-07-21 | Stmicroelectronics S.R.I. | Integrated device including connections on a separate wafer |
US20070205450A1 (en) * | 2004-10-22 | 2007-09-06 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
US20060290343A1 (en) * | 2005-06-24 | 2006-12-28 | Crafts Douglas E | Temporary planar electrical contact device and method using vertically-compressible nanotube contact structures |
Also Published As
Publication number | Publication date |
---|---|
WO2012004068A1 (en) | 2012-01-12 |
CN102986014A (zh) | 2013-03-20 |
TW201218285A (en) | 2012-05-01 |
CN102986014B (zh) | 2015-08-05 |
US8455297B1 (en) | 2013-06-04 |
US20130119548A1 (en) | 2013-05-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI511206B (zh) | 藉由三維整合技術製造高效能碳奈米管電晶體積體電路的方法 | |
JP5719430B2 (ja) | グラフェン・チャネルに基づく装置およびその製作方法 | |
US10796958B2 (en) | 3D integration method using SOI substrates and structures produced thereby | |
TWI525775B (zh) | 石墨烯基底的三維積體電路裝置 | |
TWI405321B (zh) | 三維多層堆疊半導體結構及其製造方法 | |
US9391011B2 (en) | Semiconductor structures including fluidic microchannels for cooling and related methods | |
JP4979320B2 (ja) | 半導体ウェハおよびその製造方法、ならびに半導体装置の製造方法 | |
JP5426417B2 (ja) | 半導体装置およびその製造方法 | |
US20120248621A1 (en) | Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods | |
TW201023331A (en) | Semiconductor device and method for forming the same | |
TW201010005A (en) | Hybrid conductive vias including small dimension active surface ends and larger dimension back side ends, semiconductor devices including the same, and associated methods | |
US20170271207A9 (en) | Novel 3D Integration Method Using SOI Substrates And Structures Produced Thereby | |
TW201308556A (zh) | 使用多層介層窗的3d積體電路 | |
TWI590459B (zh) | A method of manufacturing the conductive structure, and a method of manufacturing the electronic device | |
JP2021535597A (ja) | 接合メモリ装置およびその製作方法 | |
JP2008270354A (ja) | 三次元半導体デバイスの製造方法、基板生産物の製造方法、基板生産物、及び三次元半導体デバイス | |
JP2008251701A (ja) | 配線構造及びその形成方法 | |
CN109712961B (zh) | 三维集成电路及其制造方法 | |
TWI524421B (zh) | 半導體積體電路與其製造方法 | |
JP2009253279A (ja) | 素子相互接続体 | |
JP2013537363A (ja) | 犠牲材料を使用して半導体構造体中にウェーハ貫通相互接続部を形成する方法、及びかかる方法により形成される半導体構造体 | |
JP5672503B2 (ja) | スルホールビアのための炭素ベース材質を備えた半導体デバイス | |
US20240128231A1 (en) | Semiconductor Devices and Methods of Manufacture | |
TWI793560B (zh) | 半導體裝置及其製造方法 | |
CN107293484A (zh) | 一种转接板制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |