TWI506783B - Semiconductor structure and manufacturing method and operating method of the same - Google Patents

Description

Semiconductor structure, manufacturing method and operating method thereof

The present invention relates to a semiconductor structure, a method of fabricating the same, and a method of operating the same, and more particularly to a metal oxide semiconductor, a method of fabricating the same, and a method of operation.

In recent decades, the semiconductor industry has continued to shrink the size of semiconductor structures while improving the unit cost of speed, performance, density, and integrated circuits. A general semiconductor structure, such as a method of fabricating a reinforced metal oxide semiconductor (EDMOS), is to dope all of the substrate exposed by the active region defining structure to form a coding layer. The opposite edges of the coding layer are aligned with the edges of the active region definition structure. However, such a semiconductor structure has a problem of large leakage current.

The present invention relates to a semiconductor structure, a method of fabricating the same, and a method of operation. The semiconductor structure of the embodiment has a small leakage current compared to a general semiconductor structure.

A semiconductor structure is provided. The semiconductor structure includes a first doped region, a second doped region, a third doped region, a fourth doped region, and a dielectric structure. The second doped region and the third doped region form a doped coding layer. The doped coding layer is located in the first doped region and the fourth doped region. The dielectric structure is on the first doped region. The edge of the doped coding layer is between the edge of the adjacent fourth doped region and the edge of the dielectric structure.

A method of fabricating a semiconductor structure is provided. The manufacturing method includes the following steps. A first doped region is formed. A second doped region is formed. A third doped region is formed. The second doped region and the third doped region form a doped coding layer. A fourth doped region is formed. The doped coding layer is located in the first doped region and the fourth doped region. A dielectric structure is formed on the first doped region. The edge of the doped coding layer is between the edge of the adjacent fourth doped region and the edge of the dielectric structure.

A method of operating a semiconductor structure is provided. The semiconductor structure includes a first doped region, a second doped region, a third doped region, a fourth doped region, a dielectric structure, and a gate structure. The second doped region and the third doped region form a doped coding layer. The doped coding layer is located in the first doped region and the fourth doped region. The dielectric structure is on the first doped region. The edge of the doped coding layer is between the edge of the adjacent fourth doped region and the edge of the dielectric structure. The gate structure is located on the doped coding layer and the first doped region. The method of operation includes the following steps. A bias is provided between the first electrode electrically connected to the first doped region and the second electrode electrically connected to the third doped region. The voltage of the third electrode of the gate structure is electrically connected to control the turn-on current of the semiconductor structure or to turn off the semiconductor structure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a semiconductor structure in accordance with an embodiment. Referring to FIG. 1, the semiconductor structure includes a substrate 2. The first doped region 4 is located in the substrate 2. The second doping region 6 is located between the first doping region 4 and the third doping region 8. The fourth doping region 10 is located in the first doping region 4. The third doping region 8 is located in the fourth doping region 10. The fifth doping region 12 is located in the first doping region 4. The sixth doping region 14 is located in the third doping region 8. The seventh doping region 16 may be located between the fourth doping region 10 and the third doping region 8. The dielectric structure 22 is located on the first doped region 4. The gate structure 24 is located on the first doping region 4, the second doping region 6, and the third doping region 8. The gate structure 24 can also extend onto the dielectric structure 22.

Referring to FIG. 1 , in an embodiment, the first doping region 4 , the second doping region 6 , the third doping region 8 , the fifth doping region 12 , and the sixth doping region 14 have the first Conductive type. The substrate 2, the fourth doping region 10, and the seventh doping region 16 have a second conductivity type opposite to the first conductivity type. For example, the first conductivity type is N type, and the second conductivity type is P type. The impurity concentration of the fifth doping region 12 may be greater than the impurity concentration of the first doping region 4. The impurity concentration of the sixth doping region 14 may be greater than the impurity concentration of the third doping region 8. The fifth doped region 12 and the sixth doped region 14 may be heavily doped. The seventh doped region 16 can include a first portion 18 and a second portion 20. The impurity concentration of the first portion 18 may be greater than the impurity concentration of the second portion 20. The semiconductor structure can be a metal oxide semiconductor such as LDMOS or EDMOS, such as LDNMOS, LDPMOS, EDNMOS or EDPMOS. For example, the fifth doping region 12 can be used as a drain. The sixth doping region 14 can serve as a source.

Referring to FIG. 1 , in the embodiment, the impurity concentration of the first doping region 4 is smaller than the impurity concentration of the second doping region 6 . The impurity concentration of the third doping region 8 is also smaller than the impurity concentration of the second doping region 6. The second doped region 6 and the dielectric structure 22 are separated by the first doped region 1. The second doping region 6 and the third doping region 8 form a doped coding layer 7. The edge 31 of the doped coding layer 7 is between the edge 33 of the adjacent fourth doped region 10 and the edge 35 of the dielectric structure 22. In one embodiment, the distance D1 between the edge (of the edge 31) of the doped coding layer 7 and the edge (of the edge 35) of the dielectric structure 22 is about 0.4 um. The distance D2 between the edge (of the edge 37) of the doped coding layer 7 and the edge (of the edge 39) of the active region defining structure 5 is about 0.4 um. The semiconductor structure of the embodiment has a low leakage current.

In an embodiment, the method of operating the semiconductor structure includes having a bias voltage between the electrode 26 electrically connected to the first doped region 4 and the electrode 28 electrically connected to the third doped region 8. In addition, the variably electrically connected voltage to the electrode 30 of the gate structure 24 is controlled to control the turn-on current of the semiconductor structure or to turn off the semiconductor structure. The semiconductor structure of the embodiment has a low leakage current.

Figure 2 is a graph showing the drain current-gate voltage (Id-Vg) curve for a semiconductor structure of a general semiconductor structure and an embodiment. One of them applies a positive voltage to the drain. The source is grounded. Referring to FIG. 2, in the case where a negative voltage is applied to the gate, the current value of the semiconductor structure of the embodiment is smaller than that of the general semiconductor structure. Therefore, the off-state leakage current of the semiconductor structure of the embodiment is smaller than that of the general semiconductor structure.

3 to 5 illustrate a method of fabricating a semiconductor structure in an embodiment. Referring to FIG. 3, a first doped region 104 is formed in the substrate 102. A fourth doping region 110 is formed in the first doping region 104. An active region defining structure 105 is formed on the substrate 102. Active region definition structure 105 can include an insulating or dielectric material. For example, active region definition structure 105 can include an oxide such as hafnium oxide. Active region definition structure 105 can be field oxide (FOX) or shallow trench isolation (STI). Referring to FIG. 4, a dielectric structure 122 is formed on the first doped region 104. The dielectric structure 122 is not limited to the field oxide as shown in FIG. 4, and may include shallow trench isolation.

Referring to FIG. 4, a doping step is performed to form the doped coding layer 107 in the fourth doping region 110. The doping step of forming the doped coding layer 107 can also be performed on the first doped region 104. The edge 131 of the doped coding layer 107 is between the edge 133 of the adjacent fourth doped region 110 and the edge 135 of the dielectric structure 122. A portion of the doped code layer 107 located in the fourth doped region 110 is a third doped region 108. The portion of the edge of the doped coding layer 107 that extends beyond the edge 133 is the second doped region 106. In one embodiment, the doped coding layer 107 including the second doping region 106 and the third doping region 108 is simultaneously formed by a doping process, and the second doping region 106 is formed on the same conductivity type. In a doped region 104, the third doping region 108 is formed in the fourth doping region 110 having an opposite conductivity type, and thus the impurity concentration of the third doping region 108 (for example, the first conductivity type impurity impurity concentration) is It is smaller than the impurity concentration of the second doping region 106 (for example, the first conductivity type impurity net concentration). Further, the impurity concentration of the first doping region 104 (for example, the net concentration of the first conductivity type impurity) is also smaller than the impurity concentration of the second doping region 106 (for example, the net concentration of the first conductivity type impurity).

Referring to FIG. 5, a gate structure 124 is formed. The method of forming the gate structure 124 includes forming a gate dielectric layer 125 on the first doped region 104, the second doped region 106, and the third doped region 108. The gate electrode layer 127 can also extend onto the dielectric structure 122. The gate electrode layer 127 may include a metal, a polysilicon or a metal halide.

Referring to FIG. 5, a fifth doping region 112 and a sixth doping region 114 are formed in the first doping region 104 and the third doping region 108, respectively. In an embodiment, the fifth doping region 112 and the sixth doping region 114 are formed in a heavily doped manner. The seventh doping region 116 can be formed in a heavily doped manner. Seventh blend The impurity concentration of the first portion 118 formed in the fourth doping region 110 having the same conductivity type (for example, the net concentration of the second conductivity type impurity) is larger than the third doping region 108 formed in the opposite conductivity type. The impurity concentration of the second portion 120 in the middle (for example, the net concentration of the second conductivity type impurity).

Figure 6 is a cross-sectional view of a semiconductor structure in accordance with an embodiment. The semiconductor structure shown in FIG. 6 differs from the semiconductor structure shown in FIG. 1 in that the first doping region 204 is formed in the fourth doping region 210. The edge 231 of the doped coding layer 207 is between the edge 233 of the adjacent fourth doped region 210 and the edge 235 of the dielectric structure 222. The fourth doping region 210 and the seventh doping region 216 have a first conductivity type. The substrate 202, the doped coding layer 207 (including the second doped region 206 and the third doped region 208), the first doped region 204, the fifth doped region 212 and the sixth doped region 214 have a second Conductive type. For example, the first conductivity type is N type, and the second conductivity type is P type. In one embodiment, the impurity concentration of the first doping region 204 and the impurity concentration of the third doping region 208 are respectively smaller than the impurity concentration of the second doping region 206. The semiconductor structure of an embodiment can have low leakage current.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

2, 102, 202‧‧‧ base

4, 104, 204‧‧‧ first doped area

5, 105‧‧‧ active area definition structure

6, 106, 206‧‧‧Second doped area

7, 107, 207‧‧‧ doped coding layer

8, 108, 208‧‧‧ three doped areas

10, 110, 210‧‧‧ fourth doping area

12, 112, 212‧‧‧ fifth doping area

14, 114, 214‧‧‧ sixth doping area

16, 116, 216‧‧‧ seventh doping area

18, 118‧‧‧ first part

20, 120‧‧‧ Part II

22, 122, 222‧‧‧ dielectric structure

24‧‧‧ gate structure

26, 28, 30‧‧‧ electrodes

Edges of 31, 33, 35, 37, 39, 131, 133, 135, 231, 233, 235 ‧

125‧‧‧gate dielectric layer

127‧‧‧ gate electrode layer

D1, D2‧‧‧ distance

1 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 2 is a graph showing the drain current-gate voltage (Id-Vg) curve for a semiconductor structure of a general semiconductor structure and an embodiment.

3 to 5 illustrate a method of fabricating a semiconductor structure in an embodiment.

Figure 6 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

2. . . Base

4. . . First doped region

5. . . Active area definition structure

6. . . Second doped region

7. . . Doped region

8. . . Three-doped region

10. . . Fourth doped region

12. . . Fifth doped region

14. . . Sixth doping zone

16. . . Seventh doping zone

18. . . first part

20. . . the second part

twenty two. . . Dielectric structure

twenty four. . . Gate structure

26, 28, 30. . . electrode

31, 33, 35, 37, 39. . . edge

D1, D2. . . distance

Claims (10)

A semiconductor structure includes: a first doped region; a second doped region; a third doped region, wherein the second doped region and the third doped region form a doped coding layer, and the The first doped region is formed to have a depth greater than a depth formed by the third doped region; a fourth doped region, wherein the doped coding layer is located in the first doped region and the fourth doped region And a dielectric structure on the first doped region, wherein an edge of the fourth doped region is adjacent to the second doped region, and an edge of the doped coding layer is adjacent to The edge of the fourth doped region is between an edge of the dielectric structure. The semiconductor structure of claim 1, wherein the second doped region is adjacent to the third doped region, the second doped region is between the third doped region and the first doped region The impurity concentration of the second doped region is greater than the impurity concentration of the third doped region. The semiconductor structure of claim 1, further comprising a gate structure on the first doped region and the doped coding layer. The semiconductor structure of claim 1, wherein the first doped region, the second doped region and the third doped region have the same conductivity type. The semiconductor structure of claim 4, wherein the impurity concentration of the first doped region and the impurity concentration of the third doped region are different from the impurity concentration of the second doped region, respectively. The semiconductor structure of claim 5, wherein an impurity concentration of the first doped region and an impurity concentration of the third doped region are respectively smaller than an impurity concentration of the second doped region. A method of fabricating a semiconductor structure, comprising: forming a first doped region; forming a second doped region; forming a third doped region, wherein the second doped region and the third doped region form an admixture a first coded layer, wherein the first doped region forms a depth greater than a depth formed by the third doped region; forming a fourth doped region, wherein the doped code layer is located in the first doped region And forming a dielectric structure on the first doped region, wherein an edge of the fourth doped region is adjacent to the second doped region, and one of the doped coding layers The edge is between the edge of the adjacent fourth doped region and an edge of the dielectric structure. The method of fabricating a semiconductor structure according to claim 7, wherein the first doped region, the second doped region and the third doped region have the same conductivity type. The method of fabricating a semiconductor structure according to claim 8, wherein an impurity concentration of the first doped region and an impurity concentration of the third doped region are respectively smaller than an impurity concentration of the second doped region. A semiconductor structure operating method, the semiconductor structure comprising: a first doped region; a second doped region; a third doped region, wherein the second doped region and the third doped region Forming a doped coding layer, and the first doped region is formed to have a depth greater than a depth formed by the third doped region; a fourth doped region, wherein the doped coding layer is located in the first doped region And a fourth dielectric region, a dielectric structure is disposed on the first doped region, wherein an edge of the fourth doped region is adjacent to the second doped region, and one of the doped coding layers An edge is between the edge of the adjacent fourth doped region and an edge of the dielectric structure; and a gate structure is disposed on the doped coding layer and the first doped region, wherein the edge is The method includes: a bias between a first electrode electrically connected to the first doped region and a second electrode electrically connected to the third doped region; and a modulation electrical connection to A voltage of a third electrode of the gate structure to control the turn-on current of the semiconductor structure or to turn off the semiconductor structure.