TWI506684B - Electronic components and manufacturing method thereof - Google Patents

Electronic components and manufacturing method thereof Download PDF

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TWI506684B
TWI506684B TW100121324A TW100121324A TWI506684B TW I506684 B TWI506684 B TW I506684B TW 100121324 A TW100121324 A TW 100121324A TW 100121324 A TW100121324 A TW 100121324A TW I506684 B TWI506684 B TW I506684B
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electrical property
sintering
layer
suppression layer
electronic component
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TW201301369A (en
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Wen His Lee
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Univ Nat Cheng Kung
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Description

電子元件及其製造方法Electronic component and method of manufacturing same

本案係關於一種電子元件及其製作方法。尤其,本案係以抑制層與元件層一起燒結來抑制元件層燒結的收縮,並考慮抑制層對於整體電性影響的電子元件。This case relates to an electronic component and a method of fabricating the same. In particular, the present invention suppresses the shrinkage of the sintering of the element layer by sintering the suppression layer together with the element layer, and considers an electronic component that suppresses the influence of the layer on the overall electrical properties.

在資訊與無線通訊結合的市場趨勢,以及現代人對於電子產品的多功能與攜帶便利性等要求下,各種電子產品中的電子元件也隨之趨向更加輕薄短小。以其中的被動元件來看,積層陶瓷元件的應用範圍相當廣泛。然而,若要達到輕薄短小且同時要維持良好的電性,除了從原材料的性質進行改善外,更可由製程方向著手,達到更好的電子元件特性。With the market trend of combining information and wireless communication, as well as the modern people's versatility and portability of electronic products, the electronic components in various electronic products tend to be lighter, thinner and shorter. In terms of passive components, the application range of laminated ceramic components is quite extensive. However, in order to achieve thinness and shortness while maintaining good electrical properties, in addition to improving the properties of the raw materials, it is also possible to proceed from the process direction to achieve better electronic component characteristics.

現今的積層陶瓷元件1如第一圖所示,其製作方法係將積層陶瓷層11經由燒結製程後,再於積層陶瓷層11的兩端提供端電極12,以使積層陶瓷元件1可與外接電路(圖式未示出)連接。然而,在端電極12的浸鍍(dipping)製程等各種製程下,端電極的電極深度d121 控制不易,因此電極深度d121 的大小很容易產生不小的差距。由於各種電子元件的特性都與電極間的距離有極大的關係,(例如:電阻器的電阻值與電極間距離呈正比,平板電容器的電容值與電極間距離呈反比),因此如果整批電子元件的電極深度d121 之差異越大,即代表其端電極間距離的電極距離d122 差異越大,而會嚴重影響到整批電子元件的良率。The current laminated ceramic component 1 is as shown in the first figure, and the manufacturing method is to provide the terminal electrode 12 to both ends of the laminated ceramic layer 11 after the laminated ceramic layer 11 is passed through the sintering process, so that the laminated ceramic component 1 can be externally connected. The circuit (not shown) is connected. However, under various processes such as a dipping process of the terminal electrode 12, the electrode depth d 121 of the terminal electrode is not easily controlled, and thus the electrode depth d 121 is likely to cause a large difference. Since the characteristics of various electronic components are greatly related to the distance between the electrodes (for example, the resistance value of the resistor is proportional to the distance between the electrodes, and the capacitance value of the panel capacitor is inversely proportional to the distance between the electrodes), so if the entire batch of electrons The greater the difference in electrode depth d 121 of the element, that is, the greater the difference in electrode distance d 122 representing the distance between the end electrodes, which seriously affects the yield of the entire batch of electronic components.

再者,積層陶瓷元件的燒結方法如第二圖所示,積層陶瓷生坯21會放在承載陶瓷基板24上進行燒結。然而,在高 溫燒結的過程中,由於積層陶瓷生坯21與承載陶瓷基板24之間會有一些反應的發生,而嚴重影響電子元件整體的特性。此外,積層陶瓷生坯21在進行燒結時,由於陶瓷燒結本身的緻密化過程,必然會有收縮現象的產生,因此燒結完成的積層陶瓷層11將因內部收縮等因素,而增添電子元件整體特性的不穩定性。Further, as shown in the second figure, the laminated ceramic green body 21 is placed on the carrier ceramic substrate 24 for sintering. However, at high During the temperature sintering process, some reactions occur between the laminated ceramic green body 21 and the bearing ceramic substrate 24, which seriously affects the overall characteristics of the electronic component. In addition, when the laminated ceramic green body 21 is sintered, the shrinkage phenomenon is inevitably caused by the densification process of the ceramic sintering itself, so that the sintered laminated ceramic layer 11 will increase the overall characteristics of the electronic component due to internal shrinkage and the like. Instability.

本案申請人鑑於習知技術中的不足,經過悉心試驗與研究,並一本鍥而不捨之精神,終構思出本案「電子元件及其製造方法」,以結合抑制層來抑制燒結收縮之方法,並透過抑制層的選擇,使電極深度的差異對於整體電性的差異降到最低。如此一來,整批電子元件的電性差異可降至最低,以進一步提升整體的良率。In view of the deficiencies in the prior art, the applicant of this case, after careful experimentation and research, and a perseverance spirit, finally conceived the "electronic components and their manufacturing methods" in this case, combined with the suppression layer to suppress the sintering shrinkage method, and through The choice of suppression layer minimizes the difference in electrode depth for the overall electrical difference. As a result, the electrical differences of the entire batch of electronic components can be minimized to further improve the overall yield.

為了增進積層陶瓷元件的良率,本發明透過選擇具有一特殊相對電性的材料來作為抑制元件層收縮的抑制層。藉由抑制層材料與元件層材料本身電性的相對關係的選擇,而使端電極的深度對於整體電性的影響能降至最低。In order to enhance the yield of the laminated ceramic component, the present invention serves as a suppressing layer for suppressing shrinkage of the element layer by selecting a material having a specific relative electrical property. The effect of the depth of the terminal electrode on the overall electrical properties can be minimized by suppressing the choice of the electrical relative relationship between the layer material and the component layer material itself.

為了達到上述目的,本發明提出一種具有一特定電性的電子元件,其包括:一燒結元件層,其具有一第一電性;以及一燒結抑制層,其具有一第二電性,且與該燒結元件層形成一並聯狀態,其中該第二電性的大小須使該電子元件在該並聯狀態下,該特定電性係由該第一電性主導。In order to achieve the above object, the present invention provides an electronic component having a specific electrical property, comprising: a sintered component layer having a first electrical property; and a sintering inhibiting layer having a second electrical property and The sintered element layer forms a parallel state, wherein the second electrical property is sized such that the electronic component is in the parallel state, the specific electrical system being dominated by the first electrical property.

為了達到上述目的,本發明另提出一種具有一特定電性的電子元件,其包括:一元件層,其具有一第一電性以及一第一燒結收縮量;以及一抑制層,其具有一第二電性以及一 第二燒結收縮量,並位於該元件層上,其中若該電子元件為一電阻器以及一電感器其中之一,該第一電性小於該第二電性,以及若該電子元件為一電容器,該第一電性大於該第二電性。In order to achieve the above object, the present invention further provides an electronic component having a specific electrical property, comprising: a component layer having a first electrical property and a first sintering shrinkage amount; and a suppression layer having a first Two electrical and one a second amount of sintering shrinkage and located on the component layer, wherein if the electronic component is one of a resistor and an inductor, the first electrical property is less than the second electrical property, and if the electronic component is a capacitor The first electrical property is greater than the second electrical property.

為了達到上述目的,本發明再提出一種具有一特定電性的電子元件,其包括:一燒結元件層,其具有一第一電性;以及一燒結抑制層,其具有一第二電性,且與該燒結元件層形成一並聯狀態,其中該第二電性的大小須使該電子元件在該並聯狀態下,該特定電性係由該第一電性主導。In order to achieve the above object, the present invention further provides an electronic component having a specific electrical property, comprising: a sintered component layer having a first electrical property; and a sintering inhibiting layer having a second electrical property, and Forming a parallel state with the sintered element layer, wherein the second electrical property is sized such that the electronic component is in the parallel state, and the specific electrical system is dominated by the first electrical property.

為了達到上述目的,本發明還提出了一種具有一元件電性的電子元件,其包括:一燒結元件層,其具有一第一電性;以及一燒結抑制層,具有一第二電性,且該第二電性之大小致使該元件電性由該第一電性主導。In order to achieve the above object, the present invention also provides an electronic component having an elemental electrical property, comprising: a sintered component layer having a first electrical property; and a sintering inhibiting layer having a second electrical property, and The magnitude of the second electrical property causes the electrical properties of the component to be dominated by the first electrical property.

本案所提出之「電子元件及其製造方法」將可由以下的實施例說明而得到充分瞭解,使得熟習本技藝之人士可以據以完成之,然而本案之實施並非可由下列實施例而被限制其實施型態,熟習本技藝之人士仍可依據除既揭露之實施例的精神推演出其他實施例,該等實施例皆當屬於本發明之範圍。The "electronic component and its manufacturing method" as set forth in the present disclosure will be fully understood by the following examples, so that those skilled in the art can do so. However, the implementation of the present invention is not limited by the following embodiments. Other embodiments may be derived from the spirit of the embodiments disclosed herein, and such embodiments are within the scope of the invention.

請參閱第三圖(a),其係為本發明的電子元件3的示意圖。其中為了能充分了解電子元件3的整體結構,第三圖(a)對於電子元件3進行了部份的解剖。電子元件3包括元件層31、端電極32、第一抑制層331以及第二抑制層332,而整體的電子元件3具有一特定電性,元件層31具有一第一電性,第二抑制層332具有一第二電性,左側端電極深度為電 極深度d321 ,左右兩個端電極之間的距離為電極距離d322 。雖然右側端電極深度可能與左側端電極深度有所不同,但是左右兩側的端電極深度都會對電極間的距離造成影響,進而影響整體電子元件3的特定電性,然而左右兩側的電極深度的影響方式並無不同,因此僅以左側端電極深度作為代表進行說明。同樣地,雖然第一抑制層331的電性與第二抑制層332的電性可以互不相同,但是兩者對於整體電性的影響方式並無差異,因此僅以第二抑制層的第二電性作為代表進行說明。另外,為了方便了解端電極32於電子元件3上的位置,端電極32的厚度以較為誇大的方式表現,實際上端電極32可透過薄膜的方式,鍍置在電子元件3的兩端。Please refer to the third figure (a), which is a schematic diagram of the electronic component 3 of the present invention. In order to fully understand the overall structure of the electronic component 3, the third figure (a) partially dissects the electronic component 3. The electronic component 3 includes an element layer 31, a terminal electrode 32, a first suppression layer 331 and a second suppression layer 332, and the overall electronic component 3 has a specific electrical property, and the component layer 31 has a first electrical property, and the second suppression layer 332 has a second electrical property, the left end electrode depth is the electrode depth d 321 , and the distance between the left and right end electrodes is the electrode distance d 322 . Although the depth of the right end electrode may be different from the depth of the left end electrode, the depth of the end electrode on the left and right sides may affect the distance between the electrodes, thereby affecting the specific electrical properties of the overall electronic component 3, but the electrode depths on the left and right sides. The effect of the difference is not different, so only the left end electrode depth is used as a representative. Similarly, although the electrical properties of the first suppression layer 331 and the electrical properties of the second suppression layer 332 may be different from each other, there is no difference in the manner in which the two are affected by the overall electrical properties, and therefore only the second of the second suppression layer Electricality is explained as a representative. In addition, in order to facilitate the understanding of the position of the terminal electrode 32 on the electronic component 3, the thickness of the terminal electrode 32 is expressed in a more exaggerated manner. In fact, the terminal electrode 32 is plated on both ends of the electronic component 3 in a transparent manner.

由於端電極32係用以與外接電路進行電性連接,因此端電極32可位於元件層31、第一抑制層331以及第二抑制層332的共同側表面,且端電極32同時與元件層31、第一抑制層331以及第二抑制層332進行電性連接,因此本發明電子元件3的各個元件間的電性關係如第三圖(b)所示,其中第三圖(b)之各個元件符號所代表的元件皆對應第三圖(a)的各個元件符號所代表的元件,並且元件層31、第一抑制層331以及第二抑制層332係以並聯的方式進行電性連接,而形成電子元件3整體的特定電性。Since the terminal electrode 32 is electrically connected to the external circuit, the terminal electrode 32 can be located on the common side surface of the element layer 31, the first suppression layer 331 and the second suppression layer 332, and the terminal electrode 32 simultaneously with the element layer 31. The first suppression layer 331 and the second suppression layer 332 are electrically connected. Therefore, the electrical relationship between the respective elements of the electronic component 3 of the present invention is as shown in the third diagram (b), wherein each of the third diagram (b) The components represented by the component symbols correspond to the components represented by the respective component symbols of the third diagram (a), and the component layer 31, the first suppression layer 331 and the second suppression layer 332 are electrically connected in parallel. The specific electrical properties of the entire electronic component 3 are formed.

請合併參閱第三圖(a)以及第三圖(b)。由於第二抑制層332係形成於元件層31上,而端電極32係以電子元件3的整體進行如浸鍍製程等製程方法所產生,因此端電極32係以外圍包覆的方式,將第一抑制層331、第二抑制層332與元件層31的兩端包覆於其中。故,由於元件層31僅有其兩端與端電極32接觸,所以電極深度d321 並不影響元件層31的 電性表現,但由於第一抑制層331以及第二抑制層332除了兩端與端電極32接觸外,其分別有部份下表面或上表面亦被端電極32所覆蓋,因此電極深度d321 會對於抑制層的電性表現產生影響。Please refer to the third figure (a) and the third figure (b). Since the second suppression layer 332 is formed on the element layer 31, and the terminal electrode 32 is formed by the entire method of the electronic component 3, such as a immersion process, the terminal electrode 32 is covered by the periphery. A suppression layer 331, a second suppression layer 332, and both ends of the element layer 31 are covered therein. Therefore, since only the two ends of the element layer 31 are in contact with the terminal electrode 32, the electrode depth d 321 does not affect the electrical performance of the element layer 31, but since the first suppression layer 331 and the second suppression layer 332 are The terminal electrode 32 is in contact with each other, and a part of the lower surface or the upper surface thereof is also covered by the terminal electrode 32, so that the electrode depth d 321 has an influence on the electrical performance of the suppression layer.

在先前技術中,由於元件層本身的上下表面皆受端電極覆蓋,而使直接代表整體電性的元件層電性無法擺脫電極深度d121 的影響。因此,本發明的電子元件3將電極深度d321 的影響轉移到第一以及第二抑制層331,332上,並針對第一以及第二抑制層331,332的電性值大小進行材料的選擇,使整體電子元件的特定電性不受第一以及第二抑制層331,332影響,而由元件層31所主導。故,特定電性可忽略電極深度d321 的影響,僅需考慮元件層31的電性控制即可。In the prior art, since the upper and lower surfaces of the element layer itself are covered by the terminal electrodes, the element layer electrical properties directly representing the overall electrical properties cannot be removed from the electrode depth d 121 . Therefore, the electronic component 3 of the present invention transfers the influence of the electrode depth d 321 to the first and second suppression layers 331, 332, and selects the material for the electrical value of the first and second suppression layers 331, 332 to make the overall electron The specific electrical properties of the component are unaffected by the first and second suppression layers 331, 332 and are dominated by the component layer 31. Therefore, the specific electrical properties can neglect the influence of the electrode depth d 321 , and only the electrical control of the component layer 31 needs to be considered.

在一實施例中,電子元件3係為一積層陶瓷元件,而該積層陶瓷元件係用以作為一電阻器,因此特定電性、第一電性以及第二電性分別為特定電阻值、第一電阻值以及第二電阻值。由於並聯狀態下特定電阻值的倒數等於第一電阻值以及第二電阻值的倒數相加,因此第二電阻值應大於第一電阻值,以使第一電阻值來主導特定電阻值的大小。較佳地,第二電阻值遠大於第一電阻值,使第二電阻值可直接忽略。In one embodiment, the electronic component 3 is a laminated ceramic component, and the laminated ceramic component is used as a resistor, so that the specific electrical property, the first electrical property, and the second electrical property are specific resistance values, respectively. A resistance value and a second resistance value. Since the reciprocal of the specific resistance value in the parallel state is equal to the first resistance value and the reciprocal addition of the second resistance value, the second resistance value should be greater than the first resistance value such that the first resistance value dominates the magnitude of the specific resistance value. Preferably, the second resistance value is much larger than the first resistance value, so that the second resistance value can be directly ignored.

在一實施例中,該積層陶瓷元件係用以作為一電容器,因此特定電性、第一電性以及第二電性分別為特定電容值、第一電容值以及第二電容值。由於並聯狀態下的特定電容值等於第一電容值以及第二電容值的相加,因此第二電容值應小於第一電容值,以使第一電容值來主導特定電容值的大小。較佳地,第二電容值遠小於第一電容值,使第二電容值可直接忽略。In one embodiment, the laminated ceramic component is used as a capacitor, and thus the specific electrical property, the first electrical property, and the second electrical property are a specific capacitance value, a first capacitance value, and a second capacitance value, respectively. Since the specific capacitance value in the parallel state is equal to the addition of the first capacitance value and the second capacitance value, the second capacitance value should be smaller than the first capacitance value such that the first capacitance value dominates the magnitude of the specific capacitance value. Preferably, the second capacitance value is much smaller than the first capacitance value, so that the second capacitance value can be directly ignored.

在一實施例中,該積層陶瓷元件係用以作為一電感器,因此特定電性、第一電性以及第二電性分別為特定電感值、第一電感值以及第二電感值。由於並聯狀態的電感值公式係與並聯狀態的電阻值公式相對應,因此第一電感值與第二電感值的關係係與第一電阻值與第二電阻值的關係相同。In one embodiment, the laminated ceramic component is used as an inductor, and thus the specific electrical property, the first electrical property, and the second electrical property are respectively a specific inductance value, a first inductance value, and a second inductance value. Since the inductance value formula of the parallel state corresponds to the resistance value formula of the parallel state, the relationship between the first inductance value and the second inductance value is the same as the relationship between the first resistance value and the second resistance value.

由於第一以及第二抑制層331,332的電性選擇已使其電性可被忽略,導致電子元件3的特定電性由元件層31的第一電性所主導,而使會受電極深度d321 的影響的第一以及第二抑制層331,332與特定電性的大小無關。Since the electrical selection of the first and second suppression layers 331, 332 has made their electrical properties negligible, the specific electrical properties of the electronic component 3 are dominated by the first electrical property of the component layer 31, and the electrode depth d 321 is affected. The first and second suppression layers 331, 332 of the influence are independent of the magnitude of the specific electrical properties.

在上述實施例中,該電子元件3亦可僅有一抑制層331,以抑制元件層31燒結時的收縮量,並同時減少電極深度d321 對於電子元件特性的影響量。In the above embodiment, the electronic component 3 may have only one suppression layer 331 to suppress the amount of shrinkage when the element layer 31 is sintered, and at the same time reduce the influence of the electrode depth d 321 on the characteristics of the electronic component.

請參閱第四圖,其係為本發明的電子元件生坯4在燒結製程下的示意圖。其中電子元件生坯4具有元件層生坯41、第一抑制層生坯431以及第二抑制層生坯432,第一抑制層生坯431以及第二抑制層生坯432的中間夾有元件層生坯41,而電子元件生坯4以第一抑制層生坯431與承載基板44進行接觸,並透過承載基板44置入一加熱爐(圖式未示出),以一燒結溫度進行一燒結製程。Please refer to the fourth figure, which is a schematic diagram of the electronic component green body 4 of the present invention under the sintering process. The electronic component green body 4 has the element layer green body 41, the first suppression layer green body 431, and the second suppression layer green body 432, and the element layer is sandwiched between the first suppression layer green body 431 and the second suppression layer green body 432. The green body 41 and the electronic component green body 4 are brought into contact with the carrier substrate 44 by the first suppression layer green body 431, and placed in a heating furnace (not shown) through the carrier substrate 44 to be sintered at a sintering temperature. Process.

經燒結後,元件層生坯41即形成第三圖(a)中的元件層31,而第一抑制層生坯431以及第二抑制層生坯431分別形成第三圖(a)中的第一抑制層331以及第二抑制層332。而元件層31與第一以及第二抑制層331,332係透過燒結製程的方式所形成,因此其亦可分別稱為燒結元件層以及燒結抑制層。After sintering, the element layer green body 41 forms the element layer 31 in the third figure (a), and the first suppression layer green body 431 and the second suppression layer green body 431 form the third layer (a), respectively. A suppression layer 331 and a second suppression layer 332. The element layer 31 and the first and second suppression layers 331, 332 are formed by a sintering process, and therefore may be referred to as a sintered element layer and a sintering suppression layer, respectively.

元件層生坯41在該燒結溫度下形成的元件層31會有一第一收縮量,第二抑制層生坯432在該燒結溫度下形成的第 二抑制層332會有一第二收縮量(第一抑制層生坯431經燒結後亦有一收縮量,其與第二收縮量效果相同,因此僅以第二抑制層生坯432以及第二收縮量作為代表來說明)。The element layer 31 formed at the sintering temperature of the element layer green body 41 has a first contraction amount, and the second suppression layer green body 432 is formed at the sintering temperature. The second suppression layer 332 has a second shrinkage amount (the first suppression layer green body 431 also has a shrinkage amount after sintering, which has the same effect as the second shrinkage amount, so only the second suppression layer green body 432 and the second shrinkage amount As a representative to explain).

在一實施例中,元件層生坯41中更包含陶瓷生坯以及電極生坯。由於陶瓷生坯與電極生坯在燒結後各自的收縮率有所差異,因此燒結後位於元件層中所產生的陶瓷層以及電極層將因收縮率的不同,而使得電極層出現電極不連續的現象。為了抑制陶瓷層的收縮率,而使陶瓷層與電極層之間的收縮率差異降低,第二抑制層生坯432的第二收縮率應小於元件層生坯41的第一收縮率,使得第二收縮量小於第一收縮量,進而導致元件層生坯41中與第二抑制層生坯432接觸的部份,會受到第二抑制層生坯的收縮抑制,而降低其在接觸表面上的收縮量。同樣地,相對較為外側的元件層生坯41受到的抑制效果亦會向內傳遞到內側的元件層生坯41,而導致整體的抑制效果。In an embodiment, the component layer green body 41 further comprises a ceramic green body and an electrode green body. Since the ceramic green body and the electrode green body have different shrinkage rates after sintering, the ceramic layer and the electrode layer which are generated in the element layer after sintering will be discontinuous due to the difference in shrinkage rate of the electrode layer. phenomenon. In order to suppress the shrinkage ratio of the ceramic layer, the difference in shrinkage between the ceramic layer and the electrode layer is lowered, and the second shrinkage ratio of the second suppression layer green body 432 is smaller than the first shrinkage ratio of the element layer green body 41, so that The amount of shrinkage is less than the first amount of shrinkage, which in turn causes the portion of the component layer green body 41 that is in contact with the second suppression layer green body 432 to be inhibited by the shrinkage of the second suppression layer green body, thereby reducing its contact on the contact surface. The amount of shrinkage. Similarly, the suppression effect of the relatively outer element layer green body 41 is also transmitted inward to the inner element layer green body 41, resulting in an overall suppressing effect.

在一實施例中,由於第二收縮量小於第一收縮量,因此元件層生坯41在收縮的過程中,與第二抑制層生坯432接觸的平面皆會受到一收縮抑制力。由於整個平面都受到抑制力抑制的效果,因此整個平面的微結構分佈會較為均勻。此外,由於元件層生坯41的內側亦受到收縮抑制力的影響,進而使元件層31整體的微結構分佈較為均勻。因為陶瓷顆粒本身的電性質會受到其顆粒的大小的影響而產生變化,所以均勻的微結構分佈亦可使整體元件層31的電性質較為固定,而使整批的電子元件的電性質較為相近,而有較高的良率。In an embodiment, since the second contraction amount is smaller than the first contraction amount, the plane of the element layer green body 41 in contact with the second suppression layer green body 432 during contraction is subjected to a contraction suppressing force. Since the entire plane is suppressed by the suppression force, the microstructure distribution of the entire plane is relatively uniform. Further, since the inner side of the element layer green body 41 is also affected by the shrinkage suppressing force, the microstructure distribution of the entire element layer 31 is made uniform. Since the electrical properties of the ceramic particles themselves are affected by the size of the particles, the uniform microstructure distribution can also make the electrical properties of the integral component layer 31 relatively fixed, and the electrical properties of the entire batch of electronic components are relatively similar. And have a higher yield.

在一實施例中,元件層31具有一第一開始燒結溫度,第二抑制層332具有一第二開始燒結溫度。該第一開始燒結溫 度可小於該第二開始燒結溫度,使得元件層生坯41在第二抑制層生坯尚未進行收縮時,先進行燒結收縮。如此一來,由於第二抑制層生坯尚未有收縮的產生,而更能抵抗元件層生坯41的收縮現象,進而加強抑制收縮的效果。In one embodiment, element layer 31 has a first onset sintering temperature and second suppression layer 332 has a second onset sintering temperature. The first starting sintering temperature The degree may be less than the second starting sintering temperature, so that the element layer green body 41 is first subjected to sintering shrinkage when the second suppression layer green body has not been shrunk. As a result, since the second suppression layer green body has not yet produced shrinkage, it is more resistant to the shrinkage phenomenon of the element layer green body 41, thereby enhancing the effect of suppressing shrinkage.

在一實施例中,第一抑制層生坯431的材料亦可選用與承載基板44較不易反應的材料,以使元件層生坯41在燒結過程中,可透過第一抑制層生坯431的阻隔,而避免與承載基板44產生反應。就算仍有部分的第一抑制層生坯431與承載基板44產生反應,由於電子元件3的特定電性係由元件層31的第一電性所主導,因此該反應的存在並不會對特定電性產生影響。In an embodiment, the material of the first suppression layer green body 431 may also be a material that is less reactive with the carrier substrate 44, so that the element layer green body 41 can pass through the first suppression layer green body 431 during the sintering process. The barrier is avoided to avoid reaction with the carrier substrate 44. Even if a portion of the first suppression layer green body 431 reacts with the carrier substrate 44, since the specific electrical property of the electronic component 3 is dominated by the first electrical property of the component layer 31, the existence of the reaction does not Electrical effects.

請參閱第五圖,其係為本發明電子元件的製作流程,其步驟包括:(S51)形成具有第一電性的燒結元件層;(S52)於燒結元件層上形成具有第二電性的燒結抑制層;(S53)升溫至一燒結溫度進行燒結;以及(S54)於燒結元件層與燒結抑制層兩者同一側表面形成端電極。Referring to FIG. 5, which is a manufacturing process of the electronic component of the present invention, the steps include: (S51) forming a sintered component layer having a first electrical property; (S52) forming a second electrical property on the sintered component layer. a sintering suppression layer; (S53) heating to a sintering temperature for sintering; and (S54) forming a terminal electrode on the same side surface of both the sintered device layer and the sintering suppression layer.

在步驟S51中,先形成一未燒結的燒結元件層,亦即第四圖所示的元件層生坯41。該未燒結的燒結元件層具有一第一電性以及一第一收縮率。In step S51, an unsintered sintered element layer, that is, the element layer green body 41 shown in Fig. 4 is formed first. The unsintered sintered component layer has a first electrical property and a first shrinkage.

在步驟S52中,於未燒結的燒結元件層上形成一未燒結的燒結抑制層,亦即第四圖所示的抑制層生坯431及/或432。該未燒結的燒結抑制層具有一第二電性以及一第二收縮率。其中該燒結抑制層的材料選擇,需使第二電性對於整體電子元件的元件電性的影響相對較小,而由第一電性來主導元件電性。例如:若電子元件是一電阻器或電感器時,第一電性應小於第二電性;若電子元件是一電容器時,第二電性 應小於第一電性。In step S52, an unsintered sintering suppression layer, that is, the suppression layer green bodies 431 and/or 432 shown in Fig. 4, is formed on the unsintered sintered element layer. The unsintered sintering suppression layer has a second electrical property and a second shrinkage. Wherein the material selection of the sintering suppression layer is such that the influence of the second electrical property on the electrical properties of the components of the overall electronic component is relatively small, and the electrical property of the component is dominated by the first electrical property. For example, if the electronic component is a resistor or an inductor, the first electrical property should be less than the second electrical property; if the electronic component is a capacitor, the second electrical property Should be less than the first electrical property.

在步驟S53中,由於燒結的過程中,燒結元件層以及燒結抑制層會因其各自的燒結收縮率的影響,而在該燒結溫度下分別產生一第一燒結收縮量以及第二燒結收縮量,因此應控制第二燒結收縮量小於第一燒結收縮量,藉此使燒結抑制層在該燒結溫度下可抑制燒結元件層的收縮現象。此外,該燒結溫度應大於燒結元件層的第一開始燒結溫度,以確保燒結元件層已產生燒結收縮的現象。In the step S53, the sintering element layer and the sintering suppression layer may have a first sintering shrinkage amount and a second sintering shrinkage amount respectively at the sintering temperature due to the influence of the respective sintering shrinkage rates during the sintering process. Therefore, the second sintering shrinkage amount should be controlled to be smaller than the first sintering shrinkage amount, whereby the sintering suppression layer can suppress the shrinkage phenomenon of the sintered component layer at the sintering temperature. Further, the sintering temperature should be greater than the first on-sintering temperature of the sintered component layer to ensure that the sintered component layer has undergone sintering shrinkage.

由於只要燒結抑制層的第二收縮量小於燒結元件層的第一收縮量,燒結抑制層本身亦可沒有進行燒結收縮(亦即第二收縮量為零),因此,在一實施例中,該燒結溫度可大於燒結抑制層的第二開始燒結溫度;在另一實施例中,該燒結溫度亦可小於第二開始燒結溫度。在又一實施例中,該第二開始燒結溫度應大於該第一開始燒結溫度,以提高燒結抑制層對於燒結元件層的收縮抑制之效果。Since the sintering shrinkage layer itself may not undergo sintering shrinkage (that is, the second shrinkage amount is zero) as long as the second shrinkage amount of the sintering suppression layer is smaller than the first shrinkage amount of the sintered component layer, therefore, in an embodiment, The sintering temperature may be greater than the second initial sintering temperature of the sintering suppression layer; in another embodiment, the sintering temperature may also be less than the second starting sintering temperature. In still another embodiment, the second starting sintering temperature should be greater than the first starting sintering temperature to increase the effect of the sintering suppression layer on the shrinkage suppression of the sintered component layer.

在本發明之一實施例中,抑制層的材料選擇可依未燒結前的狀態進行選擇,亦即可依抑制層生坯與元件層生坯的電性關係進行選擇。在另一實施例中,抑制層的材料選擇可依燒結後的狀態進行選擇,亦即可依抑制層與元件層的電性關係進行選擇。在又一實施例中,由於未燒結的抑制層生坯以及元件層生坯於電性上的相對關係與燒結後的抑制層以及元件層於電性上的相對關係並無變化,因此可依未燒結的抑制層生坯特性或以燒結後的抑制層特性進行材料的選擇。In an embodiment of the present invention, the material selection of the suppression layer may be selected according to the state before the sintering, or may be selected according to the electrical relationship between the green layer of the suppression layer and the green body of the element layer. In another embodiment, the material selection of the suppression layer may be selected according to the state after sintering, or may be selected according to the electrical relationship between the suppression layer and the element layer. In still another embodiment, since the relative relationship between the unsintered suppression layer green body and the element layer green body and the electrical relationship between the sintered suppression layer and the element layer does not change, The raw material of the unsintered suppression layer or the material of the suppression layer after sintering is selected.

請參閱第六圖,其係以電阻為例,比較有無抑制層的狀況下,不同的電極深度對於電阻值之影響。圖中的曲線61係代表不具有抑制層的電阻器在不同電極深度下的電阻值, 而圖中的曲線62係代表本發明中具有抑制層的電阻器在不同電極深度下的電阻值。由圖可明顯看出,曲線62在不同的電極深度下,並未有太大的電阻變化,而曲線61會隨著電極深度的增加,而明顯有下降的現象。由此可知,不具有抑制層的電阻器由於電極深度的增加,使得其電極間的距離減少,而降低了本身的電阻值;相對地,具有抑制層的電阻器將電極間距離對電阻值的影響力轉移到抑制層上,並且因抑制層的電阻值大於元件層的電阻值,使得在抑制層與元件層並聯的狀態下,電極間距離對整體電阻值的影響力明顯受到抑制層對整體電阻值影響不大的緣故,使得曲線61不因電極深度的增加而有劇烈的改變。Please refer to the sixth figure, which takes the resistance as an example to compare the influence of different electrode depths on the resistance value in the presence or absence of the suppression layer. The curve 61 in the figure represents the resistance value of the resistor having no suppression layer at different electrode depths, Curve 62 in the figure represents the resistance value of the resistor having the suppression layer at different electrode depths in the present invention. It can be clearly seen from the figure that the curve 62 does not have much resistance change at different electrode depths, and the curve 61 will obviously decrease as the electrode depth increases. It can be seen that the resistor without the suppression layer reduces the distance between the electrodes due to the increase of the electrode depth, and reduces the resistance value of the electrode; in contrast, the resistor with the suppression layer has the distance between the electrodes and the resistance value. The influence is transferred to the suppression layer, and since the resistance value of the suppression layer is larger than the resistance value of the element layer, the influence of the distance between the electrodes on the overall resistance value is significantly affected by the suppression layer to the whole in the state in which the suppression layer is in parallel with the element layer. The resistance value has little effect, so that the curve 61 does not change drastically due to the increase in electrode depth.

再者,由於電極深度控制不易,因此就算電極深度設定為500μm,每一個製造出來的電阻器的電極深度仍會有一定的差異。以電極深度500μm為例,曲線61中的電阻值明顯有劇烈的變化,而曲線62的電阻值相對穩定。由此可知,由於電極深度控制不易,不具抑制層的每一個電阻器之間的電極深度之差異將直接表現在其電阻值上,再者,由於沒有抑制層的存在,元件層內部的顆粒尺寸相對較為不均勻,而使得元件層的電性也會有異常變化;相對地,具有抑制層的每一個電阻器之間的電極深度差異會透過抑制層來反應在電阻值上,而抑制層的電阻值較大,使電極深度的影響力在並聯狀態下相對較不明顯,再者,抑制層的存在也造成元件層內部顆粒尺寸較為均勻,而使得元件層的電性較不會有差異。Furthermore, since the electrode depth control is not easy, even if the electrode depth is set to 500 μm, the electrode depth of each of the manufactured resistors will have a certain difference. Taking the electrode depth of 500 μm as an example, the resistance value in the curve 61 is significantly changed sharply, and the resistance value of the curve 62 is relatively stable. It can be seen that since the electrode depth control is not easy, the difference in electrode depth between each resistor without the suppression layer will be directly expressed in the resistance value, and further, the particle size inside the element layer due to the absence of the suppression layer. Relatively non-uniform, the electrical properties of the element layer will also change abnormally; in contrast, the difference in electrode depth between each resistor having a suppression layer will be reflected in the resistance value through the suppression layer, while the suppression layer The resistance value is large, so that the influence of the electrode depth is relatively inconspicuous in the parallel state. Furthermore, the presence of the suppression layer also causes the particle size inside the element layer to be relatively uniform, so that the electrical properties of the element layer are not different.

請參閱下頁表一,其係以電阻為例,比較有無抑制層的狀況下電阻值的差異。表中的實驗數據係由5000顆電阻器隨機抽樣20顆電阻器於室溫25℃下所量測出來的電阻值。其 中電阻1係代表不具有抑制層的電阻器,而電阻二係代表具有抑制層的電阻器。Please refer to Table 1 on the next page. Take the resistance as an example to compare the difference in resistance between the presence or absence of the suppression layer. The experimental data in the table is a resistance value measured by randomly sampling 20 resistors of 5,000 resistors at room temperature of 25 °C. its The medium resistance 1 represents a resistor having no suppression layer, and the resistance second represents a resistor having a suppression layer.

由上表來看,電阻1的極大值(11280Ω)大於電阻2的極大值(11110Ω),而電阻1的極小值(9800Ω)小於電阻2的極小值(10460Ω)。由此可知,不具有抑制層的電阻1其電阻值的變化明顯較具有抑制層的電阻2大。請參閱第七圖,其係以表一的數據所繪製而成,用以表示電阻值的分布範圍。由圖可明顯看出,具有抑制層的電阻2其電阻值分布範圍較窄,相對於不具有抑制層的電阻1有較高的良率。From the above table, the maximum value of the resistor 1 (11280 Ω) is larger than the maximum value of the resistor 2 (11110 Ω), and the minimum value of the resistor 1 (9800 Ω) is smaller than the minimum value of the resistor 2 (10460 Ω). From this, it is understood that the resistance 1 of the resistor 1 having no suppression layer is significantly larger than the resistance 2 having the suppression layer. Please refer to the seventh figure, which is drawn from the data in Table 1 to indicate the distribution range of the resistance values. As is apparent from the figure, the resistor 2 having the suppression layer has a narrow distribution of resistance values and a high yield with respect to the resistor 1 having no suppression layer.

實施例Example

1.一種具有一特定電性的電子元件,其包括:一燒結元件層,其具有一第一電性;以及一燒結抑制層,其具有一第二電性,且與該燒結元件層形成一並聯狀態,其中該第二電性的大小須使該電子元件在該並聯狀態下,該特定電性係由該第一電性主導。What is claimed is: 1. An electronic component having a specific electrical property, comprising: a sintered component layer having a first electrical property; and a sintering inhibiting layer having a second electrical property and forming a layer with the sintered component layer a parallel state, wherein the second electrical property is such that the electronic component is in the parallel state, and the specific electrical system is dominated by the first electrical property.

2.如實施例1中的電子元件,其中該電子元件為一電阻器時,該特定電性、該第一電性以及該第二電性皆為電阻值,且該第二電性大於該第一電性,以使該特定電性以該第一電性主導。2. The electronic component of embodiment 1, wherein the electrical component is a resistor, the specific electrical property, the first electrical property, and the second electrical property are resistance values, and the second electrical property is greater than the electrical component The first electrical property is such that the specific electrical property is dominated by the first electrical property.

3.如實施例1~2中的任何一個實施例的電子元件, 其中該電子元件為一電容器時,該特定電性、該第一電性以及該第二電性皆為電容值,且該第二電性小於該第一電性,以使該特定電性以該第一電性主導。3. The electronic component of any of embodiments 1-2, When the electronic component is a capacitor, the specific electrical property, the first electrical property, and the second electrical property are capacitance values, and the second electrical property is less than the first electrical property, so that the specific electrical property is The first electrical dominant.

4.如實施例1~3中的任何一個實施例的電子元件,其中該電子元件為一電感器時,該特定電性、該第一電性以及該第二電性皆為電感值,且該第二電性大於該第一電性,以使該特定電性以該第一電性主導。4. The electronic component of any one of embodiments 1 to 3, wherein the specific electrical property, the first electrical property, and the second electrical property are both inductance values, and wherein the electrical component is an inductor, and The second electrical property is greater than the first electrical property such that the specific electrical property is dominated by the first electrical property.

5.如實施例1~4中的任何一個實施例的電子元件,其中該燒結元件層以及該燒結抑制層在一燒結溫度下,分別具有一第一收縮量以及一第二收縮量,且該第一收縮量大於該第二收縮量,以使該燒結抑制層在該燒結溫度下抑制該燒結元件層的收縮。5. The electronic component of any one of embodiments 1 to 4, wherein the sintered component layer and the sintering suppression layer respectively have a first shrinkage amount and a second shrinkage amount at a sintering temperature, and the The first shrinkage amount is greater than the second shrinkage amount such that the sintering suppression layer suppresses shrinkage of the sintered component layer at the sintering temperature.

6.如實施例1~5中的任何一個實施例的電子元件,其中該燒結元件層具有一第一開始燒結溫度,該燒結抑制層具有一第二開始燒結溫度,且該第一開始燒結溫度低於該第二開始燒結溫度。6. The electronic component of any one of embodiments 1 to 5, wherein the sintered component layer has a first onset sintering temperature, the sintered suppression layer has a second onset sintering temperature, and the first onset sintering temperature Below the second starting sintering temperature.

7.如實施例1~6中的任何一個實施例的電子元件更包括:一端電極,其位於該元件層與該抑制層兩者同一側表面。7. The electronic component of any one of embodiments 1 to 6 further comprising: an end electrode located on the same side surface of both the element layer and the suppression layer.

8.一種電子元件,其包括:一元件層,其具有一第一電性以及一第一燒結收縮量;以及一抑制層,其具有一第二電性以及一第二燒結收縮量,並位於該元件層上,其中若該電子元件為一電阻器以及一電感器其中之一,該第一電性小於該第二電性,以及若該電子元件為一電容器,該第一電性大於該第二電性。8. An electronic component comprising: a component layer having a first electrical property and a first amount of sintering shrinkage; and a suppression layer having a second electrical property and a second sintering shrinkage amount and located On the component layer, if the electronic component is one of a resistor and an inductor, the first electrical property is less than the second electrical property, and if the electronic component is a capacitor, the first electrical property is greater than the Second electrical.

9.如實施例8中的電子元件,其中該元件層具有一第 一開始燒結溫度,該抑制層具有一第二開始燒結溫度,且該第一開始燒結溫度低於該第二開始燒結溫度。9. The electronic component of embodiment 8, wherein the component layer has a first At the beginning of the sintering temperature, the suppression layer has a second onset sintering temperature, and the first onset sintering temperature is lower than the second onset sintering temperature.

10.如實施例8~9中的任何一個實施例的電子元件更包括:一端電極,其位於該元件層與該抑制層兩者同一側表面。10. The electronic component according to any one of embodiments 8 to 9 further comprising: an end electrode located on the same side surface of both the element layer and the suppression layer.

11.如實施例8~10中的任何一個實施例的電子元件,其中該第一燒結收縮量以及該第二燒結收縮量分別為該元件層以及該抑制層於一燒結溫度下所產生的收縮量。11. The electronic component of any one of embodiments 8 to 10, wherein the first amount of sintering shrinkage and the second amount of sintering shrinkage are shrinkage of the component layer and the suppression layer at a sintering temperature, respectively. the amount.

12.如實施例8~11中的任何一個實施例的電子元件,其中該第一燒結收縮量大於該第二燒結收縮量。12. The electronic component of any one of embodiments 8-11, wherein the first amount of sintering shrinkage is greater than the second amount of sintering shrinkage.

13.一種電子元件的製造方法,該方法的步驟包括:於具有一第一電性的一燒結元件層上形成具有一第二電性的一燒結抑制層上,其中若該電子元件為一電阻器或一電感器時,該第一電性小於該第二電性,以及若該電子元件為一電容器時,該第一電性大於該第二電性;以及將該燒結元件層以及該燒結抑制層於一燒結溫度下一起燒結。A method of manufacturing an electronic component, the method comprising: forming a sintering suppression layer having a second electrical property on a layer of a sintered component having a first electrical property, wherein the electronic component is a resistor Or the first electrical property is less than the second electrical property, and if the electronic component is a capacitor, the first electrical property is greater than the second electrical property; and the sintered component layer and the sintering The suppression layer is sintered together at a sintering temperature.

14.如實施例13中的方法之步驟更包括:於經燒結後的該燒結抑制層以及該燒結元件層兩者同一側表面上形成一端電極。14. The method of the method of embodiment 13 further comprising: forming an end electrode on the same side surface of both the sintered suppression layer and the sintered element layer after sintering.

15.如實施例13~14中的任何一個實施例中的方法,其中該第一燒結收縮量以及該第二燒結收縮量分別為該燒結元件層以及該燒結抑制層於該燒結溫度下所產生的收縮量。15. The method of any one of embodiments 13 to 14, wherein the first amount of sintering shrinkage and the second amount of sintering shrinkage are respectively generated by the sintered element layer and the sintering inhibiting layer at the sintering temperature. The amount of contraction.

16.如實施例13~15中的任何一個實施例中的方法,其中該燒結元件層具有一第一開始燒結溫度,該燒結抑制層具有一第二開始燒結溫度,且該第一開始燒結溫度低於該第二開始燒結溫度。16. The method of any one of embodiments 13 to 15, wherein the sintered element layer has a first onset sintering temperature, the sintering suppression layer has a second onset sintering temperature, and the first onset sintering temperature Below the second starting sintering temperature.

17.如實施例13~16中的任何一個實施例中的方法,其中該燒結溫度大於該第一開始燒結溫度。17. The method of any one of embodiments 13-16, wherein the sintering temperature is greater than the first onset sintering temperature.

18.如實施例13~17中的任何一個實施例中的方法,其中該燒結溫度大於該第二開始燒結溫度。18. The method of any one of embodiments 13-17, wherein the sintering temperature is greater than the second starting sintering temperature.

19.如實施例13~18中的任何一個實施例中的方法,該燒結元件層以及該燒結抑制層在該燒結溫度下,分別具有一第一收縮量以及一第二收縮量,且該第二收縮量小於該第一收縮量,以使該燒結抑制層在該燒結溫度下抑制該燒結元件層的收縮。19. The method of any one of embodiments 13 to 18, wherein the sintering element layer and the sintering suppression layer respectively have a first shrinkage amount and a second shrinkage amount at the sintering temperature, and the first The amount of contraction is less than the first amount of contraction such that the sintering suppression layer suppresses shrinkage of the layer of the sintered element at the sintering temperature.

20.一種電子元件,其具有一元件電性,其包括:一燒結元件層,其具有一第一電性;以及一燒結抑制層,具有一第二電性,且該第二電性之大小致使該元件電性由該第一電性主導。20. An electronic component having an electrical component comprising: a sintered component layer having a first electrical property; and a sintering inhibiting layer having a second electrical property and a second electrical property The electrical properties of the component are caused to be dominated by the first electrical property.

以上所述實施例僅係為了方便說明而舉例,並非限制本發明。因此熟悉本技藝之人士在不違背本發明之精神,對於上述實施例進行修改、變化,然皆不脫如附申請專利範圍所欲保護者。The embodiments described above are merely illustrative for convenience of description and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit and scope of the invention.

1‧‧‧積層陶瓷元件1‧‧‧Laminated ceramic components

11‧‧‧積層陶瓷層11‧‧‧Multilayer ceramic layer

12,32‧‧‧端電極12,32‧‧‧ terminal electrode

d121 ,d321 ‧‧‧電極深度d 121 ,d 321 ‧‧‧electrode depth

d122 ,d322 ‧‧‧電極距離d 122 ,d 322 ‧‧‧electrode distance

21‧‧‧積層陶瓷生坯21‧‧‧Laminated ceramic green body

24‧‧‧承載陶瓷基板24‧‧‧bearing ceramic substrate

3‧‧‧電子元件3‧‧‧Electronic components

31‧‧‧元件層31‧‧‧Component layer

331‧‧‧第一抑制層331‧‧‧First suppression layer

332‧‧‧第二抑制層332‧‧‧second suppression layer

4‧‧‧電子元件生坯4‧‧‧Electronic component blanks

41‧‧‧元件層生坯41‧‧‧Component layer green body

431‧‧‧第一抑制層生坯431‧‧‧First suppression layer green body

432‧‧‧第二抑制層生坯432‧‧‧Second suppression layer green body

44‧‧‧承載基板44‧‧‧Loading substrate

S51-S54‧‧‧步驟S51-S54‧‧‧Steps

第一圖為現今的積層陶瓷元件之示意圖;第二圖為現今的積層陶瓷元件的燒結方法之示意圖;第三圖(a)為本發明的電子元件的示意圖;第三圖(b)為本發明的電子元件中各個元件間的電性連接關係圖;第四圖為本發明的電子元件生坯在燒結製程下的示意 圖;第五圖為本發明電子元件的製作流程;第六圖為有無抑制層的電阻器在不同的電極深度下其電阻值的數據圖;以及第七圖為有無抑制層的電阻器的電阻值數據圖。The first figure is a schematic diagram of the current laminated ceramic component; the second figure is a schematic diagram of the sintering method of the current laminated ceramic component; the third figure (a) is a schematic view of the electronic component of the present invention; the third figure (b) is The electrical connection diagram between the various components in the electronic component of the invention; the fourth figure is an illustration of the green component green body of the invention under the sintering process Figure 5 is a flow chart showing the manufacturing process of the electronic component of the present invention; the sixth figure is a data chart of the resistance value of the resistor having the suppression layer at different electrode depths; and the seventh figure is the resistance of the resistor having the suppression layer. Value data graph.

3‧‧‧電子元件3‧‧‧Electronic components

31‧‧‧元件層31‧‧‧Component layer

32‧‧‧端電極32‧‧‧ terminal electrode

331‧‧‧第一抑制層331‧‧‧First suppression layer

332‧‧‧第二抑制層332‧‧‧second suppression layer

d321 ‧‧‧電極深度d 321 ‧‧‧electrode depth

d322 ‧‧‧電極距離d 322 ‧‧‧electrode distance

Claims (12)

一種電子元件,其包含:一燒結元件層,其具有一第一電性、一上表面與一下表面;一第一燒結抑制層,其具有一第二電性,並覆蓋於該上表面;以及一第二燒結抑制層,其具有一第三電性,並覆蓋於該下表面,其中該第一燒結抑制層、該第二燒結抑制層及該燒結元件層形成一並聯狀態;以及一端電極,位於該燒結元件層、該第一燒結抑制層與該第二燒結抑制層三者之同一側表面;其中,該電子元件具有一第四電性,而該第四電性與該第二電性之差值以及該第四電性與該第三電性之差值,皆大於該第四電性與該第一電性之差值,其中該第一電性、該第二電性、該第三電性與該第四電性皆為電阻值、電感值或電容值。 An electronic component comprising: a sintered component layer having a first electrical property, an upper surface and a lower surface; a first sintering suppression layer having a second electrical property and covering the upper surface; a second sintering suppression layer having a third electrical property and covering the lower surface, wherein the first sintering suppression layer, the second sintering suppression layer and the sintered element layer form a parallel state; and an end electrode, The same side surface of the sintered element layer, the first sintering suppression layer and the second sintering suppression layer; wherein the electronic component has a fourth electrical property, and the fourth electrical property and the second electrical property The difference between the fourth electrical property and the third electrical property is greater than a difference between the fourth electrical property and the first electrical property, wherein the first electrical property, the second electrical property, the first electrical property The third electrical property and the fourth electrical property are resistance values, inductance values, or capacitance values. 如申請專利範圍第1項所述之電子元件,其中該電子元件為一電阻器,該第一電性、該第二電性、該第三電性以及該第四電性皆為電阻值,且該第二電性大於該第一電性,以使該特定電性以該第一電性主導。 The electronic component of claim 1, wherein the electronic component is a resistor, and the first electrical property, the second electrical property, the third electrical property, and the fourth electrical property are resistance values. And the second electrical property is greater than the first electrical property such that the specific electrical property is dominated by the first electrical property. 如申請專利範圍第1項所述之電子元件,其中該電子元件為一電感器,該第一電性、該第二電性、該第三電性以及該第四電性皆為電感值,且該第二電性大於該第一電性,以使 該特定電性以該第一電性主導。 The electronic component of claim 1, wherein the electronic component is an inductor, and the first electrical property, the second electrical property, the third electrical property, and the fourth electrical property are inductance values, And the second electrical property is greater than the first electrical property such that The specific electrical property is dominated by the first electrical property. 如申請專利範圍第1項所述之電子元件,其中該電子元件為一電容器,該第一電性、該第二電性、該第三電性以及該第四電性皆為電容值,且該第二電性小於該第一電性,以使該特定電性以該第一電性主導。 The electronic component of claim 1, wherein the electronic component is a capacitor, and the first electrical property, the second electrical property, the third electrical property, and the fourth electrical property are capacitance values, and The second electrical property is less than the first electrical property such that the specific electrical property is dominated by the first electrical property. 如申請專利範圍第1項所述之電子元件,其中該燒結元件層、該第一燒結抑制層以及該第二燒結抑制層在一燒結溫度下,分別具有一第一收縮量、一第二收縮量以及一第三收縮量,且該第一收縮量大於該第二收縮量以及該第三收縮量,以使該第一燒結抑制層及該第二燒結抑制層在該燒結溫度下抑制該燒結元件層的收縮。 The electronic component of claim 1, wherein the sintered component layer, the first sintering suppression layer, and the second sintering suppression layer respectively have a first shrinkage amount and a second shrinkage at a sintering temperature. And a third shrinkage amount, wherein the first shrinkage amount is greater than the second shrinkage amount and the third shrinkage amount, so that the first sintering suppression layer and the second sintering suppression layer suppress the sintering at the sintering temperature Shrinkage of the component layer. 一種電子元件,其包含:一元件層,其具有一第一電性以及一第一燒結收縮量;一第一抑制層,其具有一第二電性以及一第二燒結收縮量,並覆蓋於該元件層之上表面;以及一第二抑制層,其具有一第三電性以及一第三燒結燒縮量,並覆蓋於該元件層之下表面;其中,該第一燒結收縮量、該第二燒結收縮量以及該第三燒結收縮量分別為該元件層、該第一抑制層以及該第二抑制層於一燒結溫度下所產生的收縮量,且該第二燒結收縮量與該第三燒結收縮量皆小於該第一燒結收縮量,以使該第一抑制層與第二抑制層在該燒結溫度下抑制該元件層的收縮;其中若該電子元件為一電阻器以及一電感器其中之一, 該第一電性小於該第二電性與該第三電性,以及若該電子元件為一電容器,該第一電性大於該第二電性與該第三電性,其中該第一電性、該第二電性與該第三電性皆為電阻值、電感值或電容值。 An electronic component comprising: a component layer having a first electrical property and a first amount of sintering shrinkage; a first suppression layer having a second electrical property and a second sintering shrinkage amount and covering a surface of the element layer; and a second suppression layer having a third electrical property and a third sintering shrinkage amount and covering the lower surface of the component layer; wherein the first sintering shrinkage amount, the The second sintering shrinkage amount and the third sintering shrinkage amount are respectively the shrinkage amount of the element layer, the first suppression layer, and the second suppression layer at a sintering temperature, and the second sintering shrinkage amount and the first The third sintering shrinkage amount is less than the first sintering shrinkage amount, so that the first suppression layer and the second suppression layer suppress the shrinkage of the element layer at the sintering temperature; wherein the electronic component is a resistor and an inductor one of them, The first electrical property is less than the second electrical property and the third electrical property, and if the electronic component is a capacitor, the first electrical property is greater than the second electrical property and the third electrical property, wherein the first electrical property The second electrical property and the third electrical property are resistance values, inductance values, or capacitance values. 如申請專利範圍第6項所述之電子元件,更包含:一端電極,其位於該元件層、該第一抑制層以及該第二抑制層三者同一側表面。 The electronic component of claim 6, further comprising: an end electrode located on the same side surface of the element layer, the first suppression layer and the second suppression layer. 如申請專利範圍第6項所述之電子元件,其中該第一燒結收縮量、該第二燒結收縮量以及該第三燒結收縮量分別為該元件層、該第一抑制層以及該第二抑制層於一燒結溫度下所產生的收縮量。 The electronic component according to claim 6, wherein the first sintering shrinkage amount, the second sintering shrinkage amount, and the third sintering shrinkage amount are the component layer, the first suppression layer, and the second suppression, respectively. The amount of shrinkage produced by the layer at a sintering temperature. 一種電子元件的製造方法,其步驟包含:於具有一第一電性的一燒結元件層之上表面形成具有一第二電性的一第一燒結抑制層;於該燒結元件層之下表面形成具有一第三電性的一第二燒結抑制層;其中若該電子元件為一電阻器或一電感器時,該第一電性小於該第二電性與該第三電性,以及若該電子元件為一電容器時,該第一電性大於該第二電性與該第三電性,其中該第一電性、該第二電性與該第三電性皆為電阻值、電感值或電容值;以及將該燒結元件層、該第一燒結抑制層以及該第二燒結抑制層於一燒結溫度下一起燒結。 A method of manufacturing an electronic component, comprising: forming a first sintering suppression layer having a second electrical property on a surface of a sintered component layer having a first electrical property; forming a lower surface of the sintered component layer a second sintering suppression layer having a third electrical property; wherein if the electronic component is a resistor or an inductor, the first electrical property is less than the second electrical property and the third electrical property, and if When the electronic component is a capacitor, the first electrical property is greater than the second electrical property and the third electrical property, wherein the first electrical property, the second electrical property, and the third electrical property are both resistance values and inductance values. Or a capacitance value; and sintering the sintered element layer, the first sintering suppression layer, and the second sintering suppression layer together at a sintering temperature. 如申請專利範圍第9項所述之方法,更包含:於經燒結後的該第一燒結抑制層、該第二燒結抑制層以及該燒結元件層三者同一側表面上形成一端電極。 The method of claim 9, further comprising forming an end electrode on the same side surface of the sintered first sintering suppression layer, the second sintering suppression layer, and the sintered element layer. 如申請專利範圍第9項所述之方法,其中該燒結元件層具有一第一開始燒結溫度,該第一燒結抑制層具有一第二開始燒結溫度,該第二燒結抑制層具有一第三開始燒結溫度,且該第一開始燒結溫度低於該第二開始燒結溫度與該第三開始燒結溫度。 The method of claim 9, wherein the sintered element layer has a first onset sintering temperature, the first sintering suppression layer has a second onset sintering temperature, and the second sintering suppression layer has a third start a sintering temperature, and the first starting sintering temperature is lower than the second starting sintering temperature and the third starting sintering temperature. 如申請專利範圍第10項所述之方法,其中該燒結元件層、第一燒結抑制層以及該第二燒結抑制層在該燒結溫度下,分別具有一第一收縮量、一第二收縮量以及一第三收縮量,且該第二收縮量與該第三收縮量小於該第一收縮量,以使該第一燒結抑制層以及該第二燒結抑制層在該燒結溫度下抑制該燒結元件層的收縮。 The method of claim 10, wherein the sintering element layer, the first sintering suppression layer, and the second sintering suppression layer respectively have a first shrinkage amount, a second shrinkage amount, and a third shrinkage amount, and the second shrinkage amount and the third shrinkage amount are smaller than the first shrinkage amount, so that the first sintering suppression layer and the second sintering suppression layer suppress the sintering element layer at the sintering temperature Contraction.
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