TWI505409B - 一種化合物半導體晶圓結構 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 32
- 150000001875 compounds Chemical class 0.000 title claims description 25
- 230000005669 field effect Effects 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 15
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 8
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910005540 GaP Inorganic materials 0.000 claims description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- 239000012636 effector Substances 0.000 claims 2
- 238000000034 method Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000002687 intercalation Effects 0.000 description 1
- 238000009830 intercalation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003389 potentiating effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Description
本發明係有關一種化合物半導體晶圓結構，尤指一種整合異質接面雙極電晶體(heterojunction bipolar transistor；HBT)、場效電晶體(field effect transistor；FET)以及閘流管電晶體(Thyristor)磊晶結構於單一晶圓，可應用於靜電防護(Electrostatic Discharge,ESD)系統之化合物半導體晶圓結構。
當人體碰觸積體電路時，人體上累積的靜電會經由積體電路的接腳進入電路中，再經由積體電路接地放電，放電過程會在短短幾百奈秒(ns)時間產生數安培的瞬間電流，造成積體電路元件功能異常或損毀，因此在積體電路中通常需要設計一靜電防護系統以保護電路中的元件。
在化合物半導體單一晶圓製程中，受限於磊晶層的設計，在靜電防護的設計方面，傳統上多是使用pn接面二極體或蕭基二極體(Schottky diode)，在實際應用上，通常是在晶元上先製作多個二極體，再將這些二極體串接使用，因此需佔據較大晶圓面積，且二極體之導通電壓較小，靜電防護能力因此受到限制。
矽控整流器(silicon-controlled rectifier；SCR)為閘流管電晶體(Thyristor)的一種，其結構為pnpn結構，係廣泛應用於矽晶圓製程。矽控整流器具有高導通電壓，而當元件進入導通狀態時則具有一低持有電壓(holding voltage)，應用於靜電防護電路時可
將系統電壓箝制在很低的電壓準位，使內部電路可以有效地被保護住，具有良好的靜電防護效能。
目前在化合物半導體晶圓結構方面，為了提高元件積集度，已逐漸採用一種稱為BiFET/BiHEMT的結構，亦即一種異質接面雙極電晶體(HBT)與場效電晶體/高電子遷移率電晶體(FET/HEMT)之垂直堆疊結構，可以將HBT與FET/HEMT元件整合於同一晶片上；由於HBT具有npn或pnp接面結構，而FET/HEMT可為n型或p型，因此，如能在BiFET/BiHEMT結構中形成矽控整流器所需之pnpn結構，即可將矽控整流器與BiFET/BiHEMT結構加以整合，能更加提高單一晶圓之應用範圍，同時可大幅改善靜電防護能力。
本發明之主要目的在於提供一種化合物半導體晶圓結構，其係於一BiFET結構中插入一n型摻雜蝕刻終止層以及一p型插入層，藉以整合場效電晶體(FET)、異質接面雙極電晶體(HBT)以及閘流管電晶體(Thyristor)之磊晶結構於一化合物半導體晶圓結構中；其中該閘流管電晶體可應於靜電保護系統(ESD)，可大幅縮小傳統利用二極體之靜電保護電路晶圓使用面積，並進一步提升靜電保護能力，大幅增進產品競爭力。
為達上述目的，本發明提供一種化合物半導體晶圓結構，包含一基板、一場效電晶體磊晶結構、一n型摻雜蝕刻終止層、一p型插入層以及一異質接面雙極電晶體結構，其中該場效電晶體磊
晶結構係位於該基板之上，包含一通道層以及一n型摻雜層，其中該n型摻雜層係位於該通道層之上，可用以製作n型場效電晶體；該異質接面雙極電晶體磊晶結構由下而上依序包含一次集極層、一集極層、一基極層以及一射極層，其中該次集極層、該集極層以及該射極層係為一n型摻雜層而該基極層係為一p型摻雜層，從而構成一npn型異質接面雙極電晶體磊晶結構；其中該場效電晶體磊晶結構、該n型摻雜蝕刻終止層、該p型插入層以及該異質接面雙極電晶體磊晶結構之次集極層、集極層與基極層可構成一具有pnpn型接面結構之閘流管電晶體(Thyristor)磊晶結構。
於實施時，前述結構中之n型摻雜蝕刻終止層係由磷化銦鎵(InGaP)所構成，其摻雜濃度係為大於等於1×1015
且小於等於1×1022
cm-3
，且其厚度為介於50 Å至5000 Å之間。
於實施時，前述結構中之p型插入層可包含一至數層p型摻雜層，其中兩兩相鄰之p型摻雜層其摻雜濃度不同，該p型插入層每一層摻雜濃度為大於等於1×1015
cm-3
且小於等於1×1022
cm-3
，且其每一層厚度為介於500 Å至20000 Å之間。
於實施時，前述結構中之p型插入層可包含一p+型摻雜層以及一p-型摻雜層，其中該p+型摻雜層係為一高濃度p型摻雜層，而該p-型摻雜層係為一低濃度p型摻雜層，該p-型摻雜層係位於該p+型摻雜層之上。
於實施時，前述p+型摻雜層以及p-型摻雜層係由砷化鎵(GaAs)所構成。
於實施時，前述p+型摻雜層之摻雜濃度為大於等於1×1018
cm-3
且小於等於1×1022
cm-3
，且其厚度為大於等於1000 Å且小於等於2000 Å。
於實施時，前述p-型摻雜層之摻雜濃度為大於等於1×1016
cm-3
且小於等於1×1017
cm-3
，且其厚度為大於等於2500 Å且小於等於15000 Å。
於實施時，前述場效電晶體磊晶結構可為一n型金屬半導體場效電晶體(metal semiconductor transistor；MESFET)磊晶結構。
於實施時，前述場效電晶體磊晶結構可為一n型高電子遷移率電晶體(high electron mobility transistor；HEMT)磊晶結構。
於實施時，前述場效電晶體磊晶結構可為一n型偽晶型高電子遷移率電晶體(pseudomorphic high electron mobility transistor；pHEMT)磊晶結構。
於實施時，構成前述基板的材料可為砷化鎵(GaAs)或磷化銦(InP)。
為對於本發明之特點與作用能有更深入之瞭解，茲藉實施例配合圖式詳述於後：
本發明所提供之整合一場效電晶體(FET)、一異質接面雙極電晶體(HBT)以及一閘流管電晶體(Thyristor)之磊晶結構的化合物半導體晶圓結構，如第1圖所示，包含一基板101、一場效電晶體磊晶結構110、一n型摻雜蝕刻終止層121、一p型插入層122
以及一異質接面雙極電晶體結構130，其中該基板101之構成材料可為砷化鎵(GaAs)或磷化銦(InP)等半絕緣性半導體材料，其中以砷化鎵(GaAs)為較佳；該場效電晶體磊晶結構110，係位於該基板101之上，包含一通道層111以及一n型摻雜層112，其中該n型摻雜層係位於該通道層之上，此結構可用以製作n型場效電晶體；該n型摻雜蝕刻終止層121係位於該場效電晶體磊晶結構110之上；該p型插入層122係位於n型摻雜蝕刻終止層121之上；該異質接面雙極電晶體磊晶結構130由下而上依序包含一次集極層131、一集極層132、一基極層133以及一射極層134，其中該次集極層131、該集極層132以及該射極層134係為一n型摻雜層，而該基極層133係為一p型摻雜層，從而構成一npn型異質接面雙極電晶體磊晶結構130；如此一來，此化合物半導體晶圓結構由上而下具有n-p-n-p-n結構，而包含了形成一閘流管電晶體(Thyristor)所需之p-n-p-n結構，亦即，該n型場效電晶體磊晶結構、該n型摻雜蝕刻終止層、該p型插入層以及該異質接面雙極電晶體磊晶結構之p型摻雜基極層、n型摻雜集極層、與n型摻雜次集極層可構成一具有pnpn型接面結構之閘流管電晶體(Thyristor)磊晶結構120。
於實施時，場效電晶體磊晶結構110可為一n型金屬半導體場效電晶體(MESFET)、一n型高電子遷移率電晶體(HEMT)、一n型偽晶型高電子遷移率電晶體(pHEMT)或其他n型場效電晶體之磊晶結構；n型摻雜蝕刻終止層121之構成材料以磷化銦鎵(InGaP)為較佳，其摻雜濃度為介於1×1015
至1×1022
cm-3
之間，其中以介於1×1017
至1×1018
cm-3
之間為較佳，其厚度可為介於50
Å至5000 Å之間，其中以介於100 Å至500 Å之間為較佳；p型插入層122可包含一至數層p型摻雜層，其中兩兩相鄰之p型摻雜層其摻雜濃度不同，其每一層摻雜濃度為大於等於1×1015
且小於等於1×1022
cm-3
，且其每一層厚度為介於500 Å至20000 Å之間；異質接面雙極電晶體磊晶結構130之主要構成材料可為砷化鎵(GaAs)，其次集極層131摻雜濃度為介於1×1015
至1×1022
cm-3
之間，其中以大於等於1×1018
cm-3
且小於等於1×1022
cm-3
之高摻雜濃度為較佳。應用於半導體元件中，如第2圖所示，可於前述晶圓整合結構之n型摻雜層112上設置一源極電極201以及一汲極電極202，於源極與汲極之間的n型摻雜層凹槽內設置一連結通道層111之閘極電極203，則該通道層111、該n型摻雜層112、該源極電極201、該汲極電極202以及該閘極電極203可構成一n型場效電晶體(FET)210；於前述晶圓整合結構之基極層133上設置一基極電極204，於次集極層131上設置一集極電極205，並於射極層134上設置一射極電極206，則該次集極層131、該集極層132、該基極層133、該射極層134、該基極電極204、該集極電極205以及該射極電極206可構成一異質接面雙極電晶體(HBT)230；於基極層133上設置一陽極電極207，並於n型摻雜層112上設置一陰極電極208，則該n型摻雜層112、該n型摻雜蝕刻終止層121、該p型插入層122、該次集極層131、該集極層132、該基極層133、該陽極電極207以及該陰極電極208可構成一閘流管電晶體(Thyristor)220。
表1為本發明之化合物半導體晶圓結構之一實施例；此實施例包含一基板以及位於該基板上的14層磊晶層，其中從上而下的
第1層及第2層為一高摻雜濃度之射極接觸層與一覆蓋層，第3至6層為射極層，包含複數層不同厚度與不同摻雜濃度之n型摻雜層；第7層為基極層，係為一高摻雜濃度之p型摻雜層；第8至10層為n型摻雜之集極層與n+型摻雜之次集極層；第11、12層為p型摻雜層，分別為一p+型摻雜層及一p-型摻雜層，係由砷化鎵(GaAs)所構成，該p+型摻雜層係為一高濃度p型摻雜層，而該p-型摻雜層係為一低濃度p型摻雜層，其中該p-型摻雜層係位於該p+型摻雜層之上，該p+型摻雜層之摻雜濃度可選擇為大於等於1×1018
cm-3
且小於等於1×1022
cm-3
，且其厚度可為大於等於1000 Å且小於等於2000 Å，在此實施例中該p+型摻雜層之摻雜濃度選擇為1×1018
cm-3
，且厚度選擇為1000 Å；而該p-型摻雜層之摻雜濃度為大於等於1×1016
cm-3
且小於等於1×1017
cm-3
，且其厚度可為大於等於2500 Å且小於等於15000 Å，在此實施例中該p-型摻雜層之摻雜濃度選擇為1×1016
cm-3
，且厚度選擇為2500 Å；第13層為n型摻雜蝕刻終止層，其係由磷化銦鎵(InGaP)所構成，其摻雜濃度選擇為3×1017
cm-3
，且其厚度選擇為200 Å；第14層為一n+型摻雜層，其摻雜濃度選擇為4×1018
cm-3
，且其厚度選擇為4000 Å。此實施例中的第7至14層為p-n-p-n結構，可用以製作一閘流管電晶體(Thyristor)。
半導體積體電路之靜電防護性能通常是以傳輸線脈衝系統(Transmission Line Pulse,TLP)進行測試，在此測試中係將一高電流脈衝訊號輸入測試電路中，所測得之入射與反射脈衝訊號經過計算可得出測試電路的電壓-電流變化曲線；此高電流脈衝輸入訊號之能量範圍與脈衝時間長度係接近人體放電模式(Human Body
Model,HBM)；第3圖為本發明所提供之閘流管電晶體之TLP電壓-電流特性曲線(實線)，並與串接二極體之TLP電壓-電流特性曲線(虛線)做一比較；圖中顯示應用本發明之晶圓結構所製作的閘流管電晶體之觸發電壓(trigger voltage)約為8伏特，持有電壓(holding voltage)約為2伏特，元件崩潰電流(device failure current)約為0.57安培；與先前技術中以串接二極體作為靜電防護電路之TLP電壓-電流特性曲線相比，本發明所提供之閘流管電晶體具有較高的觸發電壓，且元件觸發後亦能維持較低的持有電壓；此元件之觸發電壓與持有電壓係受插入之p型摻雜層之厚度與摻雜濃度影響；藉由調整p型摻雜層厚度與摻雜濃度可達到更佳的元件靜電防護功能。
綜上所述，本發明確實可達到預期之目的，而提供一種包含場效電晶體(FET)、異質接面雙極電晶體(HBT)以及閘流管電晶體(Thyristor)磊晶結構之單一化合物半導體晶圓結構；利用本晶圓結構製作的閘流管電晶體可用於靜電保護電路(ESD)，可以大幅縮小靜電保護電路使用面積，且閘流管電晶體具有較高觸發電壓，較低持有電壓，較低的能量耗損，並且對高電流具有較佳的處理能力，因此能進一步提升靜電防護能力，大幅增進產品競爭力；此外，本發明可與現有的BiFET/BiHEMT製程整合，因此可大幅降低生產製造的成本。其確具產業利用之價值，爰依法提出專利申請。
又上述說明與圖式僅是用以說明本發明之實施例，凡熟於此業技藝之人士，仍可做等效的局部變化與修飾，其並未脫離本發明之技術與精神。
101‧‧‧基板
110‧‧‧場效電晶體磊晶結構
120‧‧‧閘流管電晶體磊晶結構
130‧‧‧異質接面雙極電晶體磊晶結構
111‧‧‧通道層
112‧‧‧n型摻雜層
121‧‧‧n型摻雜蝕刻終止層
122‧‧‧p型插入層
131‧‧‧次集極層
132‧‧‧集極層
133‧‧‧基極層
134‧‧‧射極層
210‧‧‧場效電晶體
220‧‧‧閘流管電晶體
230‧‧‧異質接面雙極電晶體
201‧‧‧源極電極
202‧‧‧汲極電極
203‧‧‧閘極電極
204‧‧‧基極電極
205‧‧‧集極電極
206‧‧‧射極電極
207‧‧‧陽極電極
208‧‧‧陰極電極
第1圖 係為本發明之一種化合物半導體晶圓結構之剖面結構示意圖。
第2圖 係為本發明之一種化合物半導體晶圓結構應用於半導體元件中之剖面結構示意圖。
第3圖 係為本發明中閘流管電晶體(Thyristor)之傳輸線脈衝系統(TLP)測試之電流對電壓變化圖。
101‧‧‧基板
110‧‧‧場效電晶體磊晶結構
120‧‧‧閘流管電晶體磊晶結構
130‧‧‧異質接面雙極電晶體磊晶結構
111‧‧‧通道層
112‧‧‧n型摻雜層
121‧‧‧n型摻雜蝕刻終止層
122‧‧‧p型插入層
131‧‧‧次集極層
132‧‧‧集極層
133‧‧‧基極層
134‧‧‧射極層
Claims (11)
- 一種化合物半導體晶圓結構，整合一場效電晶體(FET)、一異質接面雙極電晶體(HBT)以及一閘流管電晶體(Thyristor)之磊晶結構，依序包含：一基板；一場效電晶體磊晶結構，係位於該基板之上，包含：一通道層，以及一n型摻雜層位於該通道層之上；一n型摻雜蝕刻終止層；一p型插入層，係位於該n型摻雜蝕刻終止層之上；以及一異質接面雙極電晶體結構，係位於該p型插入層之上，包含：一次集極層，為一n型摻雜層，一集極層，位於該次集極層之上，為一n型摻雜層，一基極層，位於該集極層之上，為一p型摻雜層，以及一射極層，位於該基極層之上，為一n型摻雜層；其中該p型插入層包含一層p型摻雜層，該p型摻雜層的摻雜濃度為非均勻性分布，且該p型摻雜層的摻雜濃度為大於等於1×1015 cm-3 且小於等於1×1022 cm-3 ，且其厚度為介於500Å至20000Å之間；其中該場效電晶體磊晶結構、該n型摻雜蝕刻終止層、該p型插入層以及該異質接面雙極電晶體磊晶結構之次集極層、集極層與基極層構成一閘流管電晶體(Thyristor)磊晶 結構。
- 一種化合物半導體晶圓結構，整合一場效電晶體(FET)、一異質接面雙極電晶體(HBT)以及一閘流管電晶體(Thyristor)之磊晶結構，依序包含：一基板；一場效電晶體磊晶結構，係位於該基板之上，包含：一通道層，以及一n型摻雜層位於該通道層之上；一n型摻雜蝕刻終止層；一p型插入層，係位於該n型摻雜蝕刻終止層之上；以及一異質接面雙極電晶體結構，係位於該p型插入層之上，包含：一次集極層，為一n型摻雜層，一集極層，位於該次集極層之上，為一n型摻雜層，一基極層，位於該集極層之上，為一p型摻雜層，以及一射極層，位於該基極層之上，為一n型摻雜層；其中該p型插入層包含複數層p型摻雜層，其中兩兩相鄰之p型摻雜層其摻雜濃度不同，該p型插入層每一層摻雜濃度為大於等於1×1015 cm-3 且小於等於1×1022 cm-3 ，且其每一層厚度為介於500Å至20000Å之間；其中該場效電晶體磊晶結構、該n型摻雜蝕刻終止層、該p型插入層以及該異質接面雙極電晶體磊晶結構之次集極層、集極層與基極層構成一閘流管電晶體(Thyristor)磊晶 結構。
- 如申請專利範圍第1或2項所述之化合物半導體晶圓結構，其中該n型摻雜蝕刻終止層係由磷化銦鎵(InGaP)所構成，其摻雜濃度係為大於等於1×1015 cm-3 且小於等於1×1022 cm-3 ，且其厚度為介於50Å至5000Å之間。
- 如申請專利範圍第2項所述之化合物半導體晶圓結構，其中該p型插入層包含一p+型摻雜層以及一p-型摻雜層，其中該p+型摻雜層係為一高濃度p型摻雜層，而該p-型摻雜層係為一低濃度p型摻雜層，該p-型摻雜層係位於該p+型摻雜層之上。
- 如申請專利範圍第4項所述之化合物半導體晶圓結構，其中該p+型摻雜層以及該p-型摻雜層係由砷化鎵(GaAs)所構成。
- 如申請專利範圍第4項所述之化合物半導體晶圓結構，其中該p+型摻雜層之摻雜濃度為大於等於1×1018 cm-3 且小於等於1×1022 cm-3 ，且其厚度為大於等於1000Å且小於等於2000Å。
- 如申請專利範圍第4項所述之化合物半導體晶圓結構，其中該p-型摻雜層之摻雜濃度為大於等於1×1016 cm-3 且小於等於1×1017 cm-3 ，且其厚度為大於等於2500Å且小於等於15000Å。
- 如申請專利範圍第1或2項所述之化合物半導體晶圓結構，其中該場效電晶體磊晶結構係為一n型金屬半導體場效電晶體(MESFET)磊晶結構。
- 如申請專利範圍第1或2項所述之化合物半導體晶圓結構，其中該場效電晶體磊晶結構係為一n型高電子遷移率電晶體(HEMT)磊晶結構。
- 如申請專利範圍第1或2項所述之化合物半導體晶圓結構，其中該場效電晶體磊晶結構係為一n型偽晶型高電子遷移率電晶體(pHEMT)磊晶結構。
- 如申請專利範圍第1或2項所述之化合物半導體晶圓結構，其中構成該基板的材料為砷化鎵(GaAs)或磷化銦(InP)。
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