TWI503969B - High electron mobility transistor and manufacturing method thereof - Google Patents

Description

High electron mobility transistor and method of manufacturing same

The present invention relates to a high electron mobility transistor and a method of fabricating the same, and more particularly to a barrier layer including a first portion under the gate and a second portion adjacent thereto, and the first portion and the second portion of the barrier layer A high electron mobility transistor having a different molar fraction of Al and Ga and a method of manufacturing the same.

Aluminum gallium nitride/gallium nitride high electron mobility transistors (AlGaN/GaN HEMTs) are often used in high power, high temperature, and high frequency circuit operations due to their excellent carrier transport characteristics.

However, in the existing high electron mobility transistor, since a two-dimensional electron gas (2DEG) is formed between the barrier layer and the channel layer, a very fast switching speed can be achieved. But relatively, because the electron transit path exists at any time, even if the gate voltage is zero, the current will pass, causing the problem of the high electron mobility transistor normally-on, that is, when operating as a circuit operation component. Even if no voltage is applied to the gate, the channel still exists, that is, there is still current passing, which causes inconvenience in circuit operation.

In view of the above, the inventors of the present invention have conceived and designed a high electron mobility transistor and a manufacturing method thereof to improve the defect of the prior art, so that the high electron mobility transistor can be normally closed (Normally-Off). Improve the implementation of the industry use.

In view of the above problems of the prior art, it is an object of the present invention to provide a high electron mobility transistor and a method of fabricating the same that solve the problem of the normally-on problem of the high electron mobility transistor of the prior art.

In accordance with the purpose of the present invention, a high electron mobility transistor is disclosed that includes a substrate, a channel layer, a barrier layer, a source, a drain, and a gate. The channel layer is formed on the substrate. A barrier layer is formed on the channel layer. The source is formed on the barrier layer, and an ohmic contact is formed between the source and the channel layer. The drain is formed on the barrier layer and an ohmic contact is formed between the drain and the channel layer. A gate is formed on the barrier layer to form a Schottky Contact, wherein the gate is located between the source and the drain. Wherein the barrier layer comprises a first portion under the gate and a second portion below the source and the drain and adjacent to the first portion, the first portion being formed of Al _x Ga _1-x N and having a first thickness, The two portions are formed of Al _y Ga _1-y N and have a second thickness. Wherein the first thickness is less than the second thickness and the x value is less than the y value.

Preferably, the channel layer can be formed of GaN.

Preferably, the value of x can be from 0.02 to 0.5 and the value of y can range from 0.2 to 0.7.

Preferably, the first thickness may be between 1 nm and 4 nm, and the second thickness may be between 1.5 nm and 40 nm.

According to the purpose of the present invention, a method for manufacturing a high electron mobility transistor is further provided, which comprises the steps of: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; forming a source in the barrier layer Forming an ohmic contact between the source and the channel layer; forming a drain on the barrier layer, forming an ohmic contact between the drain and the channel layer; and forming a gate on the barrier layer to form a Schottky contact, wherein the gate Located between the source and the drain; wherein the barrier layer includes a first portion under the gate and a second portion below the source and the drain and adjacent to the first portion, the first portion being Al _x Ga _1-x N is formed and has a first thickness, and the second portion is formed of Al _y Ga _1-y N and has a second thickness; wherein the first thickness is less than the second thickness and the x value is less than the y value.

According to the present invention, the high electron mobility transistor and the method of manufacturing the same can have the following advantages: the high electron mobility transistor and the method of fabricating the same can reduce the barrier layer under the gate Ear fraction and thickness to improve the problem of high electron mobility transistor Normally-On.

1‧‧‧High Electron Mobility Transistor

11‧‧‧Substrate

12‧‧‧Channel layer

13‧‧‧ obstacle layer

131‧‧‧Part 1

132‧‧‧Part II

14‧‧‧ source

15‧‧‧汲polar

16‧‧‧ gate

S1~S6‧‧‧Step process

Fig. 1 is a structural view of a high electron mobility transistor of the present invention.

Fig. 2 is a flow chart showing the steps of the method for producing a high electron mobility transistor of the present invention.

The technical features, contents, and advantages of the present invention, as well as the advantages thereof, can be understood by the present inventors, and the present invention will be described in detail with reference to the accompanying drawings. The subject matter is only for the purpose of illustration and description. It is not intended to be a true proportion and precise configuration after the implementation of the present invention. Therefore, the scope and configuration relationship of the attached drawings should not be interpreted or limited. First described.

Please refer to FIG. 1 , which is a structural diagram of a high electron mobility transistor of the present invention. As shown, the high electron mobility transistor 1 of the present invention comprises a substrate 11, a channel layer 12, a barrier layer 13, a source 14, a drain 15 and a gate 16. Channel layer 12 and barrier layer 13 The substrate 11 can be sequentially formed on the substrate 11 by, for example, a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method, wherein the substrate 11 can be, for example, a sapphire substrate. The source 14 is formed on the barrier layer 13 and an ohmic contact is formed between the source 14 and the channel layer 12; the drain 15 is formed on the barrier layer 13 and an ohmic contact is formed between the drain 15 and the channel layer 12.

Next, the barrier layer 13 can be etched to form a recess, for example, by conventional lithography and etching processes, and the gate 16 is formed in the recess of the barrier layer 13 using the same mask pattern to form a Schottky contact. The gate 16 is located between the source 14 and the drain 15 , and the material of the gate 16 can be selected, for example, from the group consisting of Al and Ni.

It is to be noted that the barrier layer 13 can be divided into a first portion 131 and a second portion 132. The first portion 131 is located below the gate 16 and has a relatively thin thickness. The second portion 132 is located below the source 14 and the drain 15 adjacent to the first portion 131. The second portion 132 is thicker. Further, the barrier layer 13 is entirely formed of a compound of Al, Ga, and N, however, the first portion 131 and the second portion 132 have different Mo content of Al depending on the amount of Al added. When the first portion 131 is represented by Al _x Ga _1-x N and the second portion 132 is represented by Al _y Ga _1-y N, the value of x is less than the value of y, that is, the molar fraction of Al of the first portion 131 Less than the molar fraction of Al of the second portion 132.

In this way, by reducing the thickness of the first portion 131 and the molar fraction of Al, the polarization effect between the channel layer 12 and the barrier layer 13 is changed, so that the lower portion of the first portion 131 of the barrier layer 13 and the channel layer 12 interface The concentration of the two-dimensional electron gas (2DEG) is lowered, and the threshold voltage of the transistor is increased, so that the high electron mobility transistor 1 tends to be in a Normal-Off state, that is, when the gate is not applied with a voltage, the channel is not Existence, that is, no current will pass, making the circuit more convenient to operate. In addition, The structure of the high electron mobility transistor 1 of the present invention also makes the threshold voltage higher than 1V, thereby making it less susceptible to leakage current problems and reducing power consumption.

Incidentally, the channel layer 12 can be formed of GaN. Since GaN has spontaneous polarization and piezoelectric polarization, it has higher electron concentration than conventional Si and GaAs, and can improve the high electron mobility transistor 1 of the present invention. Output power.

Further, when the first portion 131 is represented by Al _x Ga _1-x N and the second portion 132 is represented by Al _y Ga _1-y N, then the value of x is less than the value of y, and the value of x may be 0.02 to 0.5, y The value can be from 0.2 to 0.7. Moreover, in a preferred embodiment, the first portion 131 is thinner than the second portion 132, and the first portion 131 may have a thickness of 1 nm to 4 nm, and the second portion 132 may have a thickness of 1.5 nm to 40 nm.

Briefly, by forming the barrier layer 13 into a groove as shown in Fig. 1, and making the first portion 131 have a molar fraction of Al lower than that of the second portion 132, it will be substantially large. Improving the Normally-On problem of conventional high electron mobility transistors makes the high electron mobility transistor 1 of the present invention more convenient and accurate as a circuit operation component.

Although the concept of the method for manufacturing a high electron mobility transistor of the present invention has been simultaneously described in the foregoing description of the high electron mobility transistor of the present invention, for the sake of clarity, the flow chart of the steps is further illustrated below. To explain in detail.

Please refer to FIG. 2, which is a flow chart of the steps of the method for manufacturing a high electron mobility transistor of the present invention. As shown, the method of manufacturing a high electron mobility transistor of the present invention may comprise the step of providing a substrate in step S1.

In step S2, a channel layer is formed on the substrate.

In step S3, a barrier layer is formed on the channel layer.

In step S4, a source is formed on the barrier layer, and an ohmic contact is formed between the source and the channel layer.

In step S5, a drain is formed on the barrier layer, and an ohmic contact is formed between the drain and the channel layer.

In step S6, a gate is formed on the barrier layer to form a Schottky contact, wherein the gate is located between the source and the drain.

Wherein the barrier layer comprises a first portion under the gate and a second portion under the source and the drain and adjacent to the first portion, the first portion being formed of Al _x Ga _1-x N and having a first thickness, The second portion is formed of Al _y Ga _1-y N and has a second thickness. And wherein the first thickness is less than the second thickness, and the x value is less than the y value.

In summary, the main spirit of the present invention is that the barrier layer 13 is formed into a groove as shown in FIG. 1 such that the Mo portion of the first portion 131 having Al is smaller than the Al portion of the second portion 132. rate. Thereby, the Normally-On problem of the conventional high electron mobility transistor is improved, and the high electron mobility transistor 1 of the present invention can be more convenient and accurate as the circuit operation component.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

1‧‧‧High Electron Mobility Transistor

11‧‧‧Substrate

12‧‧‧Channel layer

13‧‧‧ obstacle layer

131‧‧‧Part 1

132‧‧‧Part II

14‧‧‧ source

15‧‧‧汲polar

16‧‧‧ gate

Claims (8)

A high electron mobility transistor comprising: a substrate: a channel layer formed on the substrate; a barrier layer formed on the channel layer; and a source formed on the barrier layer An ohmic contact is formed between the source and the channel layer; a drain is formed on the barrier layer, the drain electrode forms an ohmic contact with the channel layer; and a gate is formed on the barrier layer Forming a Schottky contact, wherein the gate is between the source and the drain; wherein the barrier layer comprises a first portion below the gate and under the source and the drain a second portion adjacent to the first portion, the first portion being formed of Al _x Ga _1-x N and having a first thickness, the second portion being formed of Al _y Ga _1-y N and having a first portion The thickness is less than the second thickness, and the value of x is less than the value of y such that the molar fraction of Al of the first portion is less than the molar fraction of Al of the second portion. The high electron mobility transistor according to claim 1, wherein the channel layer is formed of GaN. The high electron mobility transistor according to claim 1, wherein the value of x is between 0.02 and 0.5, and the value of y is between 0.2 and 0.7. The high electron mobility transistor according to claim 1, wherein the first thickness is between 1 nm and 4 nm, and the second thickness is between 1.5 nm and 40 nm. A method for manufacturing a high electron mobility transistor, comprising the steps of: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; forming a source on the barrier layer Forming an ohmic contact between the source and the channel layer; forming a drain on the barrier layer, forming an ohmic contact between the drain and the channel layer; and forming a gate on the barrier layer to form a Schottky contact, wherein the gate is between the source and the drain; wherein the barrier layer includes a first portion below the gate and is located below the source and the drain and with the first portion Adjacent one of the second portions, the first portion is formed of Al _x Ga _1-x N and has a first thickness, the second portion is formed of Al _y Ga _1-y N and has a second thickness; The first thickness is less than the second thickness, and the x value is less than the y value such that the Mo content of Al of the first portion is less than the Mo content of Al of the second portion. The method of manufacturing a high electron mobility transistor according to claim 5, wherein the channel layer is formed of GaN. The method for producing a high electron mobility transistor according to claim 5, wherein the value of x is between 0.02 and 0.5, and the value of y is between 0.2 and 0.7. The method of manufacturing a high electron mobility transistor according to claim 5, wherein the first thickness is between 1 nm and 4 nm, and the second thickness is between 1.5 nm and 40 nm.