TWI503927B - Device including memory array and method thereof - Google Patents

Description

Device including memory array and method thereof

This invention relates to electronic devices and, more particularly, to electronic devices having non-volatile memory.

A conventional memory array includes a plurality of individual memory cells. The memory unit can be programmed for the desired logic or storage state. When programming, the cells of the memory array will have a programmed state that indicates a high or low signal (i.e., on or off) during a read operation. Memory with cells (keeping their programmed state when power is off) is called non-volatile memory.

Non-volatile memory tissue into one or more non-volatile memory (NVM) arrays organized by rows and columns. Typically, the rows of the NVM array are referred to along the word lines, and the columns of the array are referred to along the bit lines, although the definition is arbitrary depending on the physical orientation of the array. The method of reading a single memory cell from an NVM array can be changed and the NVM architecture can be determined. There are two commonly used NVM architectures: the NOR architecture and the NAND architecture. In the NVM architecture, word lines can change the on/off state of all memory cells on a particular row. The information of a particular memory cell of the NVM array can be determined by measuring the current in the column (bit line) containing the memory cell, the column being referred to as the selected column, while adjusting the row containing the memory cell. The word line potential, which is referred to as the selected row, is adjusted relative to the word line potential of the other rows, which are referred to as unselected rows. In this way the conductivity of a particular cell can be determined by the current flowing into or out of the selected column.

For a NOR architecture, memory cells within a given column are connected in parallel such that current can flow through or out of the column if any of the memory cells in a given column are conducting. For the NOR architecture, the word line potential of the unselected rows is adjusted to limit the flow of current through the memory cells connected to the unselected rows, such as current flowing into or out of the column, regardless of their state, to allow for selection in the row. The state of the memory unit is detected.

For NAND memory architectures, memory cells within a given column are connected in series. Therefore, in order for the current to conduct through the column, all memory cells within a given column must be electrically conductive. In order to check the information held in a particular memory cell of the NAND architecture, the word lines of the unselected rows are set to such values that the memory cells of the unselected rows are sufficiently conductive for some particular selected line words. The line potential determines the conductivity of the memory cells in the selected row.

An electronic device including a non-volatile memory (NVM) array is disclosed.

The invention is illustrated by way of example and not limitation.

Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to improve the understanding of the embodiments of the invention.

In one embodiment, the NVM array includes a first gate structure that covers a first body region of the substrate at a location where the first memory cell of the NVM array is formed, and a location where the second memory cell of the NVM array is formed A second gate structure covering the second body region of the substrate. The first body region is between the first gate structure and the conductive region. The second body region is between the second gate structure and the conductive region. The conductive region is a bit line portion of the NVM array electrically coupled to the first drain structure of the first gate structure and the second drain structure associated with the second gate structure. In accordance with another embodiment, an NVM array includes first and second memory cells. The drain structure of the first memory cell and the drain structure of the second memory cell electrically connect the bit line portion, and the body of the first memory cell physically isolates the body of the second memory cell. Various embodiments of an electronic device including an NVM array will be better understood with reference to Figures 1-25.

The term "main surface" is intended to mean the surface of a substrate from which memory cells within the memory array are subsequently formed. The major surface can be the initial surface of the substrate prior to forming any structure, or can be a surface that forms a channel or other permanent structure within the memory array. For example, the memory array can be formed at least partially within the epitaxial layer overlying the substrate, and the electronic components within the peripheral region (outside the memory array) can be formed from the substrate. In this example, the major surface refers to the upper surface of the epitaxial layer rather than the initial surface of the substrate.

The term "stack" is intended to mean a plurality of layers or a plurality of at least one layer and at least one structure, wherein the plurality of layers or layers and structures provide an electronic function. For example, the non-volatile memory stack can include a layer for forming at least a portion of the non-volatile memory unit.

As used herein, the terms "including," "comprising," "including," "containing," "having," "having," or any variant thereof are intended to cover a non-exclusive inclusion. For example, a process, a method, an article, or a device that comprises a series of elements is not necessarily limited to those elements, but may include other elements not specifically listed or inherent to such processes, methods, articles, or devices. Moreover, unless explicitly stated to be relatively low, "or" refers to the inclusion or rather than exclusive or. For example, condition A or B satisfies any of the following conditions: A is true (or exists) and B is false (or does not exist), A is false (or non-existent) and B is true (or exists) and A And B are both true (or exist).

In addition, for the sake of clarity and the general meaning of the scope of the embodiments described herein, the use of "a" or "an" is used to describe one or more of the article. Therefore, whenever the word "a" or "an" is used, the description should be understood to include one or at least one, and the singular also includes the plural unless the

Unless otherwise defined, all technical and scientific terms used herein have the same meaning meaning All publications, patent applications, patents, or other references mentioned herein are hereby incorporated by reference. In the event of a conflict, this specification containing the definition will be resolved. In addition, the materials, methods, and examples are illustrative only and not intended to be limiting.

Other features and advantages of the invention will be apparent from the description and appended claims. Moreover, many details regarding particular materials, processing operations, and circuits are conventional and are available in textbooks or other sources in the field of semiconductor and microelectronics, to the extent not described herein.

Figure 1 includes an illustration of a cross-sectional view of a portion of a workpiece forming an integrated circuit. The integrated circuit can be a stand-alone memory, a microprocessor, or another integrated circuit including memory. In one embodiment, the NVM array is formed as at least a portion of an integrated circuit, including a portion of the NVM array at the location shown in FIG.

FIG. 1 shows a substrate 10 and a protective layer 14. Substrate 10 may comprise a single crystal semiconductor wafer, a semiconductor-on-insulator (SOI) wafer, a flat panel display (eg, a germanium layer over a glass sheet), or other substrate used to form an electronic device. In the particular embodiment of FIG. 1, substrate 10 includes a single crystal semiconductor wafer and is shown to include layer 11, conductive layer 12 of cover layer 11, and layer 13 overlying conductive layer 12.

In accordance with certain embodiments disclosed herein, layer 11 is a p-doped layer. Those skilled in the art will recognize that layer 11 may also be an n-doped layer, or may be an insulator layer, such as having an SOI substrate, relative to other embodiments.

Conductive layer 12 is a conductive layer that can include a metal or highly doped portion of substrate 10 from which a plurality of bit line portions of the NVM array are formed. In accordance with certain embodiments disclosed herein, the conductive layer 12 is doped with an n-type dopant, ie, the layer 12 is n-doped with a sufficient concentration to electrically connect. For example, the n-doped layer 12 can have a doping concentration greater than about 1E17 atoms/cm**3.

Layer 13 is a doped layer of a particular conductivity type. In accordance with certain embodiments disclosed herein, layer 13 has a conductivity type opposite conductive layer 12, and thus is a p-doped layer in which various body regions of the memory cells of the NVM array are formed. The typical thickness of the p-doped layer 13 is in the range of 0.5 um to 5 um.

A protective layer 14 has been formed over the substrate 10 to facilitate subsequent formation of features integrated with the substrate 10. For example, the protective layer 14 may be an etch stop layer, a polish stop layer, etc., and a combination of various techniques for forming an NVM array, and may remain over the surrounding area, for example, an integrated circuit in which no NVM array is formed in the integrated circuit. Until the user formation of the NVM array is substantially completed. The uppermost surface of the substrate 10 is the major surface 15, with the p-doped layer 13 contacting the protective layer 14. The protective layer 14 can be a laminate that can include oxides, nitrides, and the like, as well as combinations including nitrogen oxides. Although not shown in FIG. 1, various other features, such as field isolation regions, may reside in the surrounding portion of the workpiece of FIG.

A patterned resist layer (not shown) is formed over the workpiece, as shown in FIG. 2, which defines a location at which a channel will be formed within the substrate 10. 2 includes an illustration of a top view of a trench of a portion of the workpiece that is unprotected by the patterned resist layer, the layer 13 and the conductive layer 12 being removed by conventional techniques to form the exposed layer 11. The top view of the channel illustrated relative to the workpiece illustrated in FIG. 2 includes horizontal channels 26-28, and channels 21-23. A plurality of regions 5 represent locations protected by the patterned resist layer, wherein the protective layer 14, the p-doped layer 13, and portions of the conductive layer 12 remain after forming the vertical and horizontal channels. Each region 5 represents the location of a portion of an NVM array called an NVM array segment that will include a plurality of memory cells. Each memory cell can have a channel width defined by the horizontal dimension of region 5, as further illustrated herein. Additionally, each NVM segment will have a single bit line portion formed by conductive layer 12. The NVM segments in the same column will be connected to the common bit line with the appropriate active and passive circuits when the NVM array is completed.

Techniques for forming channels 21-23, and 26-27 may include time-division anisotropic etching to produce substantially vertical channel walls as shown in Figures 3 and 4, and Figure 3 illustrates section lines 3-3. 2 is a cross-sectional view of the workpiece of FIG. 2, and FIG. 4 illustrates a cross-sectional view of the workpiece of FIG. 2 of section line 4-4. As shown in FIG. 3, the channels 21-23 are spaced apart from one another, extending from the major surface 15 and defining the sidewalls of the region 5. The channels 21-23 extend through the n-doped layer 12 to a substantially uniform depth to form adjacent regions between the isolated channels, wherein a non-volatile memory cell column will subsequently be formed. In one embodiment, the bottom of each channel 21-23 is defined by a p-doped layer 11. If an SOI substrate is used, the bottom of each channel 21-23 will be defined by an insulator layer located below the n-doped layer 12 and adjacent.

The region 5 forming the left side of the channel 21 illustrated in FIG. 3 includes a protective region 141 formed of the protective layer 14, a p-doped region 131 formed of the layer 13, and a conductive region 121 formed of the layer 12. The region 5 formed between the channel 21 and the channel 22 includes a protective region 142 formed of the protective layer 14, a p-doped region 132 formed of the layer 13, and a conductive region 122 formed of the layer 12. The region 5 formed between the channel 21 and the channel 22 includes a protective region 142 formed of the protective layer 14, a p-doped region 132 formed of the layer 13, and a conductive region 122 formed of the layer 12.

The conductive regions 121-123 of the workpiece are physically isolated from each other along the lateral dimension by the formation of vertical and horizontal channels, and a bit line portion is formed within the corresponding region 5. Additionally, the illustrated conductive regions are electrically insulated from each other. For example, conductive region 122 is electrically insulated from conductive region 123 by a layer 11 comprising channel 22 and by layer 11 having an opposite conductivity type (p-doped) to conductive regions 122 and 123 (n-doped).

Insulator regions are formed in the channels 21-23 of the workpiece to form trench isolation regions 211, 221 and 231, respectively, as shown in FIG. The insulator region may be an insulator filling the channel or may be an insulator that is lined up with the channel and filled with a non-insulator such as a polysilicon. Conventional planarization techniques can be used to provide a substantially flat upper surface that includes protective regions 141-143A.

As shown in FIG. 6, the p-doped regions 131-133 are exposed using conventional techniques to remove the material of the protective regions 141-143 of the workpiece, and the p-doped regions are cleaned using conventional techniques prior to forming the upper dielectric regions 341-343. 131-133. Dielectric regions 341-343 may include oxide and will be used to form a gate structure gate dielectric portion for each memory cell of the NVM array.

The charge storage region is formed over the dielectric regions 341-343 of the workpiece, as shown by the floating gate regions 251-253 of FIG. In other embodiments, the charge storage region can include nitrides, nanocrystals, and the like, and combinations thereof. According to a particular embodiment, the floating gate regions 251-253 may be polysilicon containing dopants and etched using conventional techniques, or polysilicon subsequently deposited by a doping implantation step. In the illustrated embodiment of Figure 7, the floating gate regions 251-253 have been formed in one direction along the vertical length of the formed array team. Dielectric regions 351-353 have been formed over floating gate regions 251-253. Figure 8 illustrates a cross-sectional view of the workpiece of Figure 7 along the length of the floating gate 252 of section line 4-4 of Figure 2. Those skilled in the art will appreciate that in alternative embodiments, the dielectric layer and charge storage layer may be formed over layer 13 of FIG. 1 prior to forming protective layer 14, thereby forming channels 21-22 (FIG. 3). It helps to form floating gate regions 251-253, and dielectric regions 351-353 are formed after channels 21-22 are formed.

Conductive layer 260 and a patterned layer comprising patterned regions 291-295, such as a photoresist layer, are formed over the workpiece, as shown in Figures 9-11. Figure 9 includes a top view of the workpiece illustrating the spatial relationship between the patterned regions 291-295 of the patterned layer and various other components, respectively located at dielectric regions 351-353 above the floating gates 251-253, The dielectric regions 351-353 have no covered trench isolation regions 211, 221 and 231 (channel isolation regions 211-231). Note that the portions of the dielectric regions 351-353 and the trench isolation regions 211-231 below the patterned regions 291-295 are indicated by dashed lines. Conductive regions will be formed from conductive layer 260 using patterned regions 291-295 as word lines and associated control gates. The word lines formed by conductive layer 260 will define the memory cell rows of the formed NVM array. Those skilled in the art realize that the conductive layer 260 shown in FIG. 10 is not shown in FIG. 9, and the conductive layer 260 extends across the entire workpiece between the patterned regions 291-295 and the dielectric regions 351-352 of FIG. .

10 is a cross-sectional view of the workpiece of FIG. 9 with section lines 10-10, and illustrates a patterned region 292 of the patterned layer over conductive layer 260. Figure 11 illustrates a cross-sectional view of the position indicated by section line 11-11 of the workpiece of Figure 9 and includes patterned regions 291-293 of the patterned layer. In one embodiment, conductive layer 260 is a doped polysilicon and may have a dopant of at least about 1E19 atoms/cm**3. In another embodiment, conductive layer 260 comprises a metal.

The conductive regions are formed by removing portions of the conductive layer 260 that are not protected by the patterned layer including the patterned regions 291-293. Each of the conductive regions forms a word line and a plurality of control gates formed for the memory cells. For example, FIG. 12 includes a top view of the workpiece of FIGS. 9-11 and illustrates conductive regions 261-265 corresponding to word lines formed by conductive layer 260. In addition, FIG. 12 illustrates the gate structures 311-313, 321-323, 331-333, 341-343, and 351-353 formed by removing portions of the dielectric regions 351-353, and the patterned regions 291-295 are not provided. The position of the protected floating gate regions 251-252. The active area corresponding to the portion of region 5 (FIG. 2) is exposed by removing portions of dielectric regions 341-343 that are not protected by patterned regions 291-295.

Figure 13 illustrates the removal of conductive layer 260, dielectric regions 351-353, floating gate regions 251-252, and protective component 291- since gate structures 312, 322, and 332 (gate structures 312-332) have been formed. 295 is a cross-sectional view of the workpiece of FIG. 11 after the unprotected dielectric regions 341-343. The gate structure 312 includes a gate dielectric 3421 formed by a dielectric region 342, a floating gate 2521 formed by a floating gate region 252, an inter-gate dielectric 3521 formed by a dielectric region 352, and a conductive region 261. The portion of the control gate 2612. The gate structure 322 includes a gate dielectric 3422 formed by a dielectric region 342, a floating gate 2522 formed by a floating gate region 252, an inter-gate dielectric 3522 formed by a dielectric region 352, and a conductive region 262. Part of the control gate 2622. The gate structure 332 includes a gate dielectric 3423 formed by a dielectric region 342, a floating gate 2523 formed by a floating gate region 252, an inter-gate dielectric 3523 formed by a dielectric region 352, and a conductive region 263. Part of the control gate 2632.

As noted above, each of the conductive regions 261-265 implements a corresponding word line and a plurality of conductive gates for the rows of memory cells. For example, FIG. 14 illustrates a cross-sectional view of conductive region 262 of the workpiece of FIG. 12 corresponding to the cross-sectional view of FIG. 10, wherein conductive region 262 forms a word line for conductive gate 2621 of gate structure 321 for gate structure 322 A conductive gate 2622 and a conductive gate 2623 for the gate structure 323.

Referring to FIG. 15, the patterned regions 291-293 have been removed, and the protective layer 411, which may be a resistive material, forms an opening exposing a location where a drain structure and a connecting line are to be formed between the drain structure and the conductive region 122. In accordance with this embodiment, the exposed locations are implanted with n-type dopants to form n-doped regions 1321 and n-doped regions 1322. N-doped regions 1321 and 1322 are formed to extend through p-doped region 132 to conductive region 122 and serve as a common drain of adjacent memory cells, and electrically connect their corresponding common drains as buried interconnects as A conductive region 122 in which the buried bit line portion operates. Since the n-doped region 1321 is formed, the p-type doped region 132 of the workpiece of FIG. 13 is divided into two physically separated, ie, mutually separated, p-type body regions at the workpiece of FIG. For example, as shown in FIG. 15, body regions 1328 and 1329 have been formed from p-doped regions 132 and are separated from one another by forming n-doped regions 1321.

The N-doped region 1321 includes a common drain structure associated with the gate structure 312 and the gate structure 322, and a buried interconnect region electrically connecting the common drain structure to the conductive region 122. For example, the doped region 1321 is electrically connected to the conductive region 122 by two regions having the same conductivity type (n-type). Conversely, the level of the body region 1328 at the body region is not electrically connected to the body region 1329 because the conductivity type of the doped region 1321 between the body region 1329 and the body region 1329 is opposite to the conductivity type of the body regions 1328 and 1329. The doped region 1321 may have a range of about 1E15-1E21 atoms/cm**3, such as a doping concentration in the range of about 1E18-1E19 atoms/cm**3. Doped region 1322 includes a common drain structure associated with gate structure 332 and an adjacent gate structure (not shown n) and a buried interconnect region electrically connecting the shared drain structure to conductive region 122.

The protective layer 411 is removed from the workpiece, as shown in FIG. 16, and another protective layer, such as a photoresist layer, is formed and patterned over the workpiece as shown by the patterned layer 412. The patterned layer 412 exposes a location where a source region and a connection line are to be formed between the source region and its corresponding body region. The exposed portion of the patterned layer 412 is implanted with an n-type dopant to form an n-doped region such as the n-doped region 1323 and the n-doped region 1324 of FIG. 17, which may form a lightly doped drain ( LDD) Region or source region. In the embodiment shown in FIG. 16, n-doped regions 1323 and 1324 are LDD regions and may have approximately 1E15-1E19 atoms/cm**3 when forming a doped gate structure, such as approximately 1E18 atoms/cm. **3 dopant concentration.

After the doped regions 1323 and 1324 are formed, the mask layer 412 is removed, and the source regions can be formed at locations defined by the mask or spacer. FIG. 17 illustrates a particular embodiment after forming sidewall spacers 430 formed by adjacent sidewalls of gate structures 312-332. In the embodiment illustrated in FIG. 17, the material from which sidewall spacers 430 are formed includes nitrides or other materials that facilitate selective etching of the interlayer dielectrics discussed further herein. The thickness of the sidewall spacers 430 in the lateral dimension may be selected based on the spacing between the gate structures 312 and the gate structures 322. For example, the thickness of the layer used to form the sidewall spacers 430 is selected such that after formation the sidewall spacers 430 completely cover the common drain structures 1321 and 1322, while only partially covering the locations where the source regions are formed. Thus, the thickness of the layer used to form sidewall spacers 430 is at least half the distance between gate structure 312 and gate structure 322. As shown in Figure 17, the spacing between the gate structure 322 and the gate structure 332 has been selected to leave an opening between the sidewall spacers 430 on the source side of the gate structure, while the gate structure is There are no openings between the sidewall spacers on the pole side.

The source region and the germanide region are formed at exposed regions of the workpiece between the gate structure 322 and the gate structure 332, such as source region 1325 and source region 1326, and germanide region 441 and germanide region. 442 is shown. Forming region 1235 obtains LDD region 13232 associated with gate structure 312, LDD region 13241 associated with gate structure 322, and LDD region 13242 associated with gate structure 332. The dopant concentration of source regions 1325 and 1326 is typically in the range of about 1E18 atoms/cm**3 to 2E19 atoms/cm**3, such as about 1E19 atoms/cm**3. The telluride regions 441 and 442 are composed of a material capable of reacting with the pick-up, such as Ti, Ta, Co, W, Mo, Pt.

Connection regions 498 and 499 electrically connecting the source regions of the respective memory cells to their body regions are formed at the workpiece as shown in FIG. Connection regions 498 and 499 can be formed by implanting a p-type dopant at a location that electrically connects body region 1328 to germanide region 441 and electrically connects body region 1329 to the source region of germanide region 442. The locations at which the connection regions 498 and 499 are formed may be defined by a sacrificial patterned layer, such as a resistive mask (not shown), or by forming additional sidewall spacers that abut sidewall spacers 430 as shown by sidewall spacers 431. After sidewall spacers 431 are formed, connection regions 498 and 499 are formed by implanting a sufficient amount of p-type dopant to compensate for the n-type dopant concentration of the source and LDD regions, thereby forming approximately 1E18 The range of atoms/cm**3 to 9E19 atoms/cm**3 is, for example, the doping concentration of connection regions 498 and 499 of about 7E18/cm**3. Connection region 498 obtains source regions 13251 (not shown) and 13252 formed by doped regions 1325. Connection region 499 obtains source regions 13261 (not shown) and 13262 formed by doped regions 1326. Connection regions 498 and 499 having a p-type conductivity type are aligned with the sidewall spacers 431 and electrically connect the source regions of the respective memory cells to their body regions.

Figure 20 illustrates a portion of the workpiece of Figure 19 from a top view, including conductive regions 262 and 263 of gate structures 322 and 323 and portions of corresponding sidewall spacers and locations of the connection regions.

Over the workpiece formed by the interlayer dielectric layer, such as patterned layer 450 of FIG. 21, defines and isolates the location at which the workpiece of FIG. 19 is to form the contact of the source region of the gate structure. The patterned layer 450 can include an insulating material. The material of patterned layer 450 and sidewall 431 is selected to selectively etch the patterned layer without significantly affecting sidewall 431. This allows the contact openings 451 and 452 to terminate on the sidewall structure 431, allowing subsequently formed contacts that electrically connect the source side germanide over the metal interconnect structure, which is comprised of the sidewall structure 431 The space between the limits. For example, referring to FIG. 21, the patterned layer 450 terminates in sidewall structure 431 between gate structures 322 and 332 to create a sidewall defined by sidewalls of both sidewall spacers 431 and patterned layer 450 over the germanide region 442. Opening 452.

Those skilled in the art will appreciate that a variety of different methods can be used to form the connection region between the source and the body. For example, after the first source doping of FIG. 16, a source side spacer can be formed that defines a location where the bulk connection line is to be doped between the two memory cells. After the implant body connection line is diffused, the source side spacer is etched back to define the location at which the second source implant will occur. In this manner, the body link implant is aligned with the second source implant and the source side spacer, if used.

Figure 22 illustrates the workpiece after the contacts 453 and 454 are formed in the openings 451 and 452 (Figure 18) using conventional techniques. Wire 460 is formed over and in electrical contact with contacts 453 and 454. In one embodiment, contacts 453 and 454 are formed prior to wire 460, and a conductive layer (not shown) is formed over patterned layer 450 and then substantially fills the contact opening there. In another embodiment, wires 460 and contacts 453 and 454 are formed simultaneously as part of the dual embedding process.

In one embodiment (not shown), additional insulating and conductive layers can be formed and patterned to form additional interconnect layers. After the final interconnect layer has been formed, a passivation layer 470 is formed over the substrate 10, including the NVM array and peripheral regions, as shown in FIG.

Figure 24 illustrates a schematic diagram of an NVM array of memory cells 321-323, 331-333, 341-343, and 351-353 that include portions defining four rows and three columns of NVM arrays. Memory cells, such as memory cells 322 and 332, sharing a common body region are indicated by dashed boxes. Each memory cell has a control gate electrode connected to one of word lines 262-265, a drain electrode connected to one of conductive regions 121-123 (bit line portion), and a source connected to source line 461-463 A source electrode/body. Conductive regions 121-123 are shown as dashed lines to indicate their burial characteristics as described above. Each of the conductive regions 121-123 is connected to a corresponding bit line 521-523. Only one electrical connection is required between each of the conductive regions 121-123 and its corresponding bit line. Those skilled in the art will appreciate that each of the memory cells connected to conductive region 121 shown in FIG. 24 is associated with a certain region 5 (FIG. 2), and each of the other regions 5 in the same column will also have a connection to bit line 521. The bit line portion. Each of the memory cells connected to conductive region 122 shown in FIG. 24 is associated with a single region 5 (FIG. 2), and each of the other regions 5 in the same column will also have a bit line portion connected to bit line 522. Each of the memory cells connected to the conductive region 123 shown in FIG. 24 is associated with a single region 5 (FIG. 2), and each of the other regions 5 in the same column will also have a bit line portion connected to the bit line 523.

Figure 25 includes a table with typical operating voltages for the memory cells shown in Figure 24. Those skilled in the art will appreciate that the operating voltages can vary from the listed values because they represent typical values. The values in the columns labeled Vcg 262 and Vcg 263 correspond to the voltages at word lines 262 and 263, respectively. The values in the columns labeled Vs461 and Vs462 correspond to the voltages at source lines 461 and 462. The values in the columns labeled Vd121 and Vd122 correspond to the voltages at bit lines 521 and 522. The row labeled "Erase 321/322 (FN/Vt1)" includes the operating voltage used to simultaneously erase the memory cells 321 and 322 to the low voltage threshold using Fowler-Nordheim tunneling. The row labeled "Pgm 321 (HCI/Vth)" includes the operating voltage used to program the memory cell 321 to the high voltage threshold using thermal carrier injection. The row labeled "Erase 321/322 (FN/Vth)" includes the operating voltage used to simultaneously erase the memory cells 321 and 322 to the high voltage threshold using Fowler-Nordheim tunneling. The row labeled "Pgm 321 (FN/Vtl)" includes the operating voltage used to program the memory cell 321 to the low voltage threshold using Fowler-Nordheim tunneling. The line labeled "Read 321-323" includes reading the operating voltages of all memory cells on a given line simultaneously. The electrical Vph is typically in the range of 12-20 volts. The voltage Vinh is typically in the range of 2-8 volts. The voltage Vread is typically in the range of 1-5 volts. In the row labeled "Pgm 321 (HCI/Vth)", the voltage Vd122 is used to source the source line box drain line of the memory cell programmed by the HCI to indicate the source and 保持 held at approximately the same voltage. Polar line. In the row labeled "Read 321-323", a voltage greater than Vs 461 is used to indicate that the drain line of the read row remains at a higher voltage than the source line.

Those skilled in the art will recognize that each source line can be driven to a different voltage during a program or erase operation to change the rate at which the voltage thresholds of the various memory cells are modified. Additionally, those skilled in the art will appreciate that the voltage drop along the bit line portion during the read operation does not significantly affect the read gap of the memory cell. In embodiments where the source/body regions of the memory cells of the array segments are electrically connected along a common source line segment in the memory array segment, this is advantageous especially if the common source segment experiences a voltage drop along its length. .

Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. Those skilled in the art will recognize that the aspects and embodiments are merely illustrative and not limiting of the scope of the invention.

In a first aspect, the forming of the electronic device can include providing a substrate including a conductive region. The processing can also include forming a first gate structure over the first body region at a location where the first memory cell of the non-volatile memory array is formed, wherein the first body region is in the first gate structure and the conductive region between. The method can also include forming a second gate structure over the second body region at a location where the second memory cell of the non-volatile memory array is formed, wherein the second body region is located at the second gate structure and the conductive region between. The process can further include forming a first drain structure over the conductive region and electrically connecting the conductive region, the first drain structure being associated with the first gate structure. The process can also include forming a second drain structure over the conductive region and electrically connecting the conductive region, the second drain structure being associated with the second gate structure.

In an embodiment of the first aspect, the first and second drain structures may comprise a common drain structure. In another embodiment of the first aspect, the first and second drain structures may be spaced apart from one another. In another embodiment of the first aspect, the conductive region, the first drain structure and the second drain structure may have a first conductivity type, and the first body region and the second body region may have opposite to the first conductivity type The second conductivity type. In another embodiment of the first aspect, the first regions of the first conductivity type may be electrically connected to each other to the first drain structure and the conductive region.

In another embodiment of the first aspect, the second body region can be physically isolated from the first body region, and the processing can further include forming a first source region over the wire region and electrically connected to the first body region, A first source region is associated with the first gate structure and is formed over the conductive region and electrically coupled to the second source region of the second body region, the second source region being associated with the second gate structure. In further embodiments of certain embodiments, the first body region and the second body region may have a second conductivity type and abut the conductive region, and the second conductivity type may be opposite the first conductivity type.

In another embodiment of the first aspect, the conductive region may be the first conductive region, and the substrate may further include a second conductive region separated from the first conductive region by the insulator region when viewed from a top view, and the process further A third gate structure may be formed over the third body region at a third memory cell location forming the non-volatile memory array, wherein the third body region may be located between the third gate structure and the second conductive region between. The processing of this particular embodiment can also include forming a fourth gate structure over the fourth body region at a location where the fourth memory cell of the non-volatile memory array is formed, wherein the fourth body region is at the fourth gate Between the structure and the second conductive region. The processing of this particular embodiment can also include forming a third drain structure over the second conductive region and electrically connected to the second conductive region, the third drain structure being associated with the third gate structure. The processing of this particular embodiment further includes forming a fourth drain structure over the second conductive region and electrically connected to the second conductive region, the fourth drain structure being associated with the fourth gate structure. A further embodiment of this particular embodiment can include a first conductive region and a second conductive region having a first conductivity type, and a second conductivity type of the substrate including the first conductive region and the second conductive region and adjacent thereto In one region, the first conductivity type is opposite to the second conductivity type. Embodiments of this additional embodiment can include an insulator region extending from a major surface of the substrate and abutting the first region.

In a second aspect, the processing of forming an electronic device can include forming a first memory cell including a body region and a drain structure electrically connected to a bit line portion of the non-volatile memory array. The processing can also include forming a second memory unit including a body region physically separated from the body region of the first memory unit, and a drain structure electrically connected to the bit line portion.

In an embodiment of the second aspect, the body region of the first memory cell has a first conductivity type, and forming the first memory cell may further include forming a source region electrically connected to the body region of the first memory cell, Wherein the source region has a second conductivity type opposite to the first conductivity type.

In another embodiment of the second aspect, the body region of the first memory unit and the body region of the second memory unit may have a first conductivity type. The present embodiment of the second aspect may further include forming a region of the second conductivity type located between and adjacent to the body region of the first memory unit and the body region of the second memory unit from a top view.

Another embodiment of the second aspect can include forming a third memory unit including a body region of the second memory cell and a drain structure electrically connecting the bit line portions.

Another embodiment of the second aspect can include providing a substrate including a bit line portion prior to forming the first memory cell.

In another embodiment of the second aspect, the first memory cell can include a gate structure, wherein the body region of the first memory cell is between the gate structure and the bit line portion.

In another embodiment of the second aspect, the first memory cell includes a gate structure, wherein the body region of the first memory cell is between the gate structure and the bit line portion.

In another embodiment of the second aspect, the drain structure of the first memory cell and the second memory cell can be included in a common drain structure.

In a third aspect, an electronic device can include a substrate including a conductive region below a major surface of the substrate. The electronic device can also include a first memory cell of the non-volatile memory array including a body region, a gate structure, a source region, and a drain structure, the gate structure including a gate dielectric and a charge storage region, wherein the drain The structure is over the conductive region and is electrically connected to the conductive region, and the body region is between the gate structure and the conductive region. The electronic device can also include a second memory cell of the non-volatile memory array, including a body region, a gate structure, a source region, and a drain structure, the gate structure including a gate dielectric and a charge storage region, wherein The pole structure is located above the conductive region and is electrically connected to the conductive region, and the body region is between the gate structure and the conductive region.

Embodiments of the third aspect may further include an insulating region surrounding the body region of the first memory unit that physically isolates the body region of the first memory cell from the body region of the second memory cell, wherein the insulating region includes a connection region And electrically connecting the drain structure of the first memory cell and the drain structure of the second memory cell to the conductive region.

Another embodiment of the third aspect can include a shared drain structure including a drain structure of the first memory cell and a drain structure of the second memory cell.

A further embodiment of the third aspect may include a source region of the first memory cell and a body region of the first memory cell electrically connected to each other, a source region of the second memory cell, and a body region of the second memory cell Electrically connected to each other, the body region of the first memory unit is physically isolated from the body region of the second memory unit. The particular embodiment of the third aspect may further include a body region of the first memory cell above the conductive region and adjacent to the conductive region, a body region of the second memory cell above the conductive region and adjacent to the conductive region, first and second The body region of the memory cell has a first conductivity type and the conductive region has a second conductivity type opposite the first conductivity type.

In a fourth aspect, an electronic device can include a first memory cell of a non-volatile memory array, including a body region, a gate structure, a source region, and a drain structure. The electronic device can also include a second memory unit of the non-volatile memory array, including a body region, a gate structure, a source region, and a drain structure that are physically separated from the body region of the first memory unit. The electronic device can also include a bit line portion electrically connected to the drain structure of the first memory cell and the drain structure of the second memory cell.

In an embodiment of the fourth aspect, the source region of the first memory unit and the body region of the first memory unit may be electrically connected, and the source region of the second memory unit and the body of the second memory unit The areas can be electrically connected to each other.

In a further embodiment of the fourth aspect, the electronic device further includes a connection region electrically connected to the drain structure of the first memory cell and the first conductivity type of the drain structure of the second memory cell, the first memory cell The body region and the body region of the second memory unit have a second conductivity type opposite to the first conductivity type, the body region of the first memory unit abuts the connection region, and the body region of the second memory unit abuts the connection region.

A number of details have been described with respect to the NVM array, its memory cells, bit lines and word lines. After reading this description, those skilled in the art will appreciate that the row and column orientations can be reversed. The electrical connections along one or more rows between the memory cells and their associated bit lines, gate lines, or any combination thereof can be changed into one or more columns. Similarly, the electrical connections along one or more columns between the memory cells and their associated bit lines, gate lines, or any combination thereof can be changed to one or more rows. Additionally, it should be understood that an NVM array of m-channel based memory cells can be implemented using the opposite orientation types of the various regions and layers described above.

The embodiments described herein are advantageous in forming an NVM array or a portion thereof. Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. Those skilled in the art will recognize that the aspects and embodiments are merely illustrative and not limiting of the scope of the invention.

Note that not all activities described in the general description or examples are necessary, a portion of a particular activity may not be required, and one or more additional activities may be performed in addition to those described. In addition, the order in which the activities are listed does not have to be in the order in which they are performed. After reading this specification, those skilled in the art will determine those activities that are available for their particular needs or desires. For example, referring to FIG. 13, those skilled in the art realize that although dielectric regions 341-343 have been removed, in other embodiments, dielectric regions 341-343 may also be used as etch stop layers and remain in FIG. Come down.

Any one or more of the benefits, one or more other advantages, one or more aspects of solving one or more problems, or a combination thereof, have been described with reference to one or more specific embodiments. However, the benefit(s), the advantages(s), the solution(s) of the problem(s), or any component(s) that may bring benefits, advantages or solutions or become more apparent are not It should be understood that it is critical, or key features or elements of any or all of the claims.

The above-disclosed subject matter is intended to be illustrative, and not restrictive. The scope of the invention is to be determined by the appended claims and the claims

5. . . region

10. . . Substrate

11. . . Cover layer

12. . . Conductive layer

13. . . P-doped layer

14. . . The protective layer

15. . . Main surface

twenty one. . . Channel

twenty two. . . Channel

twenty three. . . Channel

26. . . Channel

27. . . Channel

28. . . Channel

122. . . Conductive area

121. . . Conductive area

122. . . Conductive area

123. . . Conductive area

131. . . P-doped region

132. . . P-doped region

133. . . P-doped region

141. . . Protective area

142. . . Protective area

143. . . Protective area

211. . . Channel isolation region

221. . . Channel isolation region

231. . . Channel isolation region

251. . . Floating gate

252. . . Floating gate

253. . . Floating gate

260. . . Conductive layer

261. . . Conductive area

262. . . Conductive area

263. . . Conductive area

264. . . Conductive area

265. . . Conductive area

291. . . Patterned area

292. . . Patterned area

293. . . Patterned area

294. . . Patterned area

295. . . Patterned area

311. . . Gate structure

312. . . Gate structure

313. . . Gate structure

321. . . Gate structure

322. . . Gate structure

323. . . Gate structure

331. . . Gate structure

332. . . Gate structure

333. . . Gate structure

341. . . Dielectric area

342. . . Dielectric area

343. . . Dielectric area

351. . . Dielectric area

352. . . Dielectric area

353. . . Dielectric area

411. . . The protective layer

412. . . Patterned layer

430. . . Side spacer

431. . . Side spacer

441. . . Telluride region

442. . . Telluride region

450. . . Patterned layer

451. . . Contact opening

452. . . Contact opening

453. . . Contact

454. . . Contact

460. . . wire

461. . . Source line

462. . . Source line

463. . . Source line

470. . . Passivation layer

498. . . Connection area

499. . . Connection area

521. . . Bit line

522. . . Bit line

523. . . Bit line

1321. . . N-doped region

1322. . . N-doped region

1323. . . N-doped region

1324. . . N-doped region

1325. . . Source area

1326. . . Source area

1328. . . Body area

1329. . . Body area

2521. . . Floating gate

2522. . . Floating gate

2523. . . Floating gate

2612. . . Control gate

2621. . . Conductive gate

2622. . . Control gate

2623. . . Conductive gate

2632. . . Control gate

3421. . . Gate dielectric

3422. . . Gate dielectric

3423. . . Gate dielectric

3521. . . Dielectric between gates

3522. . . Dielectric between gates

3523. . . Dielectric between gates

13232. . . LDD area

13241. . . LDD area

13242. . . LDD area

13252. . . Source area

13261. . . Source area

13262. . . Source area

Figure 1 includes an illustration of a workpiece after forming a protective layer in accordance with a particular embodiment of the present invention.

2 through 4 include illustrations of top and cross-sectional views of the workpiece of FIG. 1 after forming a channel, in accordance with a particular embodiment of the present invention.

Figure 5 includes an illustration of a cross-sectional view of the workpiece of Figure 3 after it has been filled with an insulating material in accordance with a particular embodiment of the present invention.

6 through 8 include illustrations of cross-sectional views of the workpiece of Fig. 5 after forming a floating gate structure in accordance with a particular embodiment of the present invention.

9 through 11 include illustrations of top and cross-sectional views of the workpiece of FIG. 7 after forming a conductive layer and a patterned layer in accordance with a particular embodiment of the present invention.

12 through 14 include illustrations of top and cross-sectional views of the workpiece of Fig. 10 after forming a well region in accordance with a particular embodiment of the present invention.

Figure 15 includes an illustration of a cross-sectional view of the workpiece of Figure 13 after forming a doped region in accordance with a particular embodiment of the present invention.

Figure 16 includes an illustration of a cross-sectional view of the workpiece of Figure 15 after forming a doped region, in accordance with a particular embodiment of the present invention.

17 includes an illustration of a cross-sectional view of the workpiece of FIG. 16 after forming a source region and sidewall spacers in accordance with a particular embodiment of the present invention.

Figure 18 includes an illustration of a cross-sectional view of the workpiece of Figure 17 after forming a doped region, in accordance with a particular embodiment of the present invention.

Figure 19 includes an illustration of a cross-sectional view of the workpiece of Figure 18 after forming a joint region in accordance with a particular embodiment of the present invention.

20 includes an illustration of a top view of a portion of a workpiece including the cross-sectional position of FIG. 19 in accordance with a particular embodiment of the present invention.

21 includes an illustration of a cross-sectional view of the workpiece of FIG. 19 after forming a sandwich dielectric in accordance with a particular embodiment of the present invention.

Figure 22 includes an illustration of a cross-sectional view of the workpiece of Figure 21 after forming a conductive contact in accordance with a particular embodiment of the present invention.

23 includes an illustration of a cross-sectional view of the workpiece of FIG. 22 after forming a passivation layer in accordance with a particular embodiment of the present invention.

Figure 24 includes a schematic illustration of a portion of a memory array in accordance with certain embodiments of the present invention.

Figure 25 includes an illustration of a table listing operating voltages in accordance with certain embodiments of the present invention.

122. . . Conductive area

312. . . Gate structure

322. . . Gate structure

332. . . Gate structure

430. . . Side spacer

431. . . Side spacer

442. . . Telluride region

450. . . Patterned layer

451. . . Contact opening

452. . . Contact opening

453. . . Contact

454. . . Contact

460. . . wire

498. . . Connection area

499. . . Connection area

1321. . . N-doped region

1322. . . N-doped region

1328. . . Body area

1329. . . Body area

2521. . . Floating gate

2522. . . Floating gate

2523. . . Floating gate

2612. . . Control gate

2622. . . Control gate

2632. . . Control gate

13232. . . LDD area

13241. . . LDD area

13242. . . LDD area

13252. . . Source area

13261. . . Source area

13262. . . Source area

Claims (20)

A method of forming an electronic device, the method comprising: providing a substrate comprising a conductive region, the conductive region being below a major surface of the substrate and spaced apart from the major surface of the substrate; Forming a position of one of the first memory cells of one of the non-volatile memory arrays, forming a first gate structure overlying a first body region, wherein the first body region is at the first gate Between the structure and the conductive region, and the first body region overlies the conductive region; at a position of forming one of the second memory cells of the non-volatile memory array, forming an overlying first a second gate structure of one of the body regions, wherein the second body region is between the second gate structure and the conductive region, and the second body region overlies the conductive region; and forming Above the conductive region and electrically connected to one of the first drain region and the second drain region of the conductive region, wherein the first drain region is part of the first memory cell and Second bungee zone a portion of the second memory unit, wherein the first drain region and the second drain region are combined with one of the conductive regions to be the first memory unit and the second memory unit One part of a shared bungee area. The method of claim 1, further comprising forming a first source region and a second source region over the conductive region, wherein the first a source region is a portion of the first memory cell, and the second source region is a portion of the second memory cell, wherein the first source region and the second source region are electrically Connected to the same one of the source lines and spaced apart from each other, and the first source region is one of the source regions closest to the second source region. The method of claim 1, wherein the first drain region and the second drain region are spaced apart from each other. The method of claim 1, wherein the conductive region, the first drain region, and the second drain region have a first conductivity type, and the first body region and the second body region There is one of the second conductivity types opposite to the first conductivity type. The method of claim 1, wherein the first drain region is adjacent to the conductive region. The method of claim 1, wherein each of the first memory unit and the second memory unit comprises a planar transistor. The method of claim 1, wherein the conductive region has a first conductivity type, the first body region and the second body region have a second conductivity type and abut the conductive region, and the second The conductivity type is opposite to the first conductivity type. The method of claim 1, wherein the conductive region is a first conductive region, and the substrate further comprises a second conductive region, wherein the second conductive region is covered by an insulator region when viewed from a top view Separating the first conductive regions, the method further comprising: forming a third memory unit in one of the non-volatile memory arrays a third gate structure overlying a third body region, wherein the third body region is between the third gate structure and the second conductive region; One of the fourth memory cells at one of the non-volatile memory arrays forms a fourth gate structure overlying a fourth body region, wherein the fourth body region is in the fourth gate structure Between the second conductive regions; forming a second conductive region overlying and electrically connected to one of the second conductive regions, the third drain region, the third gate region and the third gate A structure is associated; and a fourth drain region overlying the second conductive region and electrically connected to the second conductive region is formed, the fourth drain region being associated with the fourth gate structure. The method of claim 8, wherein the insulator region extends from the major surface of the substrate, abuts the first conductive region, and another one of the first conductive region and another bit line segment The conductive area is electrically insulated. The method of claim 1, wherein the shared drain region is shared only by memory cells of the non-volatile memory array segment. A method of forming an electronic device, the method comprising: providing a substrate, the substrate comprising a conductive region under one of the main surfaces of the substrate and spaced apart from the main surface of the substrate; forming a a first memory unit, the first memory unit comprising a And a body region electrically connected to one of the bit line segments of one of the non-volatile memory arrays; and forming a second memory unit, the second memory unit including a body region and electrically connected to a drain region of one of the bit line segments, wherein: the first memory cell and the drain region of the second memory cell are separated from each other; and the bit line segment includes The conductive area. The method of claim 11, wherein the body region of the first memory cell has a first conductivity type, and forming the first memory cell further comprises forming an electrical connection to the first memory cell One of the source regions is a source region, wherein the source region has a second conductivity type opposite to the first conductivity type. The method of claim 11, wherein the body region of the first memory unit and the body region of the second memory unit have a first conductivity type, the method further comprising: Detecting, between the body region of the first memory unit and the body region of the second memory unit and adjacent to the body region of the first memory unit and the second The body region of the memory cell forms a region of a second conductivity type. The method of claim 11, further comprising: forming a third memory unit including the body region of the second memory unit and electrically connecting to one of the bit line segments region. The method of claim 11, wherein: forming the first memory unit comprises forming the first memory unit including a source region; forming the second memory unit comprises forming a second source region The second memory unit, the second source region is spaced apart from the source region of the first memory unit; the method further comprising forming a tie region, wherein The connection region is located between the source regions of the first memory unit and the second memory unit and adjacent to the source regions of the first memory unit and the second memory unit . The method of claim 11, further comprising forming a third memory unit, the third memory unit comprising a body region and electrically connected to a different bit line segment of one of the non-volatile memory arrays a drain region, wherein: the different bit line segments comprise a different conductive region, the different conductive regions being spaced apart from the main surface of the substrate and located at the main portion of the substrate Under the surface; an insulator disposed between the bit line segments; and the first memory cell and the third memory cell are electrically connected to a same word line. The method of claim 11, wherein the first memory cell and the drain region of the second memory cell are included in a common drain region. An electronic device comprising: a substrate comprising a conductive region spaced apart from a major surface of the substrate and located under the main surface of the substrate; one of a non-volatile memory array a first memory unit, the first memory unit includes a first planar transistor, the first planar transistor includes a body region, a gate structure, a source region, and a drain region, wherein The gate structure includes a gate dielectric and a charge storage region, wherein the drain region overlies the conductive region and is electrically connected to the conductive region, and the body region is in the gate structure Between the conductive regions; and a second memory unit of the non-volatile memory array, the second memory unit includes a second planar transistor, and the second planar transistor includes a body region a gate structure, a source region and a drain region, wherein the gate structure comprises a gate dielectric and a charge storage region, wherein the drain region overlies the conductive region and is electrically connected To the place a conductive region, wherein the body region is between the gate structure and the conductive region, wherein a conductive line covers the source region and the source region of the first planar transistor and the second planar transistor The gate structure, wherein the conductive line electrically connects the source regions of the first memory unit and the second memory unit. The electronic device of claim 18, further comprising: a third memory unit of a non-volatile memory array, comprising a third planar transistor, wherein the third planar transistor comprises a body region a gate structure, a source region, and a drain region, wherein the gate structure includes a gate dielectric and a charge storage region; and the body region surrounding the first memory unit An insulating region that physically isolates the body region of the first memory cell from the body region of the third memory cell, wherein the first memory cell and the first The source regions of the three memory cells are electrically coupled to different source lines. The electronic device of claim 18, further comprising a tie region between said source regions of said first memory unit and said second memory unit, wherein said first memory The connection region, the source region, and the body region of the body unit and the second memory unit are electrically connected to each other.