TWI502611B - Solid electrolytic capacitor package structure for decreasing equivalent series resistance and method of manufacturing the same - Google Patents
Solid electrolytic capacitor package structure for decreasing equivalent series resistance and method of manufacturing the same Download PDFInfo
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Description
本發明係有關於一種固態電解電容器封裝結構及其製作方法,尤指一種用於降低等效串聯電阻的固態電解電容器封裝結構及其製作方法。The invention relates to a solid electrolytic capacitor package structure and a manufacturing method thereof, in particular to a solid electrolytic capacitor package structure for reducing equivalent series resistance and a manufacturing method thereof.
電容器已廣泛地被使用於消費性家電用品、電腦主機板及其周邊、電源供應器、通訊產品、及汽車等的基本元件,其主要的作用包括:濾波、旁路、整流、耦合、去耦、轉相等。是電子產品中不可缺少的元件之一。電容器依照不同的材質及用途,有不同的型態。包括鋁質電解電容、鉭質電解電容、積層陶瓷電容、薄膜電容等。先行技術中,固態電解電容器具有小尺寸、大電容量、頻率特性優越等優點,而可使用於中央處理器的電源電路的解耦合作用上。一般而言,可利用多個電容單元的堆疊,而形成高電容量的固態電解電容器,習知堆疊式固態電解電容器包括多個電容單元與導線架,其中每一電容單元包括陽極部、陰極部與絕緣部,此絕緣部使陽極部與陰極部彼此電性絕緣。特別是,電容單元的陰極部彼此堆疊,且藉由在相鄰的電容單元之間設置導電體層,以使多個電容單元之間彼此電性連接。然而,習知的固態電解電容器的設計仍然無法有效降低等效串聯電阻(equivalent series resistance,ESR)。Capacitors have been widely used in consumer appliances, computer motherboards and their peripherals, power supplies, communication products, and automotive basic components, including: filtering, bypass, rectification, coupling, decoupling And turn equal. It is one of the indispensable components in electronic products. Capacitors have different types according to different materials and uses. Including aluminum electrolytic capacitors, tantalum electrolytic capacitors, multilayer ceramic capacitors, film capacitors and so on. In the prior art, the solid electrolytic capacitor has the advantages of small size, large capacitance, superior frequency characteristics, and the decoupling of the power supply circuit for the central processing unit. In general, a stack of a plurality of capacitor units can be utilized to form a high-capacity solid electrolytic capacitor. The conventional stacked solid-state electrolytic capacitor includes a plurality of capacitor units and a lead frame, wherein each capacitor unit includes an anode portion and a cathode portion. And the insulating portion, the insulating portion electrically insulates the anode portion from the cathode portion. In particular, the cathode portions of the capacitor unit are stacked on each other, and a plurality of capacitor units are electrically connected to each other by providing a conductor layer between adjacent capacitor units. However, the design of conventional solid electrolytic capacitors still cannot effectively reduce the equivalent series resistance (equivalent Series resistance, ESR).
本發明實施例在於提供一種用於降低等效串聯電阻的固態電解電容器封裝結構及其製作方法。An embodiment of the present invention provides a solid electrolytic capacitor package structure for reducing equivalent series resistance and a manufacturing method thereof.
本發明其中一實施例所提供的一種用於降低等效串聯電阻的固態電解電容器封裝結構,其包括:一電容單元、一封裝單元及一導電單元。所述電容單元包括多個依序堆疊在一起且彼此電性連接的第一堆疊型電容器,其中每一個所述第一堆疊型電容器具有一第一正極部及一第一負極部。所述封裝單元包括一完全包覆所述電容單元的封裝體。所述導電單元包括一第一導電端子及一與所述第一導電端子彼此分離的第二導電端子,其中所述第一導電端子具有一電性連接於所述第一堆疊型電容器的所述第一正極部且被包覆在所述封裝體內的第一內埋部及一連接於所述第一內埋部且裸露在所述封裝體外的第一裸露部,且所述第二導電端子具有一電性連接於所述第一堆疊型電容器的所述第一負極部且被包覆在所述封裝體內的第二內埋部及一連接於所述第二內埋部且裸露在所述封裝體外的第二裸露部;其中,所述第二導電端子具有一上表面、一與所述上表面相對應的下表面、一連接於所述上表面與所述下表面之間的側表面、及至少一連接於所述上表面與所述下表面之間的貫穿孔(或至少一連接於所述上表面、所述下表面及所述側表面三者之間的貫穿開槽),最底端的所述第一堆疊型電容器通過導電膠以固定在所述第二導電端子的所述上表面上,且所述導電膠具有一設置於最底端的所述第一堆疊型電容器與所述第二導電端子的所述上表面之間的第一導電部及一連接於所述第一導電部且填充於至少一所述貫穿孔或貫穿開槽內的第二導電部。A solid electrolytic capacitor package structure for reducing equivalent series resistance is provided in one embodiment of the present invention, comprising: a capacitor unit, a package unit and a conductive unit. The capacitor unit includes a plurality of first stacked capacitors stacked in series and electrically connected to each other, wherein each of the first stacked capacitors has a first positive portion and a first negative portion. The package unit includes a package that completely covers the capacitor unit. The conductive unit includes a first conductive terminal and a second conductive terminal separated from the first conductive terminal, wherein the first conductive terminal has an electrical connection to the first stacked capacitor a first positive electrode portion and a first embedded portion covered in the package body and a first exposed portion connected to the first embedded portion and exposed outside the package body, and the second conductive terminal Having a second buried portion electrically connected to the first negative electrode portion of the first stacked capacitor and covered in the package body, and a second buried portion connected to the second embedded portion and exposed a second exposed portion outside the package; wherein the second conductive terminal has an upper surface, a lower surface corresponding to the upper surface, and a side connected between the upper surface and the lower surface a surface, and at least one through hole (or at least one through slot connected between the upper surface, the lower surface, and the side surface) connected between the upper surface and the lower surface The bottommost first stacked capacitor is electrically conductive Fixing on the upper surface of the second conductive terminal, and the conductive paste has a first stacked type capacitor disposed at a bottom end and the upper surface of the second conductive terminal a first conductive portion and a second conductive portion connected to the first conductive portion and filled in at least one of the through holes or through the slots.
本發明另外一實施例所提供的一種用於降低等效串聯電阻的固態電解電容器封裝結構的製作方法,其包括下列步驟:首先, 提供一第一導電端子及一第二導電端子,其中所述第二導電端子具有一上表面、一與所述上表面相對應的下表面、及至少一連接於所述上表面與所述下表面之間的貫穿孔;接著,將多個第一堆疊型電容器依序堆疊在一起且電性連接於所述第一導電端子及所述第二導電端子之間,其中每一個所述第一堆疊型電容器具有一第一正極部及一第一負極部,最底端的所述第一堆疊型電容器通過導電膠以固定在所述第二導電端子的所述上表面上,且所述導電膠具有一設置於最底端的所述第一堆疊型電容器與所述第二導電端子的所述上表面之間的第一導電部及一連接於所述第一導電部且填充於至少一所述貫穿孔內的第二導電部;然後,形成一封裝體以完全包覆所述電容單元,其中所述第一導電端子具有一電性連接於所述第一堆疊型電容器的所述第一正極部且被包覆在所述封裝體內的第一內埋部及一連接於所述第一內埋部且裸露在所述封裝體外的第一裸露部,且所述第二導電端子具有一電性連接於所述第一堆疊型電容器的所述第一負極部且被包覆在所述封裝體內的第二內埋部及一連接於所述第二內埋部且裸露在所述封裝體外的第二裸露部;最後,彎折所述第一裸露部與所述第二裸露部,以使得所述第一裸露部與所述第二裸露部皆沿著所述封裝體的外表面延伸。Another embodiment of the present invention provides a method for fabricating a solid electrolytic capacitor package structure for reducing equivalent series resistance, which comprises the following steps: First, Providing a first conductive terminal and a second conductive terminal, wherein the second conductive terminal has an upper surface, a lower surface corresponding to the upper surface, and at least one connected to the upper surface and the lower surface a through hole between the surfaces; then, a plurality of first stacked capacitors are sequentially stacked together and electrically connected between the first conductive terminal and the second conductive terminal, wherein each of the first The stacked capacitor has a first positive electrode portion and a first negative electrode portion, and the bottommost first stacked type capacitor is fixed on the upper surface of the second conductive terminal by a conductive paste, and the conductive paste Having a first conductive portion disposed between the first stacked capacitor and the upper surface of the second conductive terminal and connected to the first conductive portion and filled in at least one of a second conductive portion in the through hole; then, a package is formed to completely cover the capacitor unit, wherein the first conductive terminal has a first positive electrode electrically connected to the first stacked capacitor And packaged a first embedded portion in the package body and a first exposed portion connected to the first embedded portion and exposed outside the package body, and the second conductive terminal has an electrical connection a first buried portion of the first stacked capacitor and a second buried portion covered in the package; and a second exposed portion connected to the second embedded portion and exposed outside the package Finally, the first exposed portion and the second exposed portion are bent such that both the first exposed portion and the second exposed portion extend along an outer surface of the package.
本發明的有益效果可以在於,本發明實施例所提供的固態電解電容器封裝結構及其製作方法,其可透過“所述第二導電端子具有至少一貫穿孔或貫穿開槽”與“所述導電膠具有一設置於最底端的所述第一堆疊型電容器與所述第二導電端子的所述上表面之間的第一導電部及一連接於所述第一導電部且填充於至少一所述貫穿孔或貫穿開槽內的第二導電部”的設計,以有效降低等效串聯電阻(equivalent series resistance,ESR),並增加所述第一堆疊型電容器固定在所述第二導電端子的上表面上的固晶強度,以避免所述第一堆疊型電容器產生脫離所述第二導電端子的可能性。The beneficial effects of the present invention may be that the solid electrolytic capacitor package structure and the manufacturing method thereof provided by the embodiments of the present invention are permeable to "the second conductive terminal has at least consistent perforation or through slotting" and "the conductive adhesive Having a first conductive portion disposed between the first stacked capacitor and the upper surface of the second conductive terminal and connected to the first conductive portion and filled in at least one of a design of the through hole or the second conductive portion extending through the groove to effectively reduce an equivalent series resistance (ESR) and increase the first stacked type capacitor to be fixed on the second conductive terminal The bond strength on the surface to avoid the possibility of the first stacked capacitor being disconnected from the second conductive terminal.
為使能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與附圖,然而所附圖式僅提供參考與說明用,並非用來對本發明加以限制者。For a better understanding of the features and technical aspects of the present invention, reference should be made to the accompanying drawings.
Z‧‧‧電容器封裝結構Z‧‧‧ capacitor package structure
1‧‧‧電容單元1‧‧‧Capacitor unit
10‧‧‧第一堆疊型電容器10‧‧‧First stacked capacitor
P‧‧‧第一正極部P‧‧‧First positive part
N‧‧‧第一負極部N‧‧‧First negative part
100‧‧‧閥金屬箔片100‧‧‧ valve metal foil
101‧‧‧氧化層101‧‧‧Oxide layer
1010‧‧‧圍繞區域1010‧‧‧ Around the area
102‧‧‧導電高分子層102‧‧‧ Conductive polymer layer
1020‧‧‧末端End of 1020‧‧
103‧‧‧碳膠層103‧‧‧carbon layer
1030‧‧‧末端End of 1030‧‧
104‧‧‧銀膠層104‧‧‧Silver layer
1040‧‧‧末端End of 1040‧‧
105‧‧‧圍繞狀絕緣層105‧‧‧round insulation
10’‧‧‧第二堆疊型電容器10'‧‧‧Second stacked capacitor
P’‧‧‧第二正極部P’‧‧‧Second positive part
N’‧‧‧第二負極部N’‧‧‧second negative part
11‧‧‧導電膠11‧‧‧Conductive adhesive
111‧‧‧第一導電部111‧‧‧First Conductive Department
112‧‧‧第二導電部112‧‧‧Second Conductive Department
113‧‧‧第三導電部113‧‧‧ Third Conductive Department
2‧‧‧封裝單元2‧‧‧Package unit
20‧‧‧封裝體20‧‧‧Package
201‧‧‧第一側表面201‧‧‧ first side surface
202‧‧‧第二側表面202‧‧‧Second side surface
203‧‧‧底表面203‧‧‧ bottom surface
3‧‧‧導電單元3‧‧‧Conducting unit
31‧‧‧第一導電端子31‧‧‧First conductive terminal
310‧‧‧第一內埋部310‧‧‧First Internal Department
3101‧‧‧第一貫穿填膠孔3101‧‧‧First through the glue hole
311‧‧‧第一裸露部311‧‧‧First exposed department
32‧‧‧第二導電端子32‧‧‧Second conductive terminal
320‧‧‧第二內埋部320‧‧‧Second Internal Department
321‧‧‧第二裸露部321‧‧‧Second exposed department
3200‧‧‧上表面3200‧‧‧ upper surface
3201‧‧‧下表面3201‧‧‧ lower surface
3202‧‧‧貫穿孔3202‧‧‧through holes
3203‧‧‧第二貫穿填膠孔3203‧‧‧Second through plastic hole
3204‧‧‧側表面3204‧‧‧ side surface
3205‧‧‧貫穿開槽3205‧‧‧through slotting
32A‧‧‧銅質基板32A‧‧‧Bronze substrate
320A‧‧‧環繞內表面320A‧‧‧round inner surface
32B‧‧‧鍍錫層32B‧‧‧ tin plating
圖1為本發明第一實施例的電容單元的側視剖面示意圖。1 is a side cross-sectional view showing a capacitor unit according to a first embodiment of the present invention.
圖2A為本發明第一實施例的第一種導電單元的上視示意圖。2A is a top plan view of a first type of conductive unit in accordance with a first embodiment of the present invention.
圖2B為本發明第一實施例的第二種導電單元的上視示意圖。2B is a top plan view of a second type of conductive unit according to the first embodiment of the present invention.
圖2C為本發明第一實施例的第三種導電單元的上視示意圖。2C is a top plan view of a third conductive unit in accordance with a first embodiment of the present invention.
圖3為本發明第一實施例的電容單元設置在導電單元上的上視示意圖。3 is a top plan view showing a capacitor unit disposed on a conductive unit according to a first embodiment of the present invention.
圖4為本發明第一實施例的固態電解電容器封裝結構的側視示意圖。4 is a side elevational view showing a package structure of a solid electrolytic capacitor according to a first embodiment of the present invention.
圖5為圖4中A部分的放大示意圖。Figure 5 is an enlarged schematic view of a portion A of Figure 4.
圖6為本發明第一實施例的固態電解電容器封裝結構的製作方法的流程圖。6 is a flow chart showing a method of fabricating a solid electrolytic capacitor package structure according to a first embodiment of the present invention.
圖7為本發明第二實施例的固態電解電容器封裝結構的側視示意圖。Fig. 7 is a side elevational view showing the package structure of a solid electrolytic capacitor according to a second embodiment of the present invention.
圖8為圖7中A部分的放大示意圖。Figure 8 is an enlarged schematic view of a portion A of Figure 7.
圖9為本發明第三實施例的電容單元設置在導電單元上的上視示意圖。FIG. 9 is a top plan view showing a capacitor unit disposed on a conductive unit according to a third embodiment of the present invention.
圖10為本發明第三實施例的固態電解電容器封裝結構的側視示意圖。Figure 10 is a side elevational view showing the package structure of a solid electrolytic capacitor in accordance with a third embodiment of the present invention.
〔第一實施例〕[First Embodiment]
請參閱圖1至圖6所示,圖1為第一堆疊型電容器10或第二堆疊型電容器10’的側視剖面示意圖,圖2A為其中一種導電單元3的上側示意圖,圖2B為另外一種導電單元3的上側示意圖,圖2C為另外再一種導電單元3的上側示意圖,圖3為第一堆疊型電 容器10設置在導電單元3上的上視示意圖,圖4為固態電解電容器封裝結構Z的側視示意圖,圖5為圖4中A部分的放大示意圖,圖6為固態電解電容器封裝結構Z的製作方法的流程圖。由上述圖式可知,本發明第一實施例提供一種用於降低等效串聯電阻(Equivalent Series Resistance,ESR)的固態電解電容器封裝結構Z,其包括:一電容單元1、一封裝單元2及一導電單元3。1 to FIG. 6, FIG. 1 is a side cross-sectional view of the first stacked capacitor 10 or the second stacked capacitor 10'. FIG. 2A is a schematic diagram of an upper side of one of the conductive units 3, and FIG. 2B is another 2 is a schematic view of the upper side of the conductive unit 3, FIG. 2C is a schematic view of the upper side of another conductive unit 3, and FIG. 3 is a first stacked type of electricity. FIG. 4 is a schematic side view of the solid electrolytic capacitor package structure Z, FIG. 5 is an enlarged schematic view of the portion A of FIG. 4, and FIG. 6 is a manufacturing diagram of the solid electrolytic capacitor package structure Z. Flow chart of the method. The first embodiment of the present invention provides a solid electrolytic capacitor package structure Z for reducing the Equivalent Series Resistance (ESR), which includes: a capacitor unit 1, a package unit 2, and a capacitor. Conductive unit 3.
首先,如圖1所示,電容單元1可提供多個第一堆疊型電容器10(或稱晶片型電容器,目前圖1只顯示其中1個第一堆疊型電容器10),其中每一個第一堆疊型電容器10具有一第一正極部P及一第一負極部N。舉例來說,每一個第一堆疊型電容器10包括一閥金屬箔片100、一完全包覆閥金屬箔片100的氧化層101、一包覆氧化層101的一部分的導電高分子層102、一完全包覆導電高分子層102的碳膠層103、及一完全包覆碳膠層103的銀膠層104。此外,每一個第一堆疊型電容器10包括一設置在氧化層101的外表面上且圍繞氧化層101的圍繞狀絕緣層105,並且第一堆疊型電容器10的導電高分子層102的長度、碳膠層103的長度及銀膠層104的長度皆被圍繞狀絕緣層105所限制。更進一步來說,氧化層101的外表面上具有一圍繞區域1010,並且第一堆疊型電容器10的圍繞狀絕緣層105圍繞地設置在氧化層101的圍繞區域1010上且同時接觸導電高分子層102的末端1020、碳膠層103的末端1030及銀膠層104的末端1040。然而,本發明所使用的第一堆疊型電容器10不以上述第一實施例所舉的例子為限。First, as shown in FIG. 1, the capacitor unit 1 can provide a plurality of first stacked capacitors 10 (or wafer type capacitors, and currently only one of the first stacked capacitors 10 is shown in FIG. 1), wherein each of the first stacks The capacitor 10 has a first positive electrode portion P and a first negative electrode portion N. For example, each of the first stacked capacitors 10 includes a valve metal foil 100, an oxide layer 101 completely covering the valve metal foil 100, a conductive polymer layer 102 covering a portion of the oxide layer 101, and a The carbon glue layer 103 completely covering the conductive polymer layer 102 and the silver glue layer 104 completely covering the carbon glue layer 103. Further, each of the first stacked capacitors 10 includes a surrounding insulating layer 105 disposed on the outer surface of the oxide layer 101 and surrounding the oxide layer 101, and the length of the conductive polymer layer 102 of the first stacked capacitor 10, carbon Both the length of the adhesive layer 103 and the length of the silver paste layer 104 are limited by the surrounding insulating layer 105. Further, the outer surface of the oxide layer 101 has a surrounding area 1010, and the surrounding insulating layer 105 of the first stacked type capacitor 10 is disposed around the surrounding area 1010 of the oxide layer 101 while contacting the conductive polymer layer. End 1020 of 102, end 1030 of carbon glue layer 103, and end 1040 of silver glue layer 104. However, the first stacked capacitor 10 used in the present invention is not limited to the example of the first embodiment described above.
再者,配合圖2A、圖3及圖4所示,多個第一堆疊型電容器10可依序堆疊在一起且彼此電性連接,其中每兩個相鄰的第一堆疊型電容器10的兩個第一負極部N可透過銀膠(未標號)以相互疊堆在一起,並且每兩個相鄰的第一堆疊型電容器10的兩個第一正極部P可透過焊接層(未標號)以相互疊堆在一起。另外,封裝單元2包括一完全包覆電容單元1的封裝體20,並且封裝體20可為不 透光的封裝材料。此外,導電單元3(亦即導線架leadframe)包括一第一導電端子31及一與第一導電端子31彼此分離的第二導電端子32。其中,第一導電端子31具有一電性連接於第一堆疊型電容器10的第一正極部P(亦即電性接觸位於最底端的第一堆疊型電容器10的第一正極部P)且被包覆在封裝體20內的第一內埋部310及一連接於第一內埋部310且裸露在封裝體20外的第一裸露部311,並且第二導電端子32具有一電性連接於第一堆疊型電容器10的第一負極部N(亦即電性接觸位於最底端的第一堆疊型電容器10的第一負極部N)且被包覆在封裝體20內的第二內埋部320及一連接於第二內埋部320且裸露在封裝體20外的第二裸露部321。Furthermore, as shown in FIG. 2A, FIG. 3 and FIG. 4, a plurality of first stacked capacitors 10 can be sequentially stacked and electrically connected to each other, wherein two of each two adjacent first stacked capacitors 10 The first negative electrode portions N are permeable to silver paste (not labeled) to be stacked on each other, and the two first positive electrode portions P of each two adjacent first stacked capacitors 10 are permeable to the solder layer (not labeled) Stacked together. In addition, the package unit 2 includes a package body 20 that completely covers the capacitor unit 1, and the package body 20 may be Light-transmissive packaging material. In addition, the conductive unit 3 (ie, the lead frame) includes a first conductive terminal 31 and a second conductive terminal 32 separated from the first conductive terminal 31. The first conductive terminal 31 has a first positive electrode portion P electrically connected to the first stacked capacitor 10 (ie, electrically contacting the first positive electrode portion P of the first stacked capacitor 10 at the bottom end) and is The first embedded portion 310 is encapsulated in the package body 20 and the first exposed portion 311 is connected to the first embedded portion 310 and exposed outside the package body 20, and the second conductive terminal 32 has an electrical connection The first negative electrode portion N of the first stacked capacitor 10 (that is, electrically contacting the first negative electrode portion N of the first stacked capacitor 10 at the bottom end) and covered in the second embedded portion in the package body 20 320 and a second exposed portion 321 connected to the second embedded portion 320 and exposed outside the package 20 .
更進一步來說,配合圖3與圖4所示,封裝體20具有一第一側表面201、一與第一側表面201彼此相背對(亦即背對背)的第二側表面202、一連接於第一側表面201與第二側表面202之間的底表面203。其中,第一裸露部311可沿著封裝體20的第一側表面201與底表面203來進行延伸,以形成一L型折腳,並且第二裸露部321可沿著封裝體20的第一側表面201與底表面203來進行延伸,以形成另一L型折腳。Furthermore, as shown in FIG. 3 and FIG. 4, the package body 20 has a first side surface 201, a second side surface 202 and a first side surface 201 opposite to each other (ie, back to back). A bottom surface 203 between the first side surface 201 and the second side surface 202. The first exposed portion 311 may extend along the first side surface 201 and the bottom surface 203 of the package body 20 to form an L-shaped folding leg, and the second exposed portion 321 may be along the first portion of the package body 20 . The side surface 201 and the bottom surface 203 are extended to form another L-shaped fold.
更進一步來說,配合圖2、圖3及圖4所示,第二導電端子32具有一上表面3200、一與上表面3200相對應的下表面3201、及至少一連接於上表面3200與下表面3201之間的貫穿孔3202。位於最底端的第一堆疊型電容器10的第一負極部N可通過導電膠11以固定在第二導電端子32的上表面3200上,並且導電膠11具有一設置於最底端的第一堆疊型電容器10與第二導電端子32的上表面3200之間的第一導電部111及一連接於第一導電部111且填充於貫穿孔3202內的第二導電部112。另外,第一導電端子31具有至少一第一貫穿填膠孔3101,第二導電端子32具有至少一第二貫穿填膠孔3203,並且封裝體20可填充於至少一第一貫穿填膠 孔3101及至少一第二貫穿填膠孔3203內,藉此以增加封裝體20包覆第一導電端子31與第二導電端子32的包覆強度(亦即可避免第一導電端子31與第二導電端子32產生脫離封裝體20的可能性)。Furthermore, as shown in FIG. 2, FIG. 3 and FIG. 4, the second conductive terminal 32 has an upper surface 3200, a lower surface 3201 corresponding to the upper surface 3200, and at least one connected to the upper surface 3200 and below. A through hole 3202 between the surfaces 3201. The first negative electrode portion N of the first stacked capacitor 10 at the bottom end may be fixed to the upper surface 3200 of the second conductive terminal 32 by the conductive paste 11, and the conductive paste 11 has a first stacked type disposed at the bottommost end. The first conductive portion 111 between the capacitor 10 and the upper surface 3200 of the second conductive terminal 32 and the second conductive portion 112 connected to the first conductive portion 111 and filled in the through hole 3202. In addition, the first conductive terminal 31 has at least one first through-filling hole 3101, the second conductive terminal 32 has at least one second through-filling hole 3203, and the package 20 can be filled in at least one first through-filling The hole 3101 and the at least one second through-filling hole 3203, thereby increasing the coating strength of the first conductive terminal 31 and the second conductive terminal 32 by the package 20 (ie, avoiding the first conductive terminal 31 and the first The two conductive terminals 32 create the possibility of being detached from the package 20).
舉例來說,配合圖4與圖5所示,第二導電端子32包括一銅質基板32A及一包覆銅質基板32A的外表面的鍍錫層32B。另外,貫穿孔3202貫穿鍍錫層32B及銅質基板32A,並且銅質基板32A具有一位於貫穿孔3202內的環繞內表面320A。導電膠11的第二導電部112可接觸銅質基板32A的環繞內表面320A,並且導電膠11可為銀膠或銅膠。更進一步來說,由於第二導電端子32通過貫穿孔3202以裸露出銅質基板32A的環繞內表面320A,所以作為銀膠或銅膠的導電膠11可以穩固地接觸銅質基板32A的環繞內表面320A,藉此以增加第一堆疊型電容器10固定在第二導電端子32的上表面3200上的固晶強度(亦即可避免第一堆疊型電容器10產生脫離第二導電端子32的可能性)。For example, as shown in FIG. 4 and FIG. 5, the second conductive terminal 32 includes a copper substrate 32A and a tin-plated layer 32B covering the outer surface of the copper substrate 32A. In addition, the through hole 3202 penetrates the tin plating layer 32B and the copper substrate 32A, and the copper substrate 32A has a surrounding inner surface 320A located in the through hole 3202. The second conductive portion 112 of the conductive paste 11 may contact the surrounding inner surface 320A of the copper substrate 32A, and the conductive paste 11 may be silver paste or copper paste. Furthermore, since the second conductive terminal 32 passes through the through hole 3202 to expose the surrounding inner surface 320A of the copper substrate 32A, the conductive paste 11 as silver paste or copper paste can stably contact the inner circumference of the copper substrate 32A. The surface 320A, thereby increasing the solid crystal strength of the first stacked capacitor 10 fixed on the upper surface 3200 of the second conductive terminal 32 (that is, the possibility that the first stacked capacitor 10 is prevented from being separated from the second conductive terminal 32) ).
再者,配合圖1至圖6所示,本發明第一實施例提供一種用於降低等效串聯電阻的固態電解電容器封裝結構Z的製作方法,其包括下列步驟:首先,配合圖3、圖4及圖6所示,提供一第一導電端子31及一第二導電端子32,其中第二導電端子32具有一上表面3200、一與上表面3200相對應的下表面3201、及至少一連接於上表面3200與下表面3201之間的貫穿孔3202(步驟S100);接著,配合圖1、圖4及圖6所示,將多個第一堆疊型電容器10依序堆疊在一起且電性連接於第一導電端子31及第二導電端子32之間,其中每一個第一堆疊型電容器10具有一第一正極部P及一第一負極部N,最底端的第一堆疊型電容器10通過導電膠11以固定在第二導電端子32的上表面3200上,並且導電膠11具有一設置於最底端的第一堆疊型電容器10與第二導電端子32的上表面3200之間的第一導電部111及一連接於第一導電部 111且填充於貫穿孔3202內的第二導電部112(S102);然後,配合圖1、圖4及圖6所示,形成一封裝體20以完全包覆電容單元1,其中第一導電端子31具有一電性連接於第一堆疊型電容器10的第一正極部P且被包覆在封裝體20內的第一內埋部310及一連接於第一內埋部310且裸露在封裝體20外的第一裸露部311,並且第二導電端子32具有一電性連接於第一堆疊型電容器10的第一負極部N且被包覆在封裝體20內的第二內埋部320及一連接於第二內埋部320且裸露在封裝體20外的第二裸露部321(S104);最後,彎折第一裸露部311與第二裸露部321,以使得第一裸露部311與第二裸露部321皆沿著封裝體20的外表面延伸(S106)。Furthermore, with reference to FIG. 1 to FIG. 6 , a first embodiment of the present invention provides a method for fabricating a solid electrolytic capacitor package structure Z for reducing equivalent series resistance, which comprises the following steps: First, with FIG. 3 and FIG. 4 and FIG. 6, a first conductive terminal 31 and a second conductive terminal 32 are provided. The second conductive terminal 32 has an upper surface 3200, a lower surface 3201 corresponding to the upper surface 3200, and at least one connection. a through hole 3202 between the upper surface 3200 and the lower surface 3201 (step S100); then, as shown in FIG. 1, FIG. 4 and FIG. 6, the plurality of first stacked capacitors 10 are sequentially stacked and electrically connected. Connected between the first conductive terminal 31 and the second conductive terminal 32, wherein each of the first stacked capacitors 10 has a first positive electrode portion P and a first negative electrode portion N, and the bottommost first stacked capacitor 10 passes through The conductive paste 11 is fixed on the upper surface 3200 of the second conductive terminal 32, and the conductive paste 11 has a first conductive relationship between the first stacked capacitor 10 disposed at the bottommost end and the upper surface 3200 of the second conductive terminal 32. Portion 111 and one connected to the first conductive 111 and filling the second conductive portion 112 in the through hole 3202 (S102); then, as shown in FIG. 1, FIG. 4 and FIG. 6, a package body 20 is formed to completely cover the capacitor unit 1, wherein the first conductive terminal The first embedded portion 310 electrically connected to the first positive electrode portion P of the first stacked capacitor 10 and covered in the package 20 and connected to the first embedded portion 310 and exposed in the package a first exposed portion 311 outside the 20, and the second conductive terminal 32 has a second buried portion 320 electrically connected to the first negative portion N of the first stacked capacitor 10 and covered in the package 20 and a second exposed portion 321 connected to the second embedded portion 320 and exposed outside the package body 20 (S104); finally, the first exposed portion 311 and the second exposed portion 321 are bent so that the first exposed portion 311 and The second exposed portions 321 all extend along the outer surface of the package 20 (S106).
再者,本發明將具有貫穿孔3202的固態電解電容器封裝結構Z與沒有貫穿孔3202的固態電解電容器封裝結構Z來進行10組等效串聯電阻的量測,其量測結果顯示如下所示:有使用貫穿孔3202的固態電解電容器封裝結構Z具有較低的平均等效串聯電阻,其單位為mΩ。Furthermore, the present invention performs measurement of 10 sets of equivalent series resistances by the solid electrolytic capacitor package structure Z having the through holes 3202 and the solid electrolytic capacitor package structure Z having no through holes 3202, and the measurement results are as follows: The solid electrolytic capacitor package structure Z using the through holes 3202 has a lower average equivalent series resistance in units of mΩ.
更進一步來說,配合圖2B與圖2C所示,貫穿孔3202的數量也可以是兩個或兩個以上的圓形穿孔(如圖2B所示),或者是貫穿 孔3202也可以是狹長型的穿孔(如圖2C所示)。因此,本發明有關貫穿孔3202的數量、形狀及所設置位置的界定都是用來舉例而已,其並非用來限定本發明。例如,貫穿孔3202可以隨意前後左右偏移,並且貫穿孔3202還可以是三角形、長方形、多邊形或花瓣形等。Furthermore, as shown in FIG. 2B and FIG. 2C, the number of through holes 3202 may also be two or more circular perforations (as shown in FIG. 2B), or The aperture 3202 can also be an elongated perforation (as shown in Figure 2C). Accordingly, the present invention is intended to be illustrative of the number, shape, and location of the through-holes 3202, which are not intended to limit the invention. For example, the through holes 3202 may be arbitrarily shifted back and forth, and the through holes 3202 may also be triangular, rectangular, polygonal, or petal shaped or the like.
〔第二實施例〕[Second embodiment]
請參閱圖7與圖8所示,圖7為固態電解電容器封裝結構的側視示意圖,並且圖8為圖7中A部分的放大示意圖。由圖7與圖4的比較、及圖8與圖5的比較可知,本發明二實施例與第一實施例最大的差別在於:配合圖1、圖7及圖8所示,在第二實施例中,電容單元1包括多個依序堆疊在一起且彼此電性連接的第二堆疊型電容器10’。其中,每一個第二堆疊型電容器10’具有一第二正極部P’及一第二負極部N’,最底端的第二堆疊型電容器10’可通過導電膠11以固定在第二導電端子32的下表面3201上,並且導電膠11具有一設置於最底端的第二堆疊型電容器10’與第二導電端子32的下表面3201之間且連接於第二導電部112的第三導電部113。Please refer to FIG. 7 and FIG. 8. FIG. 7 is a schematic side view of the solid electrolytic capacitor package structure, and FIG. 8 is an enlarged schematic view of a portion A of FIG. From the comparison between FIG. 7 and FIG. 4 and the comparison between FIG. 8 and FIG. 5, the greatest difference between the second embodiment of the present invention and the first embodiment is that, in conjunction with FIG. 1, FIG. 7, and FIG. 8, in the second implementation. In the example, the capacitor unit 1 includes a plurality of second stacked capacitors 10' that are sequentially stacked and electrically connected to each other. Each of the second stacked capacitors 10' has a second positive electrode portion P' and a second negative electrode portion N'. The bottommost second stacked capacitor 10' can be fixed to the second conductive terminal through the conductive adhesive 11. The lower surface 3201 of the second conductive portion 11 has a second conductive portion 11 disposed between the bottommost second stacked type capacitor 10' and the lower surface 3201 of the second conductive terminal 32 and connected to the third conductive portion 112. 113.
再者,本發明第二實施例也可提供一種用於降低等效串聯電阻的固態電解電容器封裝結構的製作方法,其與第一實施例(如圖6所示)的製作方法最大的差別在於:在圖6的步驟S102中可更進一步包括:將多個第二堆疊型電容器10’依序堆疊在一起且電性連接於第一導電端子31及第二導電端子32之間,其中最底端的第二堆疊型電容器10’可通過導電膠11以固定在第二導電端子32的下表面3201上,並且導電膠11具有一設置於最底端的第二堆疊型電容器10’與第二導電端子32的下表面3201之間且連接於第二導電部112的第三導電部113。Furthermore, the second embodiment of the present invention can also provide a method for fabricating a solid electrolytic capacitor package structure for reducing equivalent series resistance, which is the biggest difference from the manufacturing method of the first embodiment (shown in FIG. 6). The step S102 of FIG. 6 may further include: sequentially stacking the plurality of second stacked capacitors 10 ′ and electrically connecting between the first conductive terminal 31 and the second conductive terminal 32 , wherein the bottom is The second stacked capacitor 10' at the end may be fixed on the lower surface 3201 of the second conductive terminal 32 by the conductive paste 11, and the conductive paste 11 has a second stacked capacitor 10' and a second conductive terminal disposed at the bottommost end. The lower surface 3201 of the 32 is connected to the third conductive portion 113 of the second conductive portion 112.
〔第三實施例〕[Third embodiment]
請參閱圖9與圖10所示,圖9為第一堆疊型電容器設置在導 電單元上的上視示意圖,並且圖10為固態電解電容器封裝結構的側視示意圖。由圖9與圖3的比較、及圖10與圖4的比較可知,本發明三實施例與第一實施例最大的差別在於:在第三實施例中,第二導電端子32具有一上表面3200、一與上表面3200相對應的下表面3201、一連接於上表面3200與下表面3201之間的側表面3204、及至少一連接於上表面3200、下表面3201及側表面3204三者之間的貫穿開槽3205。最底端的第一堆疊型電容器10可通過導電膠11以固定在第二導電端子32的上表面3200上,並且導電膠11具有一設置於最底端的第一堆疊型電容器10與第二導電端子32的上表面3200之間的第一導電部111及一連接於第一導電部111且填充於貫穿開槽3205內的第二導電部112。然而,本發明有關貫穿開槽3205的數量、形狀及所設置位置的界定都是用來舉例而已,其並非用來限定本發明。Please refer to FIG. 9 and FIG. 10, FIG. 9 is a first stacked capacitor disposed in the guide. A top view on the electrical unit, and Figure 10 is a side elevational view of the solid electrolytic capacitor package structure. 9 is compared with FIG. 3 and FIG. 10 and FIG. 4, the maximum difference between the third embodiment of the present invention and the first embodiment is that in the third embodiment, the second conductive terminal 32 has an upper surface. 3200, a lower surface 3201 corresponding to the upper surface 3200, a side surface 3204 connected between the upper surface 3200 and the lower surface 3201, and at least one connected to the upper surface 3200, the lower surface 3201, and the side surface 3204 There is a through slot 3205. The bottommost first stacked capacitor 10 can be fixed on the upper surface 3200 of the second conductive terminal 32 by the conductive paste 11, and the conductive paste 11 has a first stacked capacitor 10 and a second conductive terminal disposed at the bottommost end. The first conductive portion 111 between the upper surface 3200 of the 32 and the second conductive portion 112 connected to the first conductive portion 111 and filled in the through groove 3205. However, the definition of the number, shape, and location of the through-groove 3205 of the present invention is by way of example and is not intended to limit the invention.
〔實施例的可能功效〕[Possible effects of the examples]
綜上所述,本發明的有益效果可以在於,本發明實施例所提供的固態電解電容器封裝結構及其製作方法,其可透過“第二導電端子32具有至少一貫穿孔3202或貫穿開槽3205”與“導電膠11具有一設置於最底端的第一堆疊型電容器10與第二導電端子32的上表面3200之間的第一導電部111及一連接於第一導電部111且填充於貫穿孔3202或貫穿開槽3205內的第二導電部112”的設計,以有效降低等效串聯電阻,並增加第一堆疊型電容器10固定在第二導電端子32的上表面3200上的固晶強度,以避免第一.堆疊型電容器10產生脫離第二導電端子32的可能性。In summary, the beneficial effects of the present invention may be that the solid electrolytic capacitor package structure and the manufacturing method thereof provided by the embodiments of the present invention are permeable to "the second conductive terminal 32 has at least a uniform through hole 3202 or a through slot 3205". And the conductive paste 11 has a first conductive portion 111 disposed between the first stacked capacitor 10 and the upper surface 3200 of the second conductive terminal 32 and is connected to the first conductive portion 111 and filled in the through hole 3202 or a design of the second conductive portion 112" extending through the slot 3205 to effectively reduce the equivalent series resistance and increase the solid crystal strength of the first stacked capacitor 10 fixed on the upper surface 3200 of the second conductive terminal 32, To avoid the possibility that the first stacked capacitor 10 is detached from the second conductive terminal 32.
以上所述僅為本發明的較佳可行實施例,非因此侷限本發明的專利範圍,故舉凡運用本發明說明書及圖式內容所為之等效技術變化,均包含於本發明的範圍內。The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalents of the present invention are intended to be included within the scope of the present invention.
Z‧‧‧電容器封裝結構Z‧‧‧ capacitor package structure
1‧‧‧電容單元1‧‧‧Capacitor unit
10‧‧‧第一堆疊型電容器10‧‧‧First stacked capacitor
P‧‧‧第一正極部P‧‧‧First positive part
N‧‧‧第一負極部N‧‧‧First negative part
11‧‧‧導電膠11‧‧‧Conductive adhesive
111‧‧‧第一導電部111‧‧‧First Conductive Department
112‧‧‧第二導電部112‧‧‧Second Conductive Department
2‧‧‧封裝單元2‧‧‧Package unit
20‧‧‧封裝體20‧‧‧Package
201‧‧‧第一側表面201‧‧‧ first side surface
202‧‧‧第二側表面202‧‧‧Second side surface
203‧‧‧底表面203‧‧‧ bottom surface
3‧‧‧導電單元3‧‧‧Conducting unit
31‧‧‧第一導電端子31‧‧‧First conductive terminal
310‧‧‧第一內埋部310‧‧‧First Internal Department
3101‧‧‧第一貫穿填膠孔3101‧‧‧First through the glue hole
311‧‧‧第一裸露部311‧‧‧First exposed department
32‧‧‧第二導電端子32‧‧‧Second conductive terminal
320‧‧‧第二內埋部320‧‧‧Second Internal Department
321‧‧‧第二裸露部321‧‧‧Second exposed department
3200‧‧‧上表面3200‧‧‧ upper surface
3201‧‧‧下表面3201‧‧‧ lower surface
3202‧‧‧貫穿孔3202‧‧‧through holes
3203‧‧‧第二貫穿填膠孔3203‧‧‧Second through plastic hole
Claims (11)
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CN201310324408.XA CN103456513B (en) | 2013-02-06 | 2013-07-30 | Solid electrolytic capacitor packaging structure for reducing equivalent series resistance and manufacturing method thereof |
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CN104299788A (en) * | 2014-10-28 | 2015-01-21 | 钰邦电子(无锡)有限公司 | Manufacturing method of solid electrolytic capacitor packaging structure for improvement of conductive terminals |
CN110895994B (en) * | 2018-09-12 | 2021-07-27 | 钰冠科技股份有限公司 | Stacked capacitor assembly structure |
CN110895995B (en) * | 2018-09-12 | 2022-07-22 | 钰冠科技股份有限公司 | Capacitor, capacitor packaging structure and manufacturing method thereof |
CN110942917A (en) * | 2018-09-21 | 2020-03-31 | 钰冠科技股份有限公司 | Capacitor packaging structure, capacitor and polymer composite layer |
CN110942918B (en) * | 2018-09-21 | 2022-08-12 | 钰冠科技股份有限公司 | Stacked capacitor, manufacturing method thereof and silver colloid layer |
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TW201131600A (en) * | 2010-03-05 | 2011-09-16 | Apaq Technology Co Ltd | Stacked capacitor with many product pins |
TW201243890A (en) * | 2011-04-27 | 2012-11-01 | Apaq Technology Co Ltd | Capacitance unit and stacked solid electrolytic capacitor |
TWM443270U (en) * | 2012-07-04 | 2012-12-11 | Apaq Technology Co Ltd | Stacked solid electrolytic capacitor package structure |
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US6421227B2 (en) * | 1999-12-10 | 2002-07-16 | Showa Denko K.K. | Solid electrolytic multilayer capacitor |
US6972943B2 (en) * | 2002-12-12 | 2005-12-06 | Sanyo Electric Co., Ltd. | Electronic component having lead frame |
US7265965B2 (en) * | 2004-07-07 | 2007-09-04 | Showa Denko K.K. | Capacitor element and carbon paste |
JP4688875B2 (en) * | 2005-05-13 | 2011-05-25 | 三洋電機株式会社 | Multilayer solid electrolytic capacitor and manufacturing method thereof |
CN102024567A (en) * | 2010-12-07 | 2011-04-20 | 钰邦电子(无锡)有限公司 | Stack type solid electrolytic capacitor with multi-end product lead-out pin |
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TW201131600A (en) * | 2010-03-05 | 2011-09-16 | Apaq Technology Co Ltd | Stacked capacitor with many product pins |
TW201243890A (en) * | 2011-04-27 | 2012-11-01 | Apaq Technology Co Ltd | Capacitance unit and stacked solid electrolytic capacitor |
TWM443270U (en) * | 2012-07-04 | 2012-12-11 | Apaq Technology Co Ltd | Stacked solid electrolytic capacitor package structure |
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