TWI500166B - Integrated pmos transistor and schottky diode and charging switch circuit employing the integrated device - Google Patents

Description

Integrated component of PMOS transistor and Schottky diode, and charging switch circuit using the integrated component

The present invention relates to an integrated component of a PMOS transistor and a Schottky Diode, and a charging switch circuit using the integrated component.

Power switching elements consisting of separate PMOS transistors and separate Schottky diodes are often required in power control circuits. Referring to FIG. 1, the PMOS transistor 14 and the Schottky diode 12 are connected in series as a power switching element, and the PMOS transistor 14 includes a parasitic diode 14D formed in the drain and channel regions of the PMOS transistor 14. between. The control circuit 10 controls the gate of the PMOS transistor 14 to convert the input voltage Vin into an output voltage Vo. The function of the Schottky diode 12 is to prevent the current from flowing back through the parasitic diode 14D and the input voltage Vin is damaged when the output voltage Vo is higher than the input voltage Vin.

A disadvantage of the prior art described above is that the independent PMOS transistor occupies a considerable area with the independent Schottky diode, and increases the on-resistance (Ron) between the input voltage Vin and the output voltage Vo in series, at a large current flow. The voltage drop caused by the on-resistance can be as high as 0.8V or higher, resulting in great power consumption.

In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and proposes an integrated component of a PMOS transistor and a Schottky diode to reduce the area of the power switching element and reduce its on-resistance. Furthermore, the present invention also proposes a charging switch circuit constructed using the integrated component.

One of the objects of the present invention is to provide an integrated component of a PMOS transistor and a Schottky diode, which can be planar or gully.

Another object of the present invention is to provide a charging switch circuit constructed by the above-described integrated components, thereby reducing unnecessary power consumption during charging.

In order to achieve the above object, in one aspect, the present invention provides an integrated component of a PMOS transistor and a Schottky diode, comprising: a PMOS transistor including a gate, a source, a drain and a source a channel region between the drains, the source, the drain and the channel region are located in a matrix, and a parasitic diode is formed between the drain and the channel; and a reverse connection with the parasitic diode A stellate diode, the Schottky diode is located in the substrate, one end of which is connected to the parasitic diode, and the other end is connected to the source.

In a preferred embodiment, the Schottky diode includes a portion of the well region that is in the same conductivity profile as the channel region without ohmic contact.

In a preferred embodiment, the Schottky diode further comprises a doped region of a different conductivity type than the channel region.

In view of one of the semiconductor structures, the integrated component of the PMOS transistor and the Schottky diode of the present invention comprises: a substrate; a conductor layer on the substrate, forming a gate of the PMOS transistor; An N-type first well region in the substrate, a portion of which constitutes a channel region of the PMOS transistor; a first P-type doped region located in the first well region constituting a drain of the PMOS transistor, wherein the 汲a pole and a channel region form a parasitic diode; a second P-type doped region located in the first well region constitutes a source of the PMOS transistor; and a portion formed by another portion of the first well region The special base diode is reversely connected in series with the parasitic diode and does not have an N-type ohmic contact in the other portion of the first well region.

In a preferred embodiment, the third P-type doped region is further included in the other portion of the first well region.

In view of another semiconductor structure, the integrated component of the PMOS transistor and the Schottky diode of the present invention comprises: a P-type substrate constituting a drain of the PMOS transistor; and two of the PMOS transistors; a filled conductor constituting a gate of the PMOS transistor; an N-type well region between the two conductors, a portion of which forms a channel region of the PMOS transistor, wherein a parasitic diode is formed between the drain and the channel region a P-type doped region above the N-type well region, constituting a source of the PMOS transistor; and a Schottky diode formed by another portion of the first well region, and the parasitic diode The body is reversely connected in series and does not have an N-type ohmic contact in the other portion of the first well region.

In a preferred embodiment, at least two P-type doped regions are preferably provided above the N-well region.

In a preferred embodiment, the substrate preferably comprises a relatively high concentration of the body and a lower concentration of epitaxial growth regions above the body.

In another aspect, the present invention provides a charging switch circuit for coupling between a power source and a battery to be charged, the charging switch circuit comprising: first and second integrated components, and controlling the first integrated component a transistor, wherein each integrated component comprises: a PMOS transistor comprising a gate region between a gate, a source, a drain and a source drain, the source, drain and channel regions being located in a substrate; Forming a parasitic diode between the drain and the channel; and a Schottky diode in reverse series with the parasitic diode, the Schottky diode being located in the substrate, one end of the body a parasitic diode is connected, and the other end is connected to the source; wherein the first integrated component is coupled between the power source and the battery, the source is coupled to the power source, the drain is coupled to the battery, and the second integrated component is coupled Between the gate and the drain of the first integrated component, the source is coupled to the gate of the first integrated component, the drain is coupled to the gate of the first integrated component, and the gate is controlled by the power supply; The first end of the transistor of an integrated component is controlled by a power supply, The second end receives the control signal for controlling the first integrated component, and the third end controls the gate of the first integrated component.

In the above charging switch circuit, the transistor for controlling the first integrated component may be a MOS transistor or a bipolar transistor. When it is a MOS transistor, a lateral diffusion transistor (LDMOS) is preferred; when it is a bipolar transistor, a lateral bi-carrier NPN transistor (Lnpn) is preferred.

In another aspect, the present invention also provides a charging switch circuit for coupling between a power source and a battery to be charged. The charging switch circuit includes: a first PMOS transistor including a gate and a source, a channel region between the drain and the source drain, the source, drain and channel regions are located in a substrate, and a first parasitic diode is formed between the source and the channel region, and the drain and the channel region are Forming a second parasitic diode, the first parasitic diode and the second parasitic diode are connected in reverse; the second PMOS transistor includes a channel region between the gate, the source, the drain and the source drain The source, drain and channel regions are located in a substrate, and a third parasitic diode is formed between the source and the channel region, and a fourth parasitic diode is formed between the drain and the channel region, and the third a parasitic diode and a fourth parasitic diode are connected in reverse; and a transistor for controlling the first PMOS transistor gate; wherein the first PMOS transistor is coupled between the power source and the battery, and the source thereof The power supply is coupled, the drain is coupled to the battery, and the second PMOS transistor is coupled to the first PMOS Between the gate and the drain of the crystal, the source is coupled to the gate of the first PMOS transistor, the drain is coupled to the gate of the first PMOS transistor, and the gate is controlled by the power supply; the first PMOS is controlled The first end of the transistor of the transistor is controlled by the power source, the second end receives the control signal for controlling the first PMOS transistor, and the gate of the first PMOS transistor of the third end.

In the above charging switch circuit, the first and third parasitic diodes may be a general diode or a Schottky diode.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The illustrations of the present specification are schematic and their dimensions are not drawn to scale.

Referring to Figure 2, an embodiment of the present invention is shown in circuit diagram form. As shown in the figure, in the present embodiment, the Schottky diode 22 is not connected in series with the PMOS transistor 24, but is integrated into a part of the PMOS transistor 24 to constitute the power switching element 20. The Schottky diode 22 is formed on the semiconductor substrate of the PMOS transistor 24 in reverse series with the parasitic diode 24D of the PMOS transistor 24; the parasitic diode 24D is formed on the PMOS transistor 14. Between the bungee and the channel area. In this configuration, the input voltage Vin and the output voltage Vo relate only to the on-resistance of the PMOS transistor 24, and there is no voltage drop of the Schottky diode, so that the power consumption can be greatly reduced.

When the above circuit is fabricated in a semiconductor, please refer to Figure 3 for an example of its implementation. As shown in the figure, an N-type well region 201 is formed in the substrate, and a gate oxide layer (not shown) and a gate layer 202 are deposited on the substrate, and a high concentration P+ type is formed in the matrix by ion implantation. The doped regions 203, 204 are respectively used as the drain and source of the PMOS transistor 24. The input voltage Vin is directly connected to the N-type well region 201 in addition to the P+-type doping region 204 of the PMOS transistor 24. Since the direct connection between the input voltage Vin and the N-type well region 201 does not provide an ohmic contact, the conduction barrier is higher at this point, which is equivalent to the provision of a Schottky diode and a P+ doping region. The parasitic diode formed by the 203 and the N-type well region 201 is reversely connected in series, so that the current is not easily reversed from the output terminal Vo through the N-type well region 201 back to the input terminal Vin. In addition, in a preferred embodiment, a high concentration P+ doping region 205 may be further disposed at the position of the Schottky diode in the N-type well region 201 to further control the reverse leakage current of the Schottky diode. .

As can be seen from Fig. 3, the area occupied by the present invention is only equivalent to the area of the single PMOS transistor 24 (or slightly increased the area of the P+ doped region 205), which is much lower than in the prior art. Since the unit area of the overall power switching element is reduced, the PMOS transistor 24 of the present invention can be used with a larger area to make it conductive due to the area where the Schottky diode is saved under the same total area of the power switching element. The resistance is even lower. More specifically, the on-resistance of the power switching element of the present invention is about 1/4 of that of the prior art when compared to the prior art of the same area, since the present invention has no Schottky in the input-output series path. The polar body and the PMOS transistor 24 have an on-resistance of only about half.

Fig. 4 shows another embodiment of the present invention. The PMOS electro-crystal system in this embodiment is a trench type transistor. As shown, two trenches are formed on the P-type substrate 210, and the gate oxide layer 213 is formed by thermal oxidation or other methods, and is filled with a conductor 214 (for example, a doped germanium or other conductor). The gate of the trench PMOS transistor. In the substrate region between the two trenches, a well region 215 doped with an N-type impurity is formed by ion implantation (this step is performed before or after the trench is formed), and is formed on the surface of the N-type well region 215. The high concentration P+ doped region 216 constitutes the source of the trench PMOS transistor, and the back side of the substrate is the drain. In a preferred embodiment, to provide a preferred drain contact resistance, the P-type substrate 210 preferably includes a relatively high concentration of the P+ body 211 and the P-type epitaxial growth region 212. Similar to the previous embodiment, the input voltage Vin is directly connected to the N-type well region 215 in addition to the P+-type doping region 216 of the PMOS transistor 24, and the input voltage Vin is directly connected to the N-type well region 215. An ohmic contact is not provided, making it equal to a Schottky diode. In this embodiment, the P+ doping region 216 serves as the source of the PMOS transistor 24 on the one hand, and controls the reverse leakage current of the Schottky diode on the other hand.

The integrated power switching element of the present invention can be used in many places, for example as a charging switch. Referring to FIG. 5, when the battery Batt is charged from the power source VCC, one of the typical circuit structures is as shown in the figure. The control circuit 10 generates a signal Vgate according to the battery voltage Vbat and the charging current, thereby controlling the charging switch circuit 50, wherein charging The current can be obtained from the voltage across the resistor Rcs (charging current = (Isense-Vbat) / Rcs).

Figure 6 shows an embodiment of the charging switch circuit 50 constructed using the integrated power switching element 20 of the present invention. In this embodiment, the charging switch circuit 50 includes two integrated components 20A and 20B, and an NMOS transistor 52. The first integrated component 20A is coupled between the power source VCC and the battery Batt, and has a source electrically connected to the power source VCC and a drain electrically connected to the node Isense. The gate of the NMOS transistor 52 is controlled by the power source VCC, the source thereof is connected to the output Vgate of the control circuit 10, and the gate of the first integrated component 20A is gated (hereinafter will be referred to FIG. 8 for the NMOS transistor 52). Source and drain connection directions are explained). The second integrated component 20B is coupled between the gate and the drain of the first integrated component 20A, and its gate is controlled by the power source VCC. It can be seen from the above structure that in the state of charge, the power consumption from the power supply VCC to the node Isense passes through only one PMOS transistor, so the power consumption is much lower than that of the prior art of FIG.

The manner in which the charge switch circuit 50 is constructed is not limited to the above one, and Fig. 7 shows another embodiment in which the NMOS transistor 52 is replaced with a bipolar transistor 54. Also in this embodiment, the same functions as those of the embodiment of Fig. 6 can be achieved.

In the above embodiment, the integrating elements 20A and 20B may be the planar type of Fig. 3 or the grooved structure of Fig. 4. In one embodiment, the integrated component is preferably a trench type structure, and the NMOS transistor 52 is preferably a laterally diffused transistor (LDMOS), and the double carrier transistor 54 is preferably a lateral double-carrier NPN transistor. (Lnpn).

Referring to Fig. 8, the operation of the charging switch circuit 50 of the present invention will be described by taking the embodiment of Fig. 6 as an example. Assuming that the power supply VCC is 5V and the battery is full, the voltage is 4.2V: in the charging state, VCC=5V, Vgate=5V, so Vgate1=5V, the first integrated component 20A is not turned on, and I1=0. When the control circuit 10 generates a Vgate signal of 0V, VCC=5V, Vgate=0V, at this time Vgate1=0V, the first integrated component 20A is turned on, and I1 charges the battery Batt via the resistor Rcs.

After the charging is completed, after being separated from the power supply VCC, VCC=0, Vgate=0, Vbat=4.2V, at this time, the NMOS transistor 52 is not turned on but the second integrated component 20B is turned on, Vgate1=4.2V, and the first integrated component 20A is not turned on. Therefore, the reverse current IR1=IR2~0. At this time, it can be seen that when the NMOS transistor 52 is used, its source should be coupled to the node Vgate1, and the drain is coupled to the control circuit 10 to avoid the reverse current IR2 passing through the body parasitic diode of the NMOS transistor 52. It flows to the control circuit 10.

As can be seen from the above description, the power consumption of the present invention is very low, which is far superior to the prior art.

When the present invention is applied to the charge switch circuit 50, it is not absolutely necessary to integrate the Schottky diode in the PMOS transistor. Referring to Fig. 8, in the charge switch circuit 50, it is only necessary to make the IR1 unable to pass through the body of the PMOS transistor. Therefore, referring to FIG. 9, the Schottky diode 22 can be changed to the diode 32D, and the integrated component 20 is changed to a double-parasitic diode 32D having a reverse series, the PMOS transistor 30 of 24D. . Referring to Fig. 10, the PMOS transistors 30A, 30B can be used instead of the integrated components 20A, 20B of Fig. 6, and the charge switch circuit 50 can still be constructed to achieve a similar function. Of course, the circuit of Figure 7 can also be used for the same substitution.

The semiconductor structure of PMOS transistor 30 is very similar to integrated component 20, see the planar component structure of Figure 11 and the trench component structure of Figure 12. The difference between Fig. 11 and Fig. 3 is that only a single P+ type doped region 204 is provided as the source of the element, and the N-type well region 201 is floating. The P+ doping region 204 and the N-well region 201 constitute an ontoroidal diode, that is, the diode 32D in FIG. The difference between Fig. 12 and Fig. 4 is that only a single P+ type doped region 216 is provided as the source of the element, and the N-type well region 215 is floating. The P+ doping region 216 and the N-type well region 215 constitute a bulk parasitic diode, that is, the diode 32D in FIG.

The PMOS transistor 30 constructed as described above can be used as the PMOS transistors 30A, 30B in FIG. Of course, in the charging switch circuit 50 of the present invention, the integrated component 20 and the PMOS transistor 30 can also be used, that is, the first and second integrated components in FIG. 6 or FIG. 7 can be replaced only by the PMOS transistor 30. One of 20A and 20B is also within the scope of the invention.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be made by those skilled in the art, and are intended to be included within the scope of the invention.

10. . . Control circuit

12. . . Schottky diode

14. . . PMOS transistor

14D. . . Parasitic diode

20. . . Integrated power switching components

20A. . . First integrated component

20B. . . Second integrated component

twenty two. . . Schottky diode

twenty four. . . PMOS transistor

24D. . . Parasitic diode

30. . . PMOS transistor

32D. . . Parasitic diode

50. . . Charging switch circuit

52. . . Field effect transistor

54‧‧‧Double carrier transistor

201‧‧‧N type well area

202‧‧‧ gate

203‧‧‧P+ doped area

204‧‧‧P+ doped area

205‧‧‧P+ doped area

210‧‧‧P type substrate

211‧‧‧P+ type ontology

212‧‧‧P-type epitaxial growth zone

213‧‧‧ gate oxide layer

214‧‧‧ gate

215‧‧‧N type well area

216‧‧‧P+ doped area

Figure 1 shows a prior art power switching element comprising a separate PMOS transistor and a separate Schottky diode.

Figure 2 shows an embodiment of the invention in circuit diagram form.

Figure 3 shows one of the embodiments of the present invention when implemented in a semiconductor.

Fig. 4 shows another embodiment of the present invention when implemented in a semiconductor.

Fig. 5 shows a typical circuit structure for charging a battery.

Figure 6 illustrates an embodiment of a charge switch circuit constructed using the integrated power switching elements of the present invention.

Figure 7 illustrates another embodiment of a charge switch circuit constructed using the integrated power switching elements of the present invention.

Figure 8 illustrates that the charge switch circuit of the present invention has only very low power consumption.

Figure 9 shows another power switching element that can be used in the charge switch circuit of the present invention.

Fig. 10 shows another embodiment of the charge switch circuit of the present invention.

Fig. 11 shows an embodiment in which the PMOS transistor in Fig. 9 is implemented as a semiconductor.

Fig. 12 shows another embodiment in the case where the PMOS transistor in Fig. 9 is implemented as a semiconductor.

10. . . Control circuit

20. . . Integrated power switching components

twenty two. . . Schottky diode

twenty four. . . PMOS transistor

24D. . . Parasitic diode

Claims (12)

A charging switch circuit is coupled between a power source and a battery to be charged, the charging switch circuit comprising: first and second integrated components, and a transistor for controlling the first integrated component, wherein each integrated component comprises: a PMOS transistor comprising a gate region between a gate, a source, a drain and a source drain, the source, the drain and the channel region being located in a substrate, and a parasitic region is formed between the drain and the channel a polar body; and a Schottky diode in reverse series with the parasitic diode, the Schottky diode being located in the substrate, one end of which is connected to the parasitic diode, and the other end is connected to the source The first integrated component is coupled between the power source and the battery, the source is coupled to the power source, the drain is coupled to the battery, and the second integrated component is coupled to the gate and the drain of the first integrated component The source is coupled to the gate of the first integrated component, the drain is coupled to the drain of the first integrated component, the gate is controlled by the power source, and the first end of the transistor controlling the first integrated component is Controlled by the power supply, the second end receives control of the control of the first integrated component The third end controls the gate of the first integrated component. The charging switch circuit of claim 1, wherein the transistor for controlling the first integrated component is an NMOS transistor, the gate thereof is controlled by the power source, and the source receives the control signal for controlling the first integrated component, The pole controls the gate of the first integrated component. The charging switch circuit of claim 2, wherein the NMOS transistor is a lateral diffusion transistor (LDMOS). The charging switch circuit of claim 1, wherein the transistor for controlling the first integrated component is a bipolar transistor, the base of which is controlled by a power source, The collector receives the control signal of the first integrated component, and the emitter controls the gate of the first integrated component. The charging switch circuit of claim 4, wherein the bipolar transistor is a lateral bipolar NPN transistor (Lnpn). The charging switch circuit of claim 1, wherein the first and second integrated components are of a trench structure. A charging switch circuit is configured to be coupled between a power source and a battery to be charged, the charging switch circuit comprising: a first PMOS transistor comprising a channel region between the gate, the source, the drain and the source drain, The source, the drain and the channel region are located in a substrate, and a first parasitic diode is formed between the source and the channel region, and a second parasitic diode is formed between the drain and the channel region, and the first parasitic two The pole body is reversely connected in series with the second parasitic diode; the second PMOS transistor includes a channel region between the gate, the source, the drain and the source drain, and the source, the drain and the channel region are located at a third parasitic diode is formed in the base body and the channel region, and a fourth parasitic diode is formed between the drain and the channel region, and the third parasitic diode and the fourth parasitic diode are opposite And a transistor for controlling the first PMOS transistor gate; wherein, the first PMOS transistor is coupled between the power source and the battery, the source is coupled to the power source, and the drain is coupled to the battery; The second PMOS transistor is coupled between the gate and the drain of the first PMOS transistor, and the source thereof a gate of the PMOS transistor is coupled, the drain is coupled to the drain of the first PMOS transistor, the gate is controlled by the power source; and the first end of the transistor controlling the first PMOS transistor is controlled by the power source, The second end receives the control signal for controlling the first PMOS transistor, The third end controls the gate of the first PMOS transistor. The charging switch circuit of claim 7, wherein the transistor for controlling the first PMOS transistor is an NMOS transistor, the gate thereof is controlled by the power source, and the source receives the control signal for controlling the first PMOS transistor. The drain controls the gate of the first PMOS transistor. The charging switch circuit of claim 8, wherein the NMOS transistor is a lateral diffusion transistor (LDMOS). The charging switch circuit of claim 7, wherein the transistor for controlling the first PMOS transistor is a bipolar transistor, the base of the transistor is controlled by a power source, and the collector receives and controls the first PMOS transistor. The control signal, the emitter controls the gate of the first PMOS transistor. The charging switch circuit of claim 10, wherein the bipolar transistor is a lateral bipolar NPN transistor (Lnpn). The charging switch circuit of claim 7, wherein the first and second PMOS transistors are of a trench structure.