CN112865531A

CN112865531A - Step-down converter circuit, integrated chip, integrated circuit and step-down conversion method

Info

Publication number: CN112865531A
Application number: CN202110040743.1A
Authority: CN
Inventors: 包佳正; 陈居富; 王志华
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-06-22
Filing date: 2019-06-21
Publication date: 2021-05-28
Also published as: CN110635687B; CN110635687A

Abstract

The present disclosure provides a buck converter circuit and a buck conversion method. In some embodiments, a buck converter circuit includes a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a node at which a source/drain terminal of the first switching device is electrically coupled to a source/drain terminal of the second switching device. The controller is configured to alternate the first switching device between on and off, and is further configured to alternate the second switching device between on and off. When the second switching device is turned on, the first switching device is turned off. The first switching device is partially turned on immediately before or after the second switching device is transitioned between on and off.

Description

Step-down converter circuit, integrated chip, integrated circuit and step-down conversion method

The invention is a divisional application of an invention patent application with application number 201910543322.3 and invention name buck converter circuit and buck conversion method, which is proposed by 21.6.2019.

Technical Field

The present invention relates to a buck converter circuit and a buck conversion method, and more particularly, to a buck converter circuit and a buck conversion method for reducing conduction loss in dead time.

Background

A buck converter is a dc-to-dc power converter that steps down the voltage (and steps up the current) from its input to its output. A buck converter is a type of switching converter that includes at least two semiconductor devices and at least one energy storage element. For example, a buck converter may include two transistors and an inductor. Switching converters are more efficient, especially compared to linear regulators, so that switching converters are often used within integrated circuits.

Disclosure of Invention

According to an embodiment of the present disclosure, a buck converter circuit includes a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a node at which the first source/drain of the first switching device is electrically coupled to the first source/drain of the second switching device. The controller is configured to alternate the first switching device between on and off, and is further configured to alternate the second switching device between on and off. When the second switching device is turned on, the first switching device is turned off. The first switching device is partially turned on immediately before or after the second switching device is transitioned between on and off.

According to an embodiment of the present disclosure, a buck converter circuit includes a first switching device, a second switching device, an inductor, a loss prevention circuit, and a controller. The first switching device and the second switching device are coupled with the inductor at a node. The controller is configured to apply the first and second pulse trains to the gate terminals of the first and second switching devices, respectively, to cause the first and second switching devices to alternate between the first and second states. A loss prevention circuit electrically coupled to the gate terminals of the first and second switching devices and configured to provide a voltage bias to the gate terminal of the first switching device that is less than a threshold voltage of the first switching device when transitioning between the first and second states.

According to an embodiment of the present disclosure, a buck conversion method includes: applying a first pulse train to the first switching device to cause the first switching device to alternate between on and off; applying a second pulse train to the second switching device to cause the second switching device to alternate between on and off, wherein when the first switching device is on, the second switching device is off, and when the second switching device is on, the first switching device is off; charging the inductor by a node at which the respective source/drain regions of the first and second switching devices are electrically coupled, wherein the charging is performed when the second switching device is turned on; discharging the inductor when the second switching device is open; and biasing the gate of the first switching device with a voltage less than a threshold voltage of the first switching device immediately after detecting that the first pulse train is low and the second pulse train is high.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A illustrates a circuit diagram of some embodiments of a buck converter circuit including a conduction loss reduction circuit.

FIG. 1B shows a circuit diagram of various alternative embodiments of the circuit diagram of FIG. 1A.

Fig. 2 illustrates a cross-sectional view of some embodiments of a buck converter circuit including a conduction loss reduction circuit.

Fig. 3 illustrates a timing diagram of some embodiments of the operation of a buck converter circuit including the conduction loss reduction circuit from fig. 1A, 1B, or 2.

FIG. 4 shows a graph illustrating Current-Voltage (IV) characteristics for some embodiments of intrinsic diodes within a first switching device of a buck converter circuit according to the present disclosure.

Fig. 5-9 use non-limiting example voltages and currents to illustrate circuit diagrams of the buck converter circuit of fig. 2 in various states.

Fig. 10 illustrates a block diagram of some embodiments of a method of using a buck converter circuit including a conduction loss reduction circuit.

Description of the reference numerals

100a, 100b, 500, 600, 700, 800, 900: a circuit diagram;

102. q1: a first switching device;

102 a: a first intrinsic body diode;

104: a reference node;

106. VLX: a first node;

108. q2: a second switching device;

108 a: a second intrinsic diode;

110. VDD: a power source;

112: an inductor;

114. vout: a second node;

116: a load;

118: a capacitor;

120: a controller;

122. VGL, VGL 2: a first pulse wave;

124: a low side gate driver circuit;

126. VGH: a second pulse wave;

128: a high-side gate driver circuit;

130: a conduction loss reduction circuit;

132. VGL 1: a staircase pulse wave;

134. VDD 5V: a second power supply;

136: a resistor;

138: a level shifter;

140. m1: a fifth transistor;

141: a filter;

142: a high side power supply;

144: a first transistor;

146: a second transistor;

150: a second plurality of filters;

152: a low side power supply;

154. m2: a third transistor;

156: a fourth transistor;

160: a sixth transistor;

200: a cross-sectional view;

202: a gate electrode;

203: a resist protective oxide layer;

204: a sidewall spacer;

206: a gate dielectric;

208: a second source/drain region;

210: lightly doping the N-type region;

212: a high voltage P-type implant region;

214: n-type drain drift;

216: a deep P well;

218: an N-buried layer;

220: a substrate;

221: a shallow P well;

222: a shallow N well;

224: an isolation structure;

226: a first contact area;

228: a second contact area;

230: a third contact area;

232: a first source/drain region;

242: a third current path;

244: a second current path;

246: a first current path;

250: an NPN transistor;

252: an internal diode;

260. PVDD: a third power supply;

300: a timing diagram;

302: a first time frame;

304: a second time frame;

306: a third time frame;

308: a fourth time frame;

310: a fifth time frame;

312: a first pulse wave profile;

314: a second pulse wave profile;

316: a third pulse wave profile;

318: a first control signal profile;

320: a second control signal profile;

322: a first node voltage profile;

322 a: a first voltage line;

322 b: a second voltage line;

324: an inductor current profile;

400: IV curve;

502: a first position;

1000: a block diagram;

1002. 1004, 1006, 1008, 1010, 1012: an action;

GND: a reference voltage;

i₁: a first average current;

i₂: a second average current;

i₃: a third current;

i₄: a fourth current;

i_b: a base current;

i_c: collector current;

i_d: an intrinsic diode current;

i_e: an emitter current;

i_L: an inductor current;

i_Q1: a first switching current;

i_Q2: a second switching current;

t: time;

t₀: an initial time;

t₁: a first time;

t₂: a second time;

t₃: a third time;

t₄: a fourth time;

t₅: a fifth time;

vcontrol 1: a first control signal;

vcontrol 2: a second control signal;

V_f1: a first forward bias voltage;

V_f2: a second forward bias.

Detailed Description

The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and similar terms, may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The buck converter may include a p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and an n-type MOSFET electrically coupled to an inductor at a first node. The n-type MOSFET is gated with a first input signal supplied by a low-side gate driver of the control circuit. The p-type MOSFET is gated with a second input signal supplied by a low-side gate driver of the control circuit. The source of the p-type MOSFET is electrically coupled to a power source of the first voltage domain, and the source of the n-type MOSFET is electrically coupled to a reference node (e.g., ground). The control circuit supplies a first input signal and a second input signal to cause the p-type MOSFET and the n-type MOSFET to alternate between being turned on and off. When the n-type MOSFET is turned on, the p-type MOSFET is turned off, thereby defining a first state. When the n-type MOSFET is off, the p-type MOSFET is on, thereby defining a second state. Depending on which of the n-type MOSFET and the p-type MOSFET is in the on-state, the inductor is charged or discharged. Dead-time (dead-time) segments occur immediately before and after the transition from the first state to the second state, or vice versa. The control circuit ensures that both the n-type MOSFET and the p-type MOSFET are turned off during the dead time period. The dead time period ensures that the power supply does not short to ground when transitioning between the first state and the second state. A challenge of buck converters is the conduction power loss during the dead time period.

During the dead time period, the body diode in the n-type MOSFET is forward biased, whereby current flows through the body diode. The current flowing through the body diode will trigger a parasitic NPN power loss in the substrate between the power supply terminal and the drain of the N-type MOSFET. Thus, a method for overcoming the conduction power loss may be to reduce the elapsed time that the buck converter remains within the dead time period. Reducing the elapsed time in the dead time period will result in less power loss because less time will be consumed by the current flowing through the body diode. However, reducing the elapsed time too much may result in an inability to protect the power supply from shorting to the reference node when transitioning between the first and second states.

Various embodiments of the present disclosure are directed to buck converters including a conduction loss prevention circuit configured to reduce a voltage of a body diode of an n-type MOSFET. In some embodiments, the conduction loss prevention circuit includes a transistor, a pull-up resistor, and a level shifter. The first source/drain region of the transistor is electrically coupled to the reference node, and the second source/drain region is electrically coupled to the gate terminal of the n-type MOSFET. A pull-up resistor is electrically coupled from a second power source of the second voltage domain to the gate terminal of the n-type MOSFET. The level shifter is electrically coupled from the gate terminal of the p-type MOSFET to the gate terminal of the transistor. The conduction loss prevention circuit is configured to bias the gate terminal of the n-type MOSFET with a voltage less than a threshold voltage of the n-type MOSFET during the dead time period. A weak inversion current flows through a conduction channel formed in an n-type MOSFET. The weak reverse current is in parallel with the current flowing through the body diode, thereby effectively reducing the voltage of the body diode and reducing the conduction power loss in the buck converter.

Referring to fig. 1A, a circuit diagram 100a of some embodiments of a buck converter circuit is provided. The first switching device 102 (e.g., Q1) has a first source/drain terminal electrically coupled to a reference node 104 (e.g., ground) and further has a second source/drain terminal electrically coupled to a first node 106 (e.g., VLX). In some embodiments, the first switching device 102 includes a first intrinsic body diode 102a electrically coupled between the first source/drain terminal and the second source/drain terminal. The second switching device 108 (e.g., Q2) has a third source/drain terminal electrically coupled to the first node 106, and further has a fourth source/drain terminal electrically coupled to a power source 110 (e.g., VDD). In some embodiments, the second switching device 108 includes a second intrinsic diode 108a electrically coupled between the third source/drain terminal and the fourth source/drain terminal. The first and

second switching devices

102, 108 may be, for example, metal-oxide-semiconductor field effect transistors (MOSFETs), some other suitable metal-oxide-semiconductor (MOS) device, or some other suitable insulated-gate field-effect-transistor (IGFET). In some embodiments, the first switching device 102 is an n-channel MOS device and the second switching device 108 is a p-channel MOS device. In some embodiments, the first switching device 102 is a p-channel MOS device and the second switching device 108 is an n-channel MOS device. The power supply 110 may be, for example, a Direct Current (DC) voltage source and/or may, for example, apply 5 volts, 6 volts, 12 volts, or some other suitable voltage to the fourth source/drain terminal of the second switching device 108.

The inductor 112 is electrically coupled from the first node 106 to a second node 114 (e.g., Vout), and the load 116 is electrically coupled from the second node 114 to the reference node 104. In some embodiments, a capacitor 118 is also electrically coupled from the second node 114 to the reference node 104. During use of the buck converter circuit, the inductor 112 charges when the second switching device 108 is in an on state and discharges when the second switching device 108 is in an off state. Similarly, the capacitor 118 is charged when the second switching device 108 is in an on state and discharged when the second switching device 108 is in an off state.

The controller 120 (e.g., dead-time control) is configured to generate a first pulse wave (or train) 122 (e.g., VGL) provided to the gate of the first switching device 102. In some embodiments, the first pulse wave 122 is provided to the gate of the first switching device 102 via a low side gate driver circuit 124. The first pulse wave 122 causes the first switching device 102 to alternately switch between an on state and an off state. For example, where the first switching device 102 is an n-channel MOS device, the first switching device 102 may be in an on state at each pulse and may be in an off state between pulses. In addition, the controller 120 is configured to generate a second pulse wave (or train) 126 (e.g., VGH) that is provided to the gate of the second switching device 108. In some embodiments, the second pulse wave 126 is provided to the gate of the second switching device 108 via a high-side gate driver circuit 128. The second pulse wave 126 causes the second switching device 108 to alternately switch between an on state and an off state. For example, where the second switching device 108 is a p-channel MOS device, the second switching device 108 may be in an off state at each pulse and may be in an on state between pulses. In some embodiments, the duty cycle of the second pulse wave 126 is greater than the duty cycle of the first pulse wave 122, the second pulse wave 126 has a phase offset with respect to the first pulse wave 122, the frequency of the second pulse wave 126 is the same as the frequency of the first pulse wave 122, or any combination of the foregoing.

The high-side gate driver circuit 128 includes a plurality of filters 141, a high-side power supply 142, a first transistor 144, and a second transistor 146. The plurality of filters 141 are electrically coupled between the first output of the controller 120 and the gate terminals of the first transistor 144 and the second transistor 146. A first source/drain terminal of the first transistor 144 is electrically coupled to the gate of the second switching device 108. A first source/drain terminal of the second transistor 146 is electrically coupled to the high-side power source 142, and a second source/drain terminal of the second transistor 146 is electrically coupled to the gate of the second switching device 108. In some embodiments, the first transistor 144 is an n-type MOS device and the second transistor 146 is a p-type MOS device, or vice versa.

The low side gate driver circuit 124 includes a second plurality of filters 150, a low side power supply 152, a third transistor 154 (e.g., M2), and a fourth transistor 156. The second plurality of filters 150 is electrically coupled between the second output of the controller 120 and the gate terminals of the third transistor 154 and the fourth transistor 156. A first source/drain terminal of the third transistor 154 is electrically coupled to the gate of the first switching device 102. A first source/drain terminal of the fourth transistor 156 is electrically coupled to the low side power 152 and a second source/drain terminal of the fourth transistor 156 is electrically coupled to the gate of the first switching device 102. In some embodiments, the third transistor 154 is an n-type MOS device and the fourth transistor 156 is a p-type MOS device, or vice versa.

In some embodiments, the high-side power supply 142 supplies a high voltage relative to the low-side power supply 152. For example, in some embodiments, the high-side power supply 142 may supply 20 volts or greater than 20 volts, while the low-side power supply 152 may supply 5 volts or less than 5 volts. However, other voltages may be used. Furthermore, in some embodiments, the high-side power supply 142 is the same as the power supply 110. The high-side power supply 142 and the low-side power supply 152 may be, for example, DC power supplies or some other suitable power supply.

The first pulse wave 122 and the second pulse wave 126 are generated such that the first switching device 102 is not turned on at the same time as the second switching device 108. Turning on the first switching device 102 simultaneously with the second switching device 108 may electrically short the power supply 110 to the reference node 104, which may damage and/or destroy the power supply 110. The first switching device 102 is therefore not turned on at the same time as the second switching device 108, and the first pulse wave 122 is coordinated with the second pulse wave 126 so that there is a dead time (or transient) period immediately before and immediately after each pulse of the first pulse wave 122. During the dead time period, the first pulse wave 122 and the second pulse wave 126 are generated, and thus the first switching device 102 and the second switching device 108 are turned off.

In some embodiments where the first switching device 102 is an n-channel MOS device and the second switching device 108 is a p-channel MOS device, the dead time period is generated by: 1) generating a first pulse wave 122 and a second pulse wave 126 having the same frequency; 2) generating a second pulse wave 126 having a larger duty cycle than the first pulse wave 122; and 3) introducing a phase shift into the first pulse wave 122 or the second pulse wave 126 such that each pulse of the first pulse wave 122 is centered on a corresponding pulse of the second pulse wave 126 or substantially centered on a corresponding pulse of the second pulse wave 126. In these embodiments, a dead time period is generated in which the second pulse wave 126 is high and the first pulse wave 122 is low. For example, the dead time period may occur immediately before the second pulse wave 126 transitions from high to low (i.e., immediately before the falling edge of the second pulse wave 126). As another example, the dead time period may occur immediately after the low-to-high transition of the second pulse wave 126 (i.e., immediately after the rising edge of the second pulse wave 126).

If both the first switching device 102 and the second switching device 108 are completely off during the dead time period, then conduction power losses may occur due to the current from the inductor 112 traveling through the first intrinsic body diode 102a of the first switching device 102 to the reference node 104. The current flowing through the first intrinsic body diode 102a of the first switching device 102 triggers additional conduction power loss through an NPN junction (not shown) in the substrate (not shown) between the power supply 110 and the first node 106. A conduction loss reduction circuit 130, such as a loss prevention circuit, is electrically coupled to the gate of the first switching device 102 to reduce or eliminate conduction power loss.

The conduction loss reduction circuit 130 includes a second power supply 134 (e.g., VDD5V), a resistor 136, a level shifter 138, and a fifth transistor 140 (e.g., M1). The resistor 136 is electrically coupled between the second power source 134 and the gate of the first switching device 102. The fifth transistor 140 has a fifth source/drain terminal electrically coupled to the reference node 104, a sixth source/drain terminal electrically coupled to the gate of the first switching device 102, and a gate terminal electrically coupled to the level shifter 138. The level shifter 138 is electrically coupled between the gate of the second switch device 108 and the gate of the fifth transistor 140. The second power source 134 may be, for example, a Direct Current (DC) voltage source, and/or may apply, for example, 5 volts, 6 volts, 12 volts, or some other suitable voltage to the resistor 136. The fifth transistor 140 may be, for example, a MOSFET, some other suitable MOS device, or some other suitable IGFET. In some embodiments, the fifth transistor 140 is an n-channel MOS device or a p-channel MOS device. In some embodiments, the low side power supply 152 is the same as the second power supply 134 and/or the second power supply 134 supplies a voltage that is less than the voltage of the power supply 110.

The conduction loss reduction circuit 130 monitors the dead time period and biases the gate of the first switching device 102 during the dead time period so the first switching device 102 is partially turned on. In some embodiments, the bias voltage applied to the gate of the first switching device 102 may be adjusted by the resistance value of the resistor 136, the voltage value on the fifth transistor 140 (e.g., M1) when operating in the on state, the voltage value on the third transistor 154 (e.g., M2) when operating in the on state, or any combination of the foregoing. By partially on, it is meant that the voltage of the gate of the first switching device 102 is biased at a voltage that is less than the threshold voltage of the first switching device 102. As a result, the gate of the first switching device 102 is driven by a staircase-shaped pulse wave 132 (e.g., VGL), which is a combination of the first pulse wave 122 and the bias voltage from the conduction loss reduction circuit 130. By causing the first switching device 102 to become partially on during the dead time period, current from the inductor 112 may travel to the reference node 104 through both the first intrinsic body diode 102a of the first switching device 102 and the selectively conductive channel of the first switching device 102. This has the effect of reducing conduction power losses. For example, two parallel paths may reduce the overall resistance value from the inductor 112 to the reference node 104, which may reduce the forward bias of the first intrinsic body diode 102a and thereby reduce power loss. In addition, because the first switching device 102 is only partially on, the power supply 110 does not suffer damage due to an electrical short to the reference node 104.

Referring to fig. 1B, a circuit diagram 100B of some alternative embodiments of the circuit diagram of fig. 1A is provided, wherein the level shifter 138 is omitted and the conduction loss reduction circuit 130 includes a sixth transistor 160 in place of the resistor 136. A first source/drain terminal of the sixth transistor 160 is electrically coupled to the reference node 104, and a second source/drain terminal of the sixth transistor 160 is electrically coupled to the gate of the first switching device 102. A first source/drain terminal of the fifth transistor 140 is electrically coupled to the second power source 134, and a second source/drain terminal of the fifth transistor 140 is electrically coupled to the gate of the first switching device 102. The gate terminals of the fifth transistor 140 and the sixth transistor 160 are electrically coupled between the plurality of filters 141 and the gate terminals of the first transistor 144 and the second transistor 146. In some embodiments, the fifth transistor 140 is a p-type MOS device and the sixth transistor 160 is an n-type MOS device, or vice versa. A first control signal Vcontrol1 is defined between the plurality of filters 141 and the gate terminals of the first transistor 144 and the second transistor 146. A second control signal Vcontrol2 is defined between the second plurality of filters 150 and the gate terminals of the third and

fourth transistors

154, 156.

Referring to fig. 2, a cross-sectional view 200 of some embodiments of a buck converter circuit is provided. In some embodiments, the cross-sectional view 200 represents an additional embodiment of the circuit 100a according to fig. 1A. Connections are present between the substrate 220 and the terminals and/or nodes. Although not shown, the connection between the substrate 220 and the terminals and/or nodes may be achieved, for example, by a back-end-of-line (BEOL) interconnect structure overlying the substrate 220. Substrate 220 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, substrate 220 is P-type or N-type.

An N-buried layer (NBL) 218 is formed within the substrate 220 directly below the deep P-well (DPW) 216, the shallow N-well (SHN) 222, and the shallow P-well (SHP) 221. An N-type drain drift (NDD) 214 is formed directly above the DPW 216. Isolation structures 224 extend into the upper or top surface of substrate 220 to provide electrical isolation between source/drains and contact regions within substrate 220. In some embodiments, the isolation structure 224 comprises multiple sections each comprising a dielectric material, and/or is a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI) structure, or some other suitable isolation structure.

The first contact region 226 includes a P-type dopant and has a high doping concentration relative to the substrate 220. The first contact region 226 provides electrical coupling to the substrate 220, and the substrate 220 includes a P-type dopant. The second contact region 228 (e.g., NBL pickup ring) comprises an N-type dopant and has a high doping concentration relative to the SHN 222. The second contact region 228 provides electrical coupling to the SHN 222 and NBL 218. The second contact region 228 is electrically coupled to the power source 110. The third contact region 230, such as a reference or ground pickup ring (pickup ring), includes P-type dopants and has a high doping concentration relative to the SHP 221. The third contact region 230 provides electrical coupling with the SHP 221. The third contact region 230 is electrically coupled to the reference node 104.

The first switching device 102 includes a gate electrode 202, a gate dielectric 206, a first source/drain region 232, a second source/drain region 208, a high voltage P-type implanted (HVPB) region 212, an NDD214, and a sidewall spacer 204. The gate electrode 202 overlies the gate dielectric 206 and is electrically coupled to the low side gate driver (124 of fig. 1A) and the conduction loss reduction circuit (130 of fig. 1A) such that a first pulse train (e.g., VGL) is applied to the gate electrode 202. The sidewall spacer 204 includes two segments such that the gate electrode 202 is sandwiched between the two segments. A resist protective oxide layer 203 is disposed over one of the two sections of sidewall spacers 204, a portion of the gate electrode 202, and a portion of the gate dielectric 206. A second source/drain region 208 is disposed on a first side of the gate electrode 202 and is sandwiched between two lightly doped N-type regions 210. Second source/drain region 208 comprises an N-type dopant and has a high doping concentration relative to lightly doped N-type region 210. The second source/drain region 208 abuts the HVPB region 212. The second source/drain region 208 is electrically coupled to the reference node 104. A first source/drain region 232 is disposed on a second side of the gate electrode 202 and directly contacts a section of the isolation structure 224. First source/drain region 232 is laterally offset from the second side of gate electrode 202. The first source/drain region 232 includes an N-type dopant and has a higher doping concentration than the NDD 214. The first source/drain region 232 provides electrical coupling to the NDD 214. The first source/drain region 232 is electrically coupled to the first node 106.

A third source/drain terminal of the second switching device 108 is electrically coupled to the first node 106, and a fourth source/drain terminal of the second switching device 108 is electrically coupled to a third power supply 260 (e.g., PVDD). In some embodiments, the power supply 110 is the same as the third power supply 260. The low side gate driver circuit (124 of fig. 1A) and the conduction loss reduction circuit (130 of fig. 1A) are electrically coupled to the gate electrode of the second switching device 108 such that the first pulse wave (e.g., VGH) is applied to the gate electrode of the second switching device 108.

A first internal NPN junction exists between the SHN 222, the SHP221, and the NDD 214. Under certain operating conditions, the first internal NPN junction functions as an NPN transistor 250, with a first current path 246 existing along the NPN transistor 250 between the second contact region 228 and the first source/drain region 232. The second contact regions 228 and the SHN 222 serve as collectors of the NPN transistor 250, the third contact regions 230 and the SHP221 serve as bases of the NPN transistor 250, and the first source/drain regions 232 and the NDD214 serve as emitters of the NPN transistor 250. An internal diode 252 of the NPN transistor 250 is present between the SHP221 and the NDD214, directing current toward the NDD 214. When the voltage at the emitter of NPN transistor 250 is less than the voltage at the base of NPN transistor 250 and the voltage at the collector of NPN transistor 250 is greater than the voltages at the emitter and base of NPN transistor 250, NPN transistor 250 turns on and current will conduct through first current path 246. It can be appreciated that NPN transistor 250 is drawn for convenience, the actual NPN junction functions as NPN transistor 250 and the current does not have to follow the path of NPN transistor 250 as shown.

The first intrinsic body diode 102a of the first switching device 102 is positioned between the HVPB region 212 and the NDD214 under the second source/drain region 208. Under certain operating conditions, the first intrinsic body diode 102a is forward biased and current flows along the second current path 244 from the second source/drain region 208 to the first source/drain region 232. Under certain operating conditions, such as during a triode mode or sub-threshold mode, the first switching device 102 is turned on or partially turned on, respectively, and current flows between the second source/drain region 208 and the first source/drain region 232 along the third current path 242. In some embodiments, the third current path 242 represents a conductive channel formed between the second source/drain region 208 and the first source/drain region 232. In some embodiments, the second current path 244 is in parallel with the third current path 242 when the first switching device 102 is partially on and the second switching device 108 is off. The parallel path between the second current path 244 and the third current path 242 has the effect of reducing conduction power loss.

During operation of the first switching device 102, when a voltage value higher than a threshold voltage of the first switching device 102 is applied to the gate electrode 202, then the first switching device 102 operates in a triode mode and is considered to be on, a conductive channel is formed within the HVPB region 212 such that majority carriers (e.g., electrons) flow from the second source/drain region 208 to the first source/drain region 232 along the third current path 242. If the voltage value applied to the gate electrode 202 is less than the threshold voltage of the first switching device 102, the first switching device 102 operates in a partially on mode, a sub-threshold mode, or a weak inversion mode, a smaller conductive channel will be formed within the HVPB region 212 such that majority carriers (e.g., electrons) flow from the second source/drain region 208 to the first source/drain region 232 along the third current path 242. The current through the small conducting channel will increase as the voltage value increases to the threshold voltage. However, when operating in the weak inversion mode, the small conduction channel causes less current to flow than a conduction channel formed in the triode mode.

Referring to fig. 3, a timing diagram 300 of some embodiments of the buck converter circuits according to fig. 1A, 1B, and 2 operate. Timing diagram 300 provides one example of operating conditions that apply to a buck converter circuit. It should be appreciated, however, that other operating conditions may apply, with the timing diagram 300 being merely an example. The first pulse wave graph 312 shows the second pulse wave VGH (126 of fig. 1A). The second pulse wave plot 314 shows a staircase-shaped pulse wave VGL1 (VGL or 132 of fig. 1A). The third pulse wave plot 316 illustrates an additional embodiment of the first pulse wave VGL2 (e.g., 122 of fig. 1A). The third pulse wave plot 316 shows a first pulse wave VGL2 (122 of fig. 1A) applied to the gate of a first switching device (102 of fig. 1A) of a buck converter without the conduction loss reduction circuit (130 of fig. 1A), where the first switching device (102 of fig. 1A) remains open during the dead time period. The first control signal graph 318 illustrates a first control signal Vcontrol 1. Second control signal graph 320 illustrates a second control signal Vcontrol 2. Inductor current plot 324 shows current i through the inductor (112 of FIG. 1A)_L。

The first node voltage graph 322 shows a voltage value at the first node VLX (106 of fig. 1A) during operating conditions of the buck converter circuit. The first node voltage graph 322 shows a first voltage line 322a corresponding to the voltage at the first node VLX (106 of fig. 1A) due to the staircase-shaped pulse wave VGL 1. The second voltage line 322b corresponds to the first node VLX (106 of fig. 1A) caused by the first pulse wave VGL2Additional embodiments of voltages. During the dead time period associated with the staircase pulse wave VGL1, a first forward bias voltage V is applied_f1Is applied over the first intrinsic body diode (102 a of figure 1A). During the dead time period associated with the first pulse wave VGL2, the second forward bias voltage V is applied_f2Applied to the first intrinsic body diode (102 a of fig. 1A) of a buck converter without the conduction loss reduction circuit (130 of fig. 1A). A first forward bias voltage V_f1Is less than the second forward bias voltage V_f2. In some embodiments, the first forward bias voltage V_f1Is more than the second forward bias voltage V_f2Approximately 50 percent smaller. Second forward bias voltage V_f2To a first forward bias voltage V_f1Has the effect of reducing the conduction power loss. In some embodiments, the first forward bias voltage V_f1In the range of approximately-0.3 volts to approximately-0.9 volts. In some embodiments, the second forward bias voltage V_f2In the range of approximately-0.7 volts to approximately-1.9 volts.

During each time frame outlined above, the conduction loss reduction circuit (130 of fig. 1A) processes the first control signal Vcontrol1 and the second control signal Vcontrol2 to determine whether they will cause the first switching device 102 and the second switching device 108 to open, thereby creating dead time periods. If the conduction loss reduction circuit (130 of FIG. 1A) determines that a dead time period will occur, the conduction loss reduction circuit (130 of FIG. 1A) will bias the gate of the first switching device 102, thereby boosting the first pulse wave (122 of FIG. 1A) into a stepped pulse wave VGL1 (e.g., 132 of FIG. 1A), thereby partially turning on the first switching device 102.

During the first time frame 302, i.e. at an initial time t₀And immediately after a first time t₁In between, the first control signal Vcontrol1 is low (e.g., off) and the second control signal Vcontrol2 is low. VGH is high (e.g., on) and thus the second switching device (108 of fig. 1A) is off. VGL1 is high and thus the first switching device (102 of fig. 1A) is on. The voltage at the first node VLX (106 of fig. 1A) is at a first constant value and the inductor (112 of fig. 1A) is discharging. In some embodiments, the first constant value is approximately 0 volts.

At a first time t₁At this point, second control voltage Vcontrol2 goes high. During the second time frame 304, i.e. at the first time t₁And immediately after the second time t₂In between, the first control signal Vcontrol1 and the second control signal Vcontrol2 are low and high, respectively, thereby creating a first dead-band time period. Thus, the conduction loss reduction circuit (130 of fig. 1A) detects the first dead-time period and biases the voltage of the gate of the first switching device (102 of fig. 1A) to a voltage that is less than the threshold voltage of the first switching device (102 of fig. 1A). In some embodiments, the threshold voltage of the first switching device (102 of fig. 1A) is approximately 1.2 volts. In some embodiments, the gate of the first switching device (102 of FIG. 1A) is biased at a voltage of approximately 0.8 volts. Thus, the device is partially on and the third power supply 260 will not short to the reference node 104. Therefore, VGL1 is partially high and the first switching device (102 of fig. 1A) is partially on. The voltage at the first node VLX (106 of fig. 1A) is at a second constant value and the inductor (112 of fig. 1A) is discharging. In some embodiments, the second constant value is negative and/or less than the first constant value. First average current i₁Conducting through the inductor (112 of fig. 1A) during the first dead time period. First dead time conduction loss P₁Is equal to P₁＝V_f1*i₁。

At a second time t₂At this point, first control voltage Vcontrol1 goes high. At a second time t₂And immediately after a third time t₃During the third time frame 306 in between, the first control signal Vcontrol1 and the second control signal Vcontrol2 are high. VGH is low and thus the second switching device (108 of fig. 1A) is on. VGL1 is low and thus the first switching device (102 of fig. 1A) is open. The voltage at the first node VLX (106 of fig. 1A) increases rapidly at the beginning of the third time frame 306 and settles to a constant value for the remainder of the third time frame 306. The inductor (112 of fig. 1A) charges within a third time frame 306. The voltage at the first node VLX is greater than the first forward bias voltage V during the third time frame 306_f1。

At a third time t₃At a first control voltage Vcontrol1 becomes low. At a third time t₃And immediately after a fourth time t₄During the fourth time frame 308 in between, the first control signal Vcontrol1 and the second control signal Vcontrol2 are low and high, respectively, resulting in a second dead time period. Thus, the conduction loss reduction circuit (130 of fig. 1A) detects the second dead-time period and biases the gate of the first switching device (102 of fig. 1A) at a voltage that is less than the threshold voltage of the first switching device (102 of fig. 1A). Therefore, VGL1 is partially high and the first switching device (102 of fig. 1A) is partially on. VGH is high and thus the second switching device (108 of fig. 1A) is open. During an initial time of the fourth time frame 308, the voltage at the first node VLX (106 of fig. 1A) decreases to a second constant value, and the inductor (112 of fig. 1A) is discharging. In some embodiments, the second constant value is negative and/or less than the first constant value. Second average current i₂Conducting through the inductor (112 of fig. 1A) during a second dead time period. Second dead time conduction loss P₂Is equal to P₂＝V_f1*i₂。

At a fourth time t₄At this point, second control voltage Vcontrol2 goes low. At a fourth time t₄And immediately after a fifth time t₅During the fifth time frame 310 in between, the first control signal Vcontrol1 and the second control signal Vcontrol2 are low. VGH is high and thus the second switching device (108 of fig. 1A) is open. VGL1 is high and thus the first switching device (102 of fig. 1A) is on. The voltage at the first node VLX (106 of fig. 1A) is at a first constant value and the inductor (112 of fig. 1A) is discharging.

Fig. 4 shows an IV curve 400 of an embodiment of an intrinsic diode within a first switching device of a buck converter circuit including a conduction loss reduction circuit (as previously shown and described in fig. 1A). The IV curve 400 reflects the operating characteristics of the first intrinsic body diode (102 a of fig. 1A). When a first forward bias voltage V is applied_f1When the first forward current through the first intrinsic body diode (102 a of FIG. 1A) is less than when the second forward bias voltage V is applied_f2A second forward current. Thus, the second forward bias voltage V is made_f2Down to the first forward bias voltage V_f1Power loss on the first intrinsic body diode (102 a of fig. 1A) during dead time periods of the buck converter with the conduction loss reduction circuit is reduced.

Referring to fig. 5-9, non-limiting example voltages and currents are used to provide circuit diagrams 500-900 of some embodiments of the buck converter circuit of fig. 2 in various states. Fig. 5 illustrates current flowing in a buck converter circuit in a first discharge state according to a first time frame 302 of the timing diagram 300 of fig. 3. Fig. 6 shows the current flowing in the buck converter circuit during a first dead time period of the second time frame 304 according to the timing diagram 300 of fig. 3. Fig. 7 shows the current flowing in the buck converter circuit in the charging state in a third time frame 306 according to the timing diagram 300 of fig. 3. Fig. 8 illustrates the current flowing in the buck converter circuit during the second dead time period in the fourth time frame 308 according to the timing diagram 300 of fig. 3. Fig. 9 shows the current flowing in the buck converter circuit during the second discharge state in a fifth time frame 310 according to the timing diagram 300 of fig. 3.

With specific reference to the circuit diagram 500 of fig. 5, the second switching device 108 is open and thus current does not flow between the third power supply 260 and the first node 106, effectively causing an open circuit at the first location 502. Inductor current i_LFrom inductor 112 to second node 114 and through capacitor 118 and load 116 to reference node 104. Inductor 112 induces a current i through capacitor 118 and load 116 to reference node 104_LSo that the third current i₃From the reference node 104 to the second source/drain region 208. Third current i₃Flows through the third current path 242, thereby generating a fourth current i to flow from the first source/drain region 232 to the inductor 112₄。

With specific reference to the circuit diagram 600 of fig. 6, the second switching device 108 is open and thus current does not flow between the third power supply 260 and the first node 106, effectively causing an open circuit at the first location 502. The first switching device 102 is partially turned on. In some embodiments, the power supply 110 is biased at about 20 volts and the reference node 104 is biasedBiased at about 0 volts and first node 106 is biased in a range of approximately-0.3 volts to approximately-0.9 volts. Inductor current i_LFrom inductor 112 to second node 114 and through capacitor 118 and load 116 to reference node 104. Inductor 112 induces a current i through capacitor 118 and load 116 to reference node 104_LSo that the third current i₃From the reference node 104 to the second source/drain region 208. First switch current i_Q1Through a small conductive channel formed in the first switching device 102 to the first source/drain region 232 via a third current path 242. Intrinsic diode current i_dThrough the first intrinsic body diode 102a via a second current path 244. Base current i_bFlows into the third contact region 230 along the first current path 246 through the NPN transistor 250 to the first source/drain region 232. Collector current i_cFlows into the second contact region 228 along the first current path 246 through the NPN transistor 250 to the first source/drain region 232. Base current i_bAnd collector current i_cCombined to an emitter current i_eWherein i_e＝i_b+i_c. First switch current i_Q1Intrinsic diode current i_dAnd emitter current i_eAre connected in parallel with each other, so that the fourth current i₄Equal to the sum of the aforementioned currents, where i₄＝i_Q1+i_d+i_e. First dead time conduction loss P₁Is equal to P₁＝V_f1*i₄. In some embodiments, the fourth current i₄In the range of approximately 1 milliamp to approximately 100 milliamps.

With specific reference to the circuit diagram 700 of fig. 7, the second switching device 108 is turned on and thus the second switching current i_Q2Flows between the third power supply 260 and the first node 106, thereby charging the inductor 112. The first switching device 102 is open and thus current does not flow from the first source/drain region 232 to the first node 106, effectively causing an open circuit at the second location 702. Inductor current i_LFrom inductor 112 to second node 114 and through capacitor 118 and load 116 to reference node 104. In some embodiments, the third power supply 260 is about 20 volts。

With specific reference to the circuit diagram 800 of fig. 8, the second switching device 108 is open and thus current does not flow between the third power source 260 and the first node 106, effectively causing an open circuit at the first location 502. The first switching device 102 is partially turned on. In some embodiments, the power supply 110 is about 20 volts, the reference node 104 is about 0 volts, and the first node 106 is in a range of approximately-0.3 volts to approximately-0.9 volts. Inductor current i_LFrom inductor 112 to second node 114 and through capacitor 118 and load 116 to reference node 104. Inductor 112 induces a current i through capacitor 118 and load 116 to reference node 104_LSo that the third current i₃From the reference node 104 to the second source/drain region 208. First switch current i_Q1Through a small conductive channel formed in the first switching device 102 to the first source/drain region 232 via a third current path 242. Intrinsic diode current i_dThrough the first intrinsic body diode 102a via a second current path 244. Base current i_bFlows into the third contact region 230 along the first current path 246 through the NPN transistor 250 to the first source/drain region 232. Collector current i_cFlows into the second contact region 228 along the first current path 246 through the NPN transistor 250 to the first source/drain region 232. Base current i_bAnd collector current i_cCombined to an emitter current i_eWherein i_e＝i_b+i_c. First switch current i_Q1Intrinsic diode current i_dAnd emitter current i_eAre connected in parallel with each other, so that the fourth current i₄Equal to the sum of the aforementioned currents, where i₄＝i_Q1+i_d+i_e. Second dead time conduction loss P₂Is equal to P₂＝V_f1*i₄. In some embodiments, the fourth current i₄In the range of approximately 1 milliamp to approximately 100 milliamps.

With specific reference to the circuit diagram 900 of fig. 9, the second switching device 108 is open and thus current does not flow between the third power supply 260 and the first node 106, effectively causing an open circuit at the first location 502. Inductor currenti_LFrom inductor 112 to second node 114 and through capacitor 118 and load 116 to reference node 104. Inductor 112 induces a current i through capacitor 118 and load 116 to reference node 104_LSo that the third current i₃From the reference node 104 to the second source/drain region 208. Third current i₃Flows through the third current path 242, thereby generating a fourth current i to flow from the first source/drain region 232 to the inductor 112₄。

Referring to fig. 10, a block diagram 1000 of some embodiments of a method of using the buck converter of fig. 1A is provided.

At 1002, a buck converter including a first switching device, a second switching device, and an inductor is provided and the aforementioned components are connected to a node. Fig. 1A illustrates a circuit 100a corresponding to some embodiments of act 1002.

At 1004, a first pulse train is applied to the first switching device to alternate the first switching device between on and off. Fig. 5-9 illustrate circuits 500-900 corresponding to some embodiments of act 1004.

At 1006, a second pulse train is applied to the second switching device to alternate the second switching device between on and off, the second switching device being off when the first switching device is on and the first switching device being off when the second switching device is on. Fig. 5-9 illustrate circuits 500-900 corresponding to some embodiments of act 1006.

At 1008, the inductor is charged by a node at which the respective source/drain regions of the first and second switching devices are electrically coupled, the charging performed when the second switching device is turned on. Fig. 7 illustrates a circuit 700 corresponding to some embodiments of act 1008.

At 1010, the inductor discharges when the second switching device is open. Fig. 5, 6, 8, and 9 illustrate

circuits

500, 600, 800, and 900 corresponding to some embodiments of act 1010.

At 1012, immediately after detecting that the first pulse train is low and the second pulse train is high, the gate of the first switching device is biased at a voltage less than a threshold voltage of the first switching device. Fig. 6 and 8 illustrate circuit 600 and circuit 800, corresponding to some embodiments of act 1012.

While block diagram 1000 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more of the acts depicted herein may be performed in one or more than one separate act and/or phase.

Accordingly, in some embodiments, the present disclosure relates to a buck converter including a loss prevention circuit configured to bias a switching device of the buck converter with a voltage less than a threshold of the switching device during a dead time period.

In some embodiments, the present disclosure provides a buck converter circuit, comprising: a first switching device; a second switching device; an inductor electrically coupled to a node at which a source/drain of the first switching device is electrically coupled to a source/drain of the second switching device; and a controller configured to alternate the first switching device between on and off, and further configured to alternate the second switching device between on and off, wherein the first switching device is off when the second switching device is on, and wherein the first switching device is partially on immediately before or after the second switching device transitions between on and off.

In some embodiments, when partially turned on, the voltage of the gate of the first switching device is partially turned on when biased at a voltage less than the threshold voltage of the first switching device.

In some embodiments, the first switching device is partially turned on immediately before the second switching device transitions from off to on.

In some embodiments, the first switching device is partially turned on immediately after the second switching device transitions from on to off.

In some embodiments, the controller further comprises a loss prevention circuit. The loss prevention circuit is electrically coupled to the gate terminal of the first switching device and the gate terminal of the second switching device. The loss prevention circuit is configured to determine a first time frame immediately before the second switching device transitions from off to on and determine a second time frame immediately after the second switching device transitions from on to off. The loss prevention circuit partially turns on the first switching device during the first time frame and the second time frame.

In some embodiments, the duration of the first and second time frames is defined by a period during which both the first and second switching devices are open, respectively. The first switching means is partially switched on for the entire duration.

In some embodiments, during the first time frame and the second time frame, the buck converter comprises a first current path and a second current path. The first current path is between the second source/drain of the first switching device and the node. The first current path is conducted through an internal diode of the first switching device. The second current path is between the second source/drain of the first switching device and the node. The second current path is conducted through a conductive channel formed within the first switching device. The first current path is connected in parallel with the second current path.

In some embodiments, the present disclosure provides a buck converter circuit, comprising: a first switching device; a second switching device; an inductor, wherein the first switching device and the second switching device are coupled with the inductor at a node; a controller configured to apply the first and second pulse trains to gate terminals of the first and second switching devices, respectively, to cause the first and second switching devices to alternately change between a first state and a second state; and a loss prevention circuit electrically coupled to the gate terminals of the first and second switching devices and configured to bias the gate terminal of the first switching device with a voltage less than a threshold voltage of the first switching device when transitioning between the first and second states.

In some embodiments, in the first state, the first switching device is on and the second switching device is off. In a second state, the first switching device is off and the second switching device is on.

In some embodiments, the loss prevention circuit is further configured to: detecting when the first switching device and the second switching device are in a third state, wherein the third state occurs upon transitioning from the first state to the second state or upon transitioning from the second state to the first state, and wherein the first switching device and the second switching device are open in the third state; and during a third state, enhancing the first pulse train to partially turn on the first switching device.

In some embodiments, during the third state, the buck converter includes a first current path, a second current path, and a third current path. The first current path is between the power rail and the node. The second current path is between the source/drain of the first switching device and a node. The second current path is conducted through an internal diode of the first switching device. The third current path is between the source/drain terminals and the node. The third current path is conducted through a conductive channel formed within the first switching device. The third current path is connected in parallel with the second current path.

In some embodiments, the first current path and the second current path each exist along an NPN junction within the substrate.

In some embodiments, during the third state, current flows through the first current path, the second current path, and the third current path.

In some embodiments, the first switching device is an n-channel metal oxide semiconductor device, and wherein the second switching device is a p-channel metal oxide semiconductor device.

In some embodiments, the loss prevention circuit includes a third switching device, a pull-up resistor, and a level shifter. The third switching device is electrically coupled to ground and the gate terminal of the first switching device. The pull-up resistor is electrically coupled to the power rail and the gate terminal of the first switching device. And a level shifter electrically coupled from the gate terminal of the first switching device to the gate terminal of the third switching device.

In some embodiments, the present disclosure provides a method for operating a buck converter circuit, comprising: applying a first pulse train to the first switching device to cause the first switching device to alternate between on and off; applying a second pulse train to the second switching device to cause the second switching device to alternate between on and off, wherein when the first switching device is on, the second switching device is off, and when the second switching device is on, the first switching device is off; charging, by a node at which respective source/drain regions of a first switching device and a second switching device are electrically coupled, an inductor, wherein the charging is performed when the second switching device is turned on; discharging the inductor when the second switching device is open; and biasing the gate of the first switching device with a voltage less than a threshold voltage of the first switching device immediately after detecting that the first pulse train is low and the second pulse train is high.

In some embodiments, the first pulse train has a first duty cycle and the second pulse train has a second duty cycle greater than the first duty cycle. The first burst is phase shifted with respect to the second burst.

In some embodiments, immediately after detecting that the first burst and the second burst are low and high, respectively, the buck conversion method further comprises: a conductive channel is formed within the first switching device, wherein a weak inversion current flows through the conductive channel to the node.

In some embodiments, the weak reverse current is in parallel with the current flowing through the internal diode of the first switching device.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A buck converter circuit comprising:

a first switching device;

a second switching device;

an inductor electrically coupled to a node at which a first source/drain region of the first switching device is electrically coupled to a first source/drain region of the second switching device; and

a controller configured to alternate the first switching device between on and off and further configured to alternate the second switching device between on and off, wherein when the second switching device is on, the first switching device is off, wherein immediately before or after the second switching device transitions between on and off, the first switching device is partially on, wherein when the first switching device is on, the gate of the first switching device is biased at a threshold voltage, and when partially on, the gate of the first switching device is biased at a sub-threshold voltage, wherein the sub-threshold voltage is not zero and an absolute value of the sub-threshold voltage is greater than or equal to half of an absolute value of the threshold voltage.

2. The buck converter circuit of claim 1, wherein the first switching device includes a second source/drain region, wherein the first and second source/drain regions of the first switching device are disposed within a substrate on opposite sides of the gate of the first switching device, and wherein a conductive channel is formed directly below the substrate and between the first and second source/drain regions when the first switching device is partially turned on.

3. The buck converter circuit of claim 1, wherein the first switching device is partially turned on immediately before the second switching device transitions from off to on.

4. The buck converter circuit of claim 1, wherein the first switching device is partially turned on immediately after the second switching device transitions from on to off.

5. The buck converter circuit of claim 1, the controller further comprising:

a loss prevention circuit electrically coupled to the gate of the first switching device and the gate of the second switching device, wherein the loss prevention circuit is configured to determine a first time frame immediately before the second switching device transitions from off to on and determine a second time frame immediately after the second switching device transitions from on to off, and wherein the loss prevention circuit partially turns the first switching device on during the first time frame and the second time frame.

6. The buck converter circuit of claim 5, wherein durations of the first and second time frames are defined by periods of time during which both the first and second switching devices are off, respectively, and wherein the first switching device is partially on throughout the durations.

7. The buck converter circuit of claim 6, wherein during the first and second time frames the buck converter comprises:

a first current path between a second source/drain region of the first switching device and the node, wherein the first current path conducts through an internal diode of the first switching device; and

a second current path between the second source/drain region of the first switching device and the node, wherein the second current path conducts through a conductive channel formed within the first switching device, and wherein the first current path is in parallel with the second current path.

8. A buck converter circuit comprising:

a first switching device;

a second switching device;

an inductor, wherein the first switching device and the second switching device are coupled with the inductor at a node;

a controller configured to apply a first pulse train and a second pulse train to a gate terminal of the first switching device and a gate terminal of the second switching device, respectively, to cause the first switching device and the second switching device to alternately change between a first state and a second state; and

a loss prevention circuit electrically coupled to the gate terminal of the first switching device and the gate terminal of the second switching device and configured to provide a voltage bias to the gate terminal of the first switching device that is less than a threshold voltage of the first switching device when transitioning between the first state and the second state, wherein the loss prevention circuit comprises:

a third switching device electrically coupled to ground and the gate terminal of the first switching device;

a pull-up resistor electrically coupled to a power rail and the gate terminal of the first switching device; and

a level shifter electrically coupled from the gate terminal of the first switching device to a gate terminal of the third switching device.

9. The buck converter circuit of claim 8, wherein in the first state the first switching device is on and the second switching device is off, and wherein in the second state the first switching device is off and the second switching device is on.

10. The buck converter circuit of claim 8, wherein the loss prevention circuit is further configured to:

detecting when the first switching device and the second switching device are in a third state, wherein the third state occurs upon transitioning from the first state to the second state or upon transitioning from the second state to the first state, and wherein the first switching device and the second switching device are open in the third state; and

during the third state, the first pulse train is enhanced to partially turn on the first switching device.

11. The buck converter circuit of claim 10, wherein during the third state, the buck converter comprises:

a first current path between a power rail and the node;

a second current path between a source/drain terminal of the first switching device and the node, wherein the second current path conducts through an internal diode of the first switching device; and

a third current path between the source/drain terminal and the node, wherein the third current path conducts through a conductive channel formed within the first switching device, and wherein the third current path is in parallel with the second current path.

12. The buck converter circuit of claim 11, wherein the first current path and the second current path each exist along an NPN junction within a substrate.

13. The buck converter circuit of claim 11, wherein during the third state, current flows through the first current path, the second current path, and the third current path.

14. The buck converter circuit of claim 8, wherein the first switching device is an n-channel metal oxide semiconductor device, and wherein the second switching device is a p-channel metal oxide semiconductor device.

15. A method of buck conversion, comprising:

applying a first pulse train to a first switching device to cause the first switching device to alternate between on and off, thereby causing the first switching device to be in a triode mode when on;

applying a second pulse train to a second switching device to cause the second switching device to alternate between on and off, wherein when the first switching device is on, the second switching device is off, and when the second switching device is on, the first switching device is off;

charging an inductor by a node electrically coupled at respective source/drain regions of the first and second switching devices, wherein the charging is performed when the second switching device is turned on;

discharging the inductor when the second switching device is open; and

immediately after detecting that the first pulse train is low and the second pulse train is high, biasing a gate of the first switching device at a sub-threshold voltage that is less than a threshold voltage of the first switching device, wherein the first switching device is biased at the sub-threshold voltage in a sub-threshold mode such that the sub-threshold mode is between a turn-off mode of the first switching device and the triode mode of the first switching device, and wherein the sub-threshold voltage is not zero.

16. The buck conversion method of claim 15, wherein the first pulse train has a first duty cycle and the second pulse train has a second duty cycle greater than the first duty cycle, and wherein the first pulse train has a phase offset relative to the second pulse train.

17. The buck conversion method of claim 16, further comprising, immediately after detecting that the first and second pulse trains are low and high, respectively:

forming a conductive channel within the first switching device, wherein a weak inversion current flows through the conductive channel to the node.

18. The buck conversion method of claim 17, wherein the weak reverse current is in parallel with a current flowing through an internal diode of the first switching device.

19. The buck conversion method of claim 15, wherein the first switching device is an n-channel metal oxide semiconductor device, and wherein the second switching device is a p-channel metal oxide semiconductor device.

20. The buck conversion method of claim 16, wherein a gate of the first switching device is biased at the sub-threshold voltage less than the threshold voltage, forming a conductive channel at a first source/drain region and a second source/drain region of the first switching device, wherein the conductive channel is directly below the gate of the first switching device.

21. An integrated circuit, comprising:

a first switching device;

a second switching device;

a controller configured to cause the first switching device and the second switching device to alternately change between a first state and a second state, wherein the second switching device is in a third state before or after transitioning between the first state and the second state, wherein a subthreshold voltage is applied to the first gate of the first switching device during the third state such that the third state is between a cut-off mode of the first switching device and a triode mode of the first switching device.

22. The integrated circuit of claim 21, wherein the sub-threshold voltage is not zero.

23. The integrated circuit of claim 21, wherein the sub-threshold voltage is lower than a threshold voltage of the first switching device and is not zero.

24. The integrated circuit of claim 21, wherein the first switching device and the second switching device are each turned on in the first state and turned off in the second state, wherein the first gate is biased at a threshold voltage in the first state, and wherein an absolute value of the sub-threshold voltage is greater than or equal to one-quarter of an absolute value of the threshold voltage.

25. The integrated circuit of claim 21, wherein the first switching device is in a third state immediately prior to the second switching device transitioning from the second state to the first state.

26. The integrated circuit of claim 21, wherein the first switching device comprises a second source/drain region, wherein the first and second source/drain regions of the first switching device are disposed within the substrate on opposite sides of the first gate, wherein during the third state, a conductive channel is laterally between the first and second source/drain regions of the first switching device and disposed directly below the substrate.

27. The integrated circuit of claim 21, wherein the subthreshold voltage is greater than a voltage applied to the first gate during the second state and less than a voltage applied to the first gate during the first state.

28. An integrated chip, comprising:

a first transistor;

a second transistor;

an inductor coupled to the first transistor and the second transistor at a node;

a controller configured to cause the first transistor and the second transistor to alternately change between a first state and a second state, respectively; and

a conduction loss reduction circuit electrically coupled to a gate terminal of the first transistor and a gate terminal of the second transistor and configured to bias the gate terminal of the first transistor at a sub-threshold voltage less than a threshold voltage of the first transistor when transitioning between the first state and the second state, wherein the conduction loss reduction circuit comprises a third transistor electrically coupled to ground and the gate terminal of the first transistor.

29. The integrated chip of claim 28, wherein the sub-threshold voltage is not zero.

30. The integrated chip of claim 28, wherein the conduction loss reduction circuit further comprises:

a level shifter electrically coupled from the gate terminal of the second transistor to the gate terminal of the third transistor.

31. The integrated chip of claim 28, wherein the conduction loss reduction circuit further comprises:

a fourth transistor electrically coupled to a power rail and the gate terminal of the first transistor.

32. The integrated chip of claim 31, wherein the third transistor is an n-channel metal-oxide-semiconductor transistor, and wherein the fourth transistor is a p-channel metal-oxide-semiconductor transistor.

33. The integrated chip of claim 28, wherein when the gate terminal of the first transistor is biased with the sub-threshold voltage, the integrated chip comprises:

a first current path between a power rail and the node;

a second current path between a first source/drain region of the first transistor and the node, wherein the second current path is conducted via an internal diode of the first transistor; and

a third current path between the first and second source/drain regions of the first transistor, wherein the first and second source/drain regions are disposed within the substrate on opposite sides of a gate structure of the first transistor, wherein the third current path is laterally between the first and second source/drain regions and disposed directly beneath the gate structure to conduct.

34. The integrated chip of claim 33, wherein the third current path is in parallel with the second current path.

35. The integrated chip of claim 28, wherein the subthreshold voltage is greater than or equal to one tenth of an absolute value of the threshold voltage.

36. A method of buck conversion, comprising:

applying first and second pulse trains to first and second transistors, respectively, to cause the first and second transistors to alternate between a first state and a second state, wherein in the first state the first transistor is on and the second transistor is off, and wherein in the second state the first transistor is off and the second transistor is on.

During the second state, charging an inductor by a node electrically coupled to respective source/drain regions of the first and second transistors;

immediately after detecting that a first pulse train is low and a second pulse train is high, biasing a gate of the first transistor with a sub-threshold voltage such that the first transistor is in a sub-threshold mode, wherein during the sub-threshold mode the first transistor is between on and off.

37. The buck conversion method of claim 36, wherein the first pulse train is between low and high when a gate of the first transistor is biased with the sub-threshold voltage.

38. The buck conversion method of claim 36, wherein the sub-threshold voltage is lower than a threshold voltage of the first transistor and is not zero.

39. The buck conversion method of claim 36, wherein the inductor is discharged when the second transistor is turned off.

40. The buck conversion method of claim 36, wherein a frequency of the first pulse train is equal to a frequency of the second pulse train, wherein the second pulse train has a duty cycle that is greater than a duty cycle of the first pulse train, and wherein the second pulse train has a phase offset relative to the first pulse train.