TWI496290B - Semiconductor device and manufacturing method thereof - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention claims priority from JP 2011-199238 (filing date: September 13, 2011), the entire contents of which are incorporated herein by reference.

Embodiments of the present invention relate to a semiconductor device and a method of fabricating the same.

A semiconductor device for power control requires a high voltage withstand voltage characteristic, and a reduction in ON resistance is required to suppress power loss. In addition, the high withstand voltage and the reduction of the on-resistance in the semiconductor device are mutually opposite physical properties, and there must be trade-offs in design.

For example, a 60~250V power MOSFET for bungee. The source-to-source voltage V _dss and the on-resistance R _onA , the resistance of the drift layer become dominant. Therefore, the drift layer can increase the withstand voltage by using a low concentration epitaxial layer, but the ON resistance becomes high. Therefore, the review of new gauge structures that achieve both high withstand voltage and low on-resistance has progressed. However, this structure is complicated and the manufacturing cost tends to increase. Therefore, it is necessary to simultaneously realize a semiconductor device having high withstand voltage and low on-resistance and being easy to manufacture.

An embodiment of the present invention provides a semiconductor device which can simultaneously realize high withstand voltage and low on-resistance, and which is easy to manufacture, and a method of manufacturing the same.

The semiconductor device according to the embodiment includes: a first conductivity type semiconductor layer; a second conductivity type first semiconductor region is provided on the semiconductor layer; and a first conductivity type second semiconductor region is selectively provided On the surface of the first semiconductor region. The first control electrode is disposed inside the trench provided in the semiconductor layer, and is opposed to the first semiconductor region and the second semiconductor region via an insulating film; and the second control electrode extends over the second control electrode The bottom surface of the trench is located on the bottom surface side of the first control electrode. The semiconductor layer has a depth between the end of the first main surface of the first semiconductor region and the end of the second control electrode on the bottom surface side, and the impurity concentration of the first conductivity type is lower than The first part of the other part of the above semiconductor layer.

According to the embodiment of the present invention, it is possible to provide a semiconductor device capable of simultaneously achieving high withstand voltage and low on-resistance, and which is easy to manufacture, and a method of manufacturing the same.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same portions are denoted by the same reference numerals, and the detailed description thereof will be omitted as appropriate, and only the different parts will be described. In the following embodiments, the first conductivity type is an n-type and the second conductivity type is a p-type. However, the first conductivity type may be a p-type, and the second conductivity type may be an n-type.

[First Embodiment]

Fig. 1 is a schematic cross-sectional view showing a semiconductor device 100 according to the first embodiment. As shown in the figure, the semiconductor device 100 is a trench gate type power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a field plate electrode (FP electrode) 9.

The semiconductor device 100 includes an n-type drift layer 3 (a first conductivity type semiconductor layer) provided on the n ⁺ drain layer 2, and a p-type base region 15 provided on the n-type drift layer 3 (first The semiconductor region is an n-type source region 17 (second semiconductor region) selectively provided on the surface of the p-type base region 15.

The semiconductor device 100 has a trench 5 that penetrates the p-type base region 15 through the first main surface 3a and reaches the n-type drift layer 3. The bottom surface 5a of the trench 5 is located closer to the side of the second main surface 3b than the p-type base region 15. Inside the trench 5, two gate electrodes 7 (first control electrodes) which are opposed to the p-type base region 15 and the n-type source region 17 are provided via the gate insulating film 12.

As will be described later, the p-type base region 15 and the n-type source region 17 are formed on the first main surface 3a of the n-type drift layer 3. Therefore, in the structure of the device completed as shown in Fig. 1, the first main surface 3a of the n-type drift layer 3 is the surface of the n-type source region 17. For convenience, a portion other than the p-type base region 15 and the n-type source region 17 of the n-type drift layer 3 is simply referred to as an n-type drift layer 3. In addition, in the following description, the depth means the positional relationship of the 1st main surface 3a in the direction of the 2nd main surface 3b.

An FP electrode 9 (second control electrode) extending from the side of the first main surface 3a toward the bottom surface 5a of the trench 5 is provided inside the trench 5. The end 9b of the bottom surface side of the trench 5 of the FP electrode 9 is located on the side closer to the bottom surface 5a than the end 7a of the bottom surface side of the gate electrode 7. The FP electrode 9 faces the inner surface of the trench 5 via the FP insulating film 13. Further, a portion 9a on the side of the source electrode 29 (first main electrode) of the FP electrode 9 extends between the two gate electrodes 7.

The source electrode 29 is electrically connected to the p-type base region 15 and the n-type source region 17. For example, as shown in FIG. 1, the surface of the n-type source region 17 and the surface of the p+ contact region 19 provided through the bottom surface of the contact trench 23 penetrating the n-type source region 17 are in contact with each other. form.

Further, a drain electrode 27 (second main electrode) is provided on the side of the second main surface 3b of the n-type drift layer 3. For example, the drain electrode 27 is electrically connected to the n-type drift layer 3 via the n ⁺ drain layer 2 containing a higher concentration of n-type impurities than the n-type drift layer 3.

Further, the depth between the end 15a on the side of the second main surface 3b of the p-type base region 15 and the end 9b of the FP electrode 9 in the bottom surface side of the trench 5 is set to be larger than the other portions of the n-type drift layer 3. Part 1 21 containing a lower n-type carrier concentration. That is, the drift layer 3 has the first portion 21. The first portion 21 includes, for example, a p-type impurity having a lower concentration of the n-type impurity contained in the n-type drift layer 3, and the carrier concentration is higher than that of the n-type drift layer 3 by compensation of the n-type impurity. Partially lower n-type. In addition, the epitaxial growth process of the n-type drift layer can be formed by reducing the doping amount of the n-type impurity or by adding a p-type impurity.

In the present embodiment, ion implantation of a p-type impurity in the first portion 21 will be described, and an n-type having a lower concentration than other portions will be described. Further, as shown in FIG. 1, the first portion 21 is provided at the depth of the end 7a of the bottom surface side of the trench 5 in the gate electrode 7. For example, the position of the peak concentration of the p-type impurity included in the first portion 21 is formed to be the same depth as the end 7a of the gate electrode 7. Here, the depth is the same, and strictly speaking, it means not only the same but also the vicinity thereof.

Further, the first portion 21 may be provided at a depth between the end 7a of the gate electrode 7 and the end 9b of the FP electrode 9. Preferably, it is provided in the vicinity of the side of the second main surface 3b of the end 7a.

FIG. 2 is a view showing a carrier concentration distribution and an electric field distribution of the semiconductor device 100. In Fig. 2(a), the vertical axis represents the carrier concentration of the n-type drift layer 3 and the p-type base region 15, the n-type source region 17, and the horizontal axis represents the distance from the n ⁺ drain layer 2. In Fig. 2(b), the vertical axis represents the electric field intensity, and the horizontal axis represents the distance from the n ⁺ drain layer 2.

2(a) shows the electron concentration 31 of the n-type source region 17, the hole concentration 32 of the p-type base region 15, and the electron concentration 37 of the n-type drift layer 3, respectively. Hereinafter, the electron concentration is referred to as an n-type carrier concentration, and the hole concentration is a p-type carrier concentration.

The boundary between the p-type base region 15 and the n-type drift layer 3, that is, the end on the second main surface 3b side of the p-type base region 15, is located at a position where the n ⁺ drain layer 2 is separated by -6.6 μm. The n-type carrier concentration of the n-type drift layer 3 is 2.3 × 10 ¹⁶ cm ^-3 . At the end 39 of the n ⁺ drain layer 2 side, the n-type carrier concentration becomes high. Such carrier concentration profile by line during the n ⁺ drain layer epitaxially grown on the n-type drift layer 2 3, the n-type impurity from the n ⁺ drain diffusion layer 2 to the n-type drift layer 3 is generated.

In Fig. 2(a), the distribution of the p-type impurity 25 included in the first portion 21 is indicated by a broken line. The p-type impurity 25 has a concentration peak at a position where the n ⁺ drain layer 2 leaves -5.8 μm. In response to this, the n-type carrier concentration of the first portion 21 is the lowest at the peak position of the p-type impurity, and becomes lower than the other portions.

Fig. 2(b) shows the electric field distribution at the time of a break in the n-type drift layer 3. This electric field distribution was obtained by simulating the carrier concentration distribution shown in Fig. 2(a).

For example, corresponding to the depth position of the end 7a of the gate electrode 7 and the depth position of the end 9b of the bottom surface side of the trench 5 of the FP electrode 9, two electric field concentrations which are breakdown points are generated. The electric field peak A _{1 is} the electric field concentration corresponding to the depth of the end 7a of the gate electrode 7, and the electric field peak A _{2 is} the electric field concentration corresponding to the depth of the end 9b of the FP electrode 9. The drain in the semiconductor device 100 is estimated. The breakdown voltage V _dss between the sources is 106V, and the ON resistance R _onA is 35.5mΩmm ² .

3 is a view showing a carrier concentration distribution and an electric field distribution of a semiconductor device 110 (not shown) of a comparative example. 4 is a view showing a carrier concentration distribution and an electric field distribution of a semiconductor device 120 (not shown) of another comparative example. The first portion 21 is not provided in each of the semiconductor devices 110 and 120, and has a carrier concentration distribution without the p-type impurity 25 as shown in Figs. 3(a) and 4(a). The other portions have the same configuration as the semiconductor device 100 shown in FIG.

The n-type carrier concentration of the n-type drift layer 3 of the semiconductor device 110 is 2.3 × 10 ¹⁶ cm ^-3 as in the case of the semiconductor device 100. Further, the n-type carrier concentration of the n-type drift layer 3 in the semiconductor device 120 is 1.4 × 10 ¹⁶ cm ^-3 .

As shown in FIG. 3(b), in the semiconductor device 110, the pn junction between the p-type base region 15 and the n-type drift layer 3 is slightly offset from the side of the n ⁺ drain layer 2 (by n ⁺汲). The pole layer 2 is separated from the position of -6.2 μm, and the electric field is concentrated to generate one electric field peak B. This position is the same as the electric field peak A ₁ shown in Fig. 2(b), and the electric field intensity of the electric field peak B is higher than the electric field peak A ₁ . The breakdown voltage V _dss of the semiconductor device 110 is estimated to be 63 V, and the on-resistance R _onA is 34 mΩ mm ² .

Comparing the semiconductor devices 100 and 110, the breakdown voltage of the semiconductor device 100 is high, and the on-resistance is slightly smaller than the semiconductor device 110. The difference between the latter is only because of the presence or absence of the first part 21, so the first part 21 can increase the breakdown voltage. That is, by the setting of the first portion 21, the electric field A _{3 of} the portion rises, and the electric field concentration in the vicinity of the pn junction is alleviated. Thus it is, in FIG. 3 (b) B reduces the peak electric field as shown in FIG. 2 (b) the peak electric field as shown in A _1. In addition, a new electric field concentration is generated on the n ⁺ drain layer 2 side, and an electric field peak A _{2 is} generated. As a result, the integral of the electric field distribution, that is, the collapse voltage rises. Further, although the on-resistance is increased by the provision of the first portion 21 having a low concentration, the amount of increase is only slight, and the effect of increasing the breakdown voltage is preferable.

Further, in FIG. 4 (b), the semiconductor device 120 of the electric field distribution of an electric field side of peak C ₁ a pn junction with the n ⁺ drain layer 2 side of the electric field peak C _2. C ₁ peak electric field and the electric field intensity of the same peak C _2, the semiconductor device 100 compared to the electric field of _an intensity of the peak A of the electric field is low. The breakdown voltage V _dss of the semiconductor device 120 is 114 V, which is higher than that of the semiconductor device 100. However, since the n-type carrier layer of the n-type drift layer 3 has a low concentration, the on-resistance R _onA is 40 mΩmm ² , which is about 10% higher than that of the semiconductor device 100.

The relationship between the above-described semiconductor devices 100, 110, and 120 can be explained from another point of view as follows. For example, when the on-resistance of the semiconductor device 120 is to be lowered, and only the n-type carrier concentration of the n-type drift layer 3 is simply increased, the breakdown voltage is lowered as in the case of the semiconductor device 110. Therefore, by providing the first portion 21 in the n-type drift layer 3, the breakdown voltage can be increased. In this way, the semiconductor device 100 capable of achieving both a high breakdown voltage and a low on-resistance can be realized.

In the semiconductor device 100, the magnitude of the rise in the breakdown voltage varies depending on the position at which the first portion 21 is disposed and the amount of p-type impurities contained therein. Therefore, by appropriately designing the position of the first portion 21 and the amount of p-type impurities, the desired breakdown voltage and on-resistance can be achieved.

Further, as described above, the electric field concentration generated on the pn junction side is generated at the depth of the end 7a of the bottom surface side of the trench 5 of the gate electrode 7. To alleviate the concentration of the electric field, as in the present embodiment, it is preferable to provide the first portion 21 in the vicinity of the n ⁺ drain layer 2 side of the end 7a of the gate electrode 7.

Next, a manufacturing process of the semiconductor device 100 will be described with reference to FIGS. 5 to 9. 5(a) to 9(b) are schematic views showing a partial cross section of a wafer in each project.

First, as shown in FIG. 5(a), the FP electrode 9 is formed inside the trench 5 provided in the n-type drift layer 3. For example, the n-type drift layer 3 is an n-type germanium layer grown by epitaxial growth on a germanium substrate. The tantalum substrate is an n ⁺ substrate containing a high concentration of n-type impurities and also serves as an n ⁺ drain layer 2. The trench 5 is formed, for example, by using a tantalum oxide film (SiO ₂ film) as a mask and selectively performing dry etching of the n-type drift layer 3 .

Next, thermal oxidation of the inner surface of the trench 5 is performed to form the FP insulating film 13. Further, an n-type polysilicon layer is deposited on the surface of the wafer, and the inside of the trench 5 is filled. Next, the n-type polysilicon which becomes the FP electrode 9 remains inside the trench 5, and the polysilicon layer on the surface of the wafer is etched back.

Next, as shown in FIG. 5(b), the FP insulating film 13 is etched back from the surface of the wafer to expose one of the FP electrodes 9.

Next, as shown in FIG. 6(a), thermal oxidation of the inner surface of the upper portion of the trench 5 is performed to form the gate insulating film 12. At the same time, the surface of the exposed portion 9a of the FP electrode 9 is also thermally oxidized to form the insulating film 14. The insulating film 14 is used to perform insulation between the gate electrode 7 and the FP electrode 9.

Next, an n-type polysilicon layer is deposited on the surface of the wafer, and a space between the gate insulating film 12 and the insulating film 14 is filled. Further, the n-type polysilicon which is the gate electrode 7 remains, and the n-type polysilicon layer deposited on the surface of the wafer is etched back.

As a result, as shown in FIG. 6(b), two gate electrodes 7 opposed to each other via the gate insulating film 12 are formed on the sidewalls of the trench 5. Next, from the side of the first main surface 3a of the n-type drift layer 3 toward the bottom surface 5a of the trench 5, the FP electrode 9 extending to a deeper position than the gate electrode 7 is formed.

Next, as shown in FIG. 7(a), boron (B) ion implantation of, for example, a p-type impurity is performed from the side of the first main surface 3a of the n-type drift layer 3. then The heat treatment is performed to activate the ion-implanted p-type impurity to further diffuse.

Thus, as shown in FIG. 7(b), the p-type base region 15 is formed. For example, heat treatment is performed at a temperature of 1000 ° C for about 10 minutes. As shown in the figure, the end 15a on the side of the second main surface 3b of the p-type base region 15 is formed shallower than the end 7a on the bottom surface side of the trench 5 in the gate electrode 7.

Next, as shown in FIG. 8(a), arsenic (As) of an n-type impurity and boron (B) of a p-type impurity are implanted from the side of the first main surface 3a of the n-type drift layer 3, for example. . The implantation of arsenic can be set to, for example, 30 keV. Further, the implantation of boron can be set, for example, so as to be implanted to the same depth as the end 7a of the bottom surface side of the trench 5 in the gate electrode 7. Further, the doping amount of boron is an amount that does not reverse the n-type drift layer 3 to a p-type, and is, for example, 6 × 10 ¹¹ cm ^-2 . In this manner, arsenic ions are implanted in the vicinity of the surface on the side of the first main surface 3a of the p-type base region 15 at a position deeper than the end 15a on the side of the second main surface 3b of the p-type base region 15, Boron ions are implanted.

Next, heat treatment is performed to activate the ion-implanted p-type impurity (B) and the n-type impurity (As). The heat treatment temperature at this time is set to, for example, 800 ° C to suppress the diffusion of boron. Thus, as shown in FIG. 8(b), the n-type source region 17 is formed on the surface of the p-type base region 15 at a position deeper than the end 15a of the p-type base region 15 (and the end of the gate electrode 7). The first portion 21 is formed at the same depth of 7a. In this case, the gate electrode 7 is opposed to the p-type base region 15 and the n-type source region 17 via the gate insulating film 12. A trench gate structure is formed.

Next, as shown in FIG. 9, an interlayer insulating film 43 is formed over the trench 5, and the insulating film of the other portion is removed. Next, a contact trench 23 is formed from the surface of the n-type source region 17 to the p-type base region 15, and a p ⁺ contact region 19 is formed on the bottom surface thereof.

Next, as shown in FIG. 9(b), the source electrode 29 which is in contact with the n-type source region 17 and the p ⁺ contact region 19 and covers the interlayer insulating film 43 is formed. Further, a drain electrode 27 is formed on the back side of the n ⁺ drain layer 2 (the surface on the opposite side of the n-type drift layer 3). Next, the wafer is diced into individual wafers, and assembled into a specific package to complete the semiconductor device 100.

As described above, in the present embodiment, the n-type drift layer 3 is provided with the first portion 21 having a lower n-type carrier concentration than the other portions, and the electric field concentration near the end 7a of the gate electrode 7 is alleviated, and the breakdown voltage is increased. . In this way, the n-type carrier concentration of the n-type drift layer can be increased, and the on-resistance can be reduced.

Further, in the present embodiment, it is possible to easily carry out the ion implantation process of the p-type impurity by adding the n-type drift layer 3. Therefore, a semiconductor device having high withstand voltage and low on-resistance can be realized without increasing the manufacturing cost.

In the semiconductor device 100, a breakdown voltage of 100 V or more is ensured, and the on-resistance of 10% is reduced. In this way, for example, the wafer size can be reduced by 10%, and the manufacturing cost can be reduced.

[Second Embodiment]

Fig. 10 is a view showing the mode of the semiconductor device 200 of the second embodiment; Sectional view. The semiconductor device 200 is different from the semiconductor device 100 shown in FIG. 1 in that instead of the first portion 21, the second portion 47 surrounding the bottom of the trench 5 is provided in the n-type drift layer 3. That is, the drift layer 3 has the second portion 47. The n-type carrier concentration of the second portion 47 is set to be lower than the other portions of the n-type drift layer 3.

As shown in Fig. 11 (a), a hard mask 49 is formed on the first main surface 3a of the n-type drift layer 3, and the trench 5 is formed in the direction of the second main surface 3b by, for example, dry etching. Next, for example, boron (B) ion implantation is performed with the hard mask 49 as an implant mask, and an implant layer 47a is formed at the bottom of the trench 5.

The hard mask 49 is, for example, a SiO ₂ film, and is patterned into a planar shape of the trench 5. The implantation of boron can be, for example, 30 keV, and the doping amount is set to an amount that does not invert the n-type drift layer 3 to a p-type.

Next, the processes of FIGS. 5 to 9 are performed to complete the semiconductor device 200 shown in FIG. However, in the present embodiment, ion implantation in which the p-type impurity of the first portion 21 is formed is not performed.

The implant layer 47a formed at the bottom of the trench 5 is activated by the heat treatment in the subsequent process to become the second portion 47. For example, the boron ion is subjected to heat treatment after implantation, and activation may be carried out as shown in Fig. 11 (b). Further, boron contained in the second portion 47 is diffused and redistributed by heat treatment at the time of formation of the p-type base region 15. In this case, the peak concentration of boron in the second portion 47 tends to be lower than that in the first portion 21. Therefore, the doping amount of boron implanted, for example, at the bottom of the trench 5 can be set to be higher than the doping amount of boron forming the first portion 21. Specifically, for example, the doping amount is set to 8 × 10 ¹² cm ^-2 , which is ten times larger than that of the first portion 21.

According to the present embodiment, by providing the second portion 47 surrounding the bottom of the trench 5, the electric field concentration on the pn junction side is alleviated, and the electric field peak B is reduced (refer to Fig. 3(b)). The bottom of the trench 5 can be depleted and the electric field strength can be increased. In this way, by increasing the breakdown voltage, the n-type carrier concentration of the n-type drift layer 3 is increased, and a semiconductor device having high withstand voltage and low on-resistance can be realized. Further, in the present embodiment, it is easy to carry out by performing ion implantation work on the bottom of the trench 5.

[Third embodiment]

Fig. 12 is a schematic cross-sectional view showing a semiconductor device 300 according to a third embodiment. The semiconductor device 300 differs from the semiconductor devices 100 and 200 in that it has both the first portion 21 and the second portion 47.

As shown in the carrier concentration distribution of FIG. 13(a), the semiconductor device 300 includes a p-type impurity 25 in the vicinity of the depth position of the end 7a of the gate electrode 7, and a p-type impurity 45 at the bottom of the trench 5. The n-type carrier concentration 37 of the n-type drift layer 3 is 2.3 × 10 ¹⁶ cm ^-3 as in the case of the semiconductor device 100.

The electric field distribution shown in Fig. 13 (b) has electric field peaks D ₁ and D ₂ corresponding to the two electric field concentration portions, and a portion D ₃ corresponding to the first portion 21 to increase the electric field. In this embodiment, in addition to the first portion 21 corresponding to portion D _3, by the second portion 47 of the groove at the bottom 5 provided that n ⁺ drain layer side peak electric field of ₂ D 2 increased. In this case, the breakdown voltage V _dss rises to 110V. Further, although the on-resistance R _onA is slightly higher at 36.8 mΩmm ² , the increase is extremely small. Therefore, the n-type carrier concentration of the n-type drift layer 3 can be increased and the on-resistance can be reduced while ensuring the same breakdown voltage as the semiconductor device 100.

Fig. 14 is a schematic cross-sectional view showing a semiconductor device 400 according to a modification of the embodiment. In the semiconductor device 400, the FP electrode 53 is provided on the bottom surface side of the trench 55, and the gate electrode 54 is provided on the side of the first main surface 3a. In other words, in the present modification, the gate electrode 54 and the FP electrode 53 are disposed above and below the same figure, and this point is different from the semiconductor device 300 in which the FP electrode 9 extends between the two gate electrodes 7.

The semiconductor device 400 is provided with a first portion 21 at a depth of the end of the bottom surface side of the trench 55 in the gate electrode 54, and a second portion 47 surrounding the bottom of the trench 55 is provided. This configuration is suitable for a semiconductor device which can easily realize a high withstand voltage and a low on-resistance when the width of the trench 55 is narrow.

The embodiments of the present invention have been described above, but the embodiments are merely examples and are not intended to limit the present invention. The implementation of the new rules can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The invention or its equivalents are also included in the scope of the invention and the equivalents thereof.

100‧‧‧Semiconductor device

9‧‧‧ Field plate electrode (FP electrode)

2‧‧‧n ⁺ bungee layer

3‧‧‧n type drift layer

15‧‧‧p-type base area

17‧‧‧n source region

3a‧‧‧1st main face

5‧‧‧ trench

5a‧‧‧ bottom

3b‧‧‧2nd main face

12‧‧‧Gate insulation film

7‧‧‧ gate electrode

9‧‧‧FP electrode (2nd control electrode)

9b‧‧‧

7a‧‧‧

13‧‧‧FP insulation film

29‧‧‧Source electrode

Section 9a‧‧‧

23‧‧‧Contact trench

19‧‧‧p+ contact area

27‧‧‧汲electrode

21‧‧‧Part 1

13‧‧‧FP insulation film

15a‧‧‧

Fig. 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment.

Fig. 2 is a view showing a carrier concentration distribution and an electric field distribution of the semiconductor device of the first embodiment.

[Fig. 3] Carrier concentration distribution and electric field division of a semiconductor device of a comparative example The map of cloth.

4 is a view showing a carrier concentration distribution and an electric field distribution of a semiconductor device of another comparative example.

Fig. 5 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment.

Fig. 6 is a schematic cross-sectional view showing the manufacturing process of Fig. 5.

Fig. 7 is a schematic cross-sectional view showing the manufacturing process of Fig. 6.

Fig. 8 is a schematic cross-sectional view showing the manufacturing process of Fig. 7.

Fig. 9 is a schematic cross-sectional view showing the manufacturing process of Fig. 8.

Fig. 10 is a schematic cross-sectional view showing a semiconductor device according to a second embodiment.

Fig. 11 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device of the second embodiment.

Fig. 12 is a schematic cross-sectional view showing a semiconductor device according to a third embodiment.

Fig. 13 is a view showing a carrier concentration distribution and an electric field distribution of the semiconductor device of the third embodiment.

Fig. 14 is a schematic cross-sectional view showing a semiconductor device according to a modification of the third embodiment.

100‧‧‧Semiconductor device

9‧‧‧ Field plate electrode (FP electrode)

2‧‧‧n ⁺ bungee layer

3‧‧‧n type drift layer

15‧‧‧p-type base area

17‧‧‧n source region

3a‧‧‧1st main face

5‧‧‧ trench

5a‧‧‧ bottom

3b‧‧‧2nd main face

12‧‧‧Gate insulation film

7‧‧‧ gate electrode

9‧‧‧FP electrode (2nd control electrode)

9b‧‧‧

7a‧‧‧

13‧‧‧FP insulation film

29‧‧‧Source electrode

Section 9a‧‧‧

23‧‧‧Contact trench

19‧‧‧p+ contact area

27‧‧‧汲electrode

21‧‧‧Part 1

13‧‧‧FP insulation film

15a‧‧‧

Claims (20)

A semiconductor device comprising: a first conductivity type semiconductor layer; a second conductivity type first semiconductor region provided on the semiconductor layer; and a first conductivity type second semiconductor region selectively provided in the semiconductor layer a surface of the first semiconductor region; the first control electrode is a trench extending through the first semiconductor region and reaching the semiconductor layer, and the bottom surface is located inside the trench at a position deeper than the first semiconductor region; Interposed between the first semiconductor region and the second semiconductor region via an insulating film; the second control electrode extends toward the bottom surface of the trench, and is located on the bottom surface side of the first control electrode; a main electrode electrically connected to the first semiconductor region and the second semiconductor region; and a second main electrode electrically connected to the semiconductor layer, wherein the semiconductor layer is provided at an end of the first semiconductor region The depth between the ends of the second control electrode on the bottom surface side is such that the carrier concentration of the first conductivity type is lower than the other portion of the semiconductor layer. The semiconductor device according to claim 1, wherein the first portion includes a second conductivity type impurity having a lower concentration than an impurity of the first conductivity type included in the semiconductor layer. A semiconductor device as claimed in claim 2, wherein The semiconductor layer is an n-type germanium layer, and the first portion is boron containing a p-type impurity. The semiconductor device according to claim 1, wherein an end of the trench on the bottom surface side of the first control electrode is located deeper than the first semiconductor region; and the first portion includes The impurity of the second conductivity type has a concentration peak at the same depth as the end of the first control electrode on the bottom surface side. The semiconductor device according to claim 1, wherein an end of the trench on the bottom surface side of the first control electrode is provided at a position deeper than the first semiconductor region; and the first portion is provided in the first portion The end of the first control electrode on the bottom surface side is between the end of the second control electrode and the bottom surface side. The semiconductor device according to claim 1, wherein the semiconductor layer further comprises: a portion of the semiconductor layer surrounding a bottom portion of the trench, wherein a concentration of a carrier of the first conductivity type is higher than that of the first portion The other part of the semiconductor layer is a low second part. The semiconductor device according to claim 6, wherein the second portion includes a second conductivity type impurity having a lower concentration than an impurity of the first conductivity type included in the semiconductor layer. The semiconductor device according to claim 7, wherein the semiconductor layer is an n-type germanium layer, and the second portion is boron containing a p-type impurity. The semiconductor device according to claim 1, wherein in the first portion, the impurity concentration of the first conductivity type is lower than that of the other portion of the semiconductor layer. The semiconductor device according to claim 1, wherein the first control electrode is provided inside the trench, and the second control electrode extends between the two first control electrodes. The semiconductor device according to claim 1, wherein the second control electrode is provided between the first control electrode and a bottom surface of the trench. The semiconductor device according to claim 1, wherein the third semiconductor region of the second conductivity type is selectively provided on a surface of the first semiconductor region; and the first main electrode is via the third The main electrode is electrically connected to the first semiconductor region. The semiconductor device according to claim 1, further comprising: a surface opposite to a surface of the semiconductor layer opposite to the first semiconductor region, and containing a first conductivity type impurity having a higher concentration than the semiconductor layer The second main electrode is electrically connected to the semiconductor layer via the layer. A semiconductor device comprising: a first conductivity type semiconductor layer; and a second conductivity type first semiconductor region provided on the semiconductor layer The second semiconductor region of the first conductivity type is selectively provided on the surface of the first semiconductor region; and the first control electrode is a trench that penetrates the first semiconductor region and reaches the semiconductor layer, and is on the bottom surface. The inside of the trench located deeper than the first semiconductor region is opposed to the first semiconductor region and the second semiconductor region via an insulating film; and the second control electrode extends over the bottom surface of the trench The side is located on the bottom surface side of the first control electrode; the first main electrode is electrically connected to the first semiconductor region and the second semiconductor region; and the second main electrode is electrically connected to the semiconductor layer The semiconductor layer has a portion of the semiconductor layer surrounding the bottom of the trench, and includes a second conductivity type impurity having a lower concentration than an impurity of the first conductivity type included in the semiconductor layer, and the first conductivity type The carrier concentration is lower than the other portions of the above semiconductor layer. A method of manufacturing a semiconductor device comprising: forming a first control electrode facing a sidewall of the trench via an insulating film inside a trench provided on a first main surface of a first conductivity type semiconductor layer; And a process of extending the second control electrode deeper than the first control electrode by the first main surface side toward the bottom surface of the trench; and implanting the second conductivity type into the semiconductor layer by the first main surface side a process of forming a first semiconductor region of a second conductivity type by applying a heat treatment to an impurity ion; An ion implantation process is performed on the second conductivity type impurity having a lower concentration than the impurity of the first conductivity type included in the semiconductor from the first main surface side to a position deeper than the first semiconductor region; a process of ion implantation of impurities of the first conductivity type from the first main surface side to the first semiconductor region; and the second conductivity for ion implantation at a position deeper than the first semiconductor region The impurity of the type and the impurity of the first conductivity type which is ion-implanted in the first semiconductor region are simultaneously subjected to heat treatment to perform activation. The method of manufacturing a semiconductor device according to claim 15, wherein the temperature of the heat treatment for activating the impurity implanted at a position deeper than the first semiconductor region is higher than the formation of the first semiconductor region. The heat treatment temperature in the project is low. The method of manufacturing a semiconductor device according to claim 15, wherein the semiconductor layer is an n-type germanium layer, the impurity of the first conductivity type is arsenic, and the impurity of the second conductivity type is boron. The method of manufacturing a semiconductor device according to claim 15, further comprising: forming, at a bottom portion of the trench, a second conductivity type impurity having a lower concentration than an impurity of the first conductivity type included in the semiconductor Ion implantation engineering. The manufacturer of the semiconductor device as claimed in claim 15 In the method, the impurity of the second conductivity type that is ion-implanted at a position deeper than the first semiconductor region is located at a depth of an end of the first control electrode on the bottom surface side of the trench. The method of manufacturing a semiconductor device according to claim 15, wherein the impurity of the second conductivity type ion-implanted at a position deeper than the first semiconductor region is located in the trench of the first control electrode The depth between the end of the bottom surface side and the end of the second control electrode on the bottom surface side.