TWI493884B - Delta-sigma modulator and method of calibration thereof - Google Patents

Description

Triangular integral modulator and its correction method

The present invention relates to a delta-sigma modulator, and more particularly to a delta-sigma modulator and a method of correcting the respective integrators.

In recent years, Delta-Sigma modulator (DSM) has been widely used in high-sampling analog-to-digital converters (Over-Sampling ADCs) in audio systems. It is a hearing aid, and you can see the trace of the delta-sigma modulator. In general, the delta-sigma modulator has the advantages of high resolution, simple circuit, and insensitivity to clock jitter. Moreover, since the triangular integral modulator has the characteristics of noise shaping, the signal-to-noise ratio is relatively improved, and the higher-order triangular integral modulator has better noise shaping effect. In addition, the integrator in the delta-sigma modulator also influences the performance of the delta-sigma modulator. If the integrator in the delta-sigma modulator produces distortion, its noise shaping capability will also decrease. The signal-to-noise ratio will be relatively unsatisfactory.

In general, the technique of a switched-capacitor circuit can be applied to an integrator of a delta-sigma modulator. A switched capacitor circuit includes switches, capacitors, and operational amplifiers, where the gain of the op amp is significantly correlated with overall circuit performance. However, with the advancement of the current integrated circuit process, although the speed of the circuit is increased and a small circuit area is realized, the power supply voltage thereof is relatively lowered. This is not However, the output impedance of the operational amplifier is limited, and the gain of the operational amplifier is also limited, which may cause a leakage of the integrated capacitor in the switched capacitor circuit.

In order to reduce the influence of this leakage phenomenon, it is necessary to use a large integrated capacitor and an operational amplifier with a large output impedance, that is, a large component that consumes a large amount of power. However, in today's process, it is not easy to design an operational amplifier with good voltage gain, which makes the capacitor switching circuit encounter a bottleneck in the low power supply environment of today's process. In addition, in addition to the influence of the process on the integrator, environmental factors of the operation may cause leakage of the integrator, such as temperature rise and fall.

In order to improve the leakage or distortion problem encountered by the capacitive switching circuit integrator, in the prior art, a test signal is added before or after the quantizer of the delta-sigma modulator, and the response of the test signal is based on the test signal. To correct the integrator is a common method. In addition, the time constant of the delta-sigma modulator is also adjusted by calculation of a special circuit, that is, adjusting a plurality of electronic components in the integrator to improve the performance of the integrator. However, in the prior art, it takes not only a long time to perform correction, but also a more complicated hardware circuit design, such as an adaptive filter or an addition of a narrowband filter. For the current electronics industry, not only is it high efficiency, but it also requires low cost. Therefore, how to design a product that meets the requirements is also an important issue.

In view of this, the present invention provides a triangular integral modulator and a correction thereof In the method, the correction signal is added to the position of the output end of each series integrator in the delta-sigma-integrator, and the detection signal is collected at the input end of each series integrator, and a simple correction processor is set to calculate and process According to this, the operating poles of each integrator are adjusted to overcome the influence of the integrator leakage on the delta-sigma modulator.

The present invention provides a delta-sigma modulator that includes a loop filter, a quantizer, a digital analog converter, and a correction processor. The loop filter is configured to receive input signals, feedback signals, and correction signals. This loop filter includes N integrators that are connected in series with each other and N is a positive integer. The quantizer is coupled to the loop filter for digitizing the output signal of the loop filter to output digital data. The digital analog converter is coupled to the quantizer, and converts the digital data of the quantizer to output a feedback signal. The correction processor includes N correction units, each of which is coupled to a corresponding integrator, wherein the i-th correction unit uses the detection signal output by the (i-1)th integrator to generate an error signal to the ith The integrator, the i-th integrator adjusts its operating pole according to the above error signal, and i is an integer greater than 1 and less than or equal to N.

In an embodiment of the invention, the loop filter in the above-described delta-sigma modulator further includes a plurality of adders located at an input end position and an output end position of each integrator in series. These adders are used to input the correction signal to the output of each integrator and input the feedback signal to the input of each integrator.

In an embodiment of the present invention, the first correcting unit in the triangular integral modulator uses the digital data output by the triangular integral modulator to generate an error signal to the first integrator, and the first integrator is based on Error signal adjustment operating pole point.

In an embodiment of the present invention, the correction processor in the above-described delta-sigma modulator further includes (N-1) correction quantizers, wherein the i-th correction quantizer is used to digitize the (i-1)th The detection signal output by the integrator generates a digital detection signal to the i-th correction unit.

In an embodiment of the invention, each of the correction units includes a multiplier, a first accumulator, a dual peak detector, and a second accumulator. The first accumulator is coupled to the multiplier, receives the filter shaping signal, and accumulates the filtered shaped signal to generate an accumulated signal. The dual peak detector is coupled to the first accumulator for receiving the accumulated signal to determine whether the absolute value of the accumulated signal is greater than a critical value. If the determination is yes, a stable detection signal is generated. The second accumulator is coupled to the dual peak detector for receiving the stable detection signal and accumulating the stable detection signal to generate an error signal. The multiplier of the first correcting unit is coupled to the output end of the delta-sigma modulator for receiving the digital data of the trigonometric integral modulator, and the multiplier of the i-th correcting unit is coupled to the i-th correcting quantizer. Used to receive digital detection data.

In an embodiment of the present invention, the multiplier of each correction unit in the above-mentioned triangular integral modulator receives the filtering sequence signal for filtering and shaping the digital detection signal. The correction signal is a periodic signal, and the period of the filtering sequence signal is the same as the correction signal.

In an embodiment of the present invention, in the above-described triangular integral modulator, when the absolute value of the accumulated signal is greater than a threshold, the dual peak detector generates a reset signal to the first accumulator.

In an embodiment of the invention, the integrator in the above-described delta-sigma modulator is an adjustable pole switching capacitive integrator.

In an embodiment of the present invention, in the above-described delta-sigma modulator, each integrator includes a variable capacitance element, and the capacitance value of the variable capacitance element is controlled according to an error signal to adjust an operating pole of each integrator.

In an embodiment of the invention, the above-described delta-sigma modulator further includes a correction signal generator. The correction signal generator is coupled to the loop filter for generating a correction signal.

In an embodiment of the invention, the above-described delta-sigma modulator further includes a logic circuit. The logic circuit is coupled to the correction signal generator for generating a filtered sequence signal.

The invention provides a method for correcting a triangular integral modulator. The triangular integrator receives an input signal and outputs digital data. The triangular integrator comprises at least one integrator and at least one correction unit. The calibration method comprises the following steps. First, a correction signal is input at the position of the output of each integrator. Next, a detection signal is collected at the output of the previous integrator of each integrator, wherein the first correction unit collects the digital data of the delta-sigma modulator. Then, each correction unit generates an error signal to each integrator according to the detection signal. Finally, each integrator adjusts the operating poles of each integrator based on the error signal.

In an embodiment of the invention, the step of collecting the detection signal further comprises digitizing the detection signal by using the correction quantizer to generate the digital detection signal.

In an embodiment of the invention, the step of generating an error signal comprises the following steps. First, the digital detection signal is multiplied by the filtered sequence signal to generate a filtered shaped signal. Then, the filter shaping signal is accumulated to generate an accumulated signal. Then, it is judged whether the absolute value of the accumulated signal is greater than a critical value, and if the judgment is yes, a stable detection signal is generated. Finally, accumulate the stable detection signal and output the error accordingly. Signal.

In an embodiment of the invention, the step of determining whether the absolute value of the accumulated signal is greater than a threshold further comprises: if the determination is yes, generating a reset signal to return the accumulated signal to zero.

In an embodiment of the invention, the step of adjusting the operating poles of the integrators includes controlling the capacitance values of the variable capacitance elements according to the error signals to adjust the operating poles of the integrators.

Based on the above, the delta-sigma modulator and the calibration method thereof are provided by inputting a correction signal at a position of an output end of each integrator and collecting a detection signal at a position of each integrator input, and with a simple correction. The design of the processor corrects the operation poles of each integrator one by one. According to this, each integrator can be operated on a better operating pole, overcoming the inferior phenomenon caused by the process or environmental factors of the integrator, and avoiding the complicated hardware circuit design, so that the triangular integral modulator can realize its Expected noise shaping effect.

The above described features and advantages of the present invention will be more apparent from the following description.

In today's mainstream integrated circuit design, there are a large number of triangular integral modulators that use switched capacitive integrators and practice. For example, FIG. 1 that is a switched capacitor integrator, when the switch when the phase of C T _1, C _s the sampling capacitor, the output voltage Vop and Von input voltage Vip and Vin, respectively, are each connected to a respective _f are connected Capacitance sampling. When the switching phase is T ₂ , the sampled voltage difference is added to C _i because of the charge conservation. Therefore, the z-domain transfer-function of such an integrator is

As can be seen from the above equation, in this switched capacitor integrator, β is its pole, and when β is 1, the integrator will have the best operation result. In addition, β is more related to the capacitance value of the capacitance C _f in the integrator. Increasing C _f can increase β , and decreasing C _f can reduce β . Therefore, the pole of the integrator can be changed by adjusting the capacitance C _f . , to reduce its distortion or leakage, so that the triangular integral modulator can have the best noise reforming effect, achieving a better signal-to-noise ratio. The present invention is to adjust the pole of the integrator in the delta-sigma modulator by designing a correction processing method to reduce the negative influence caused by the integrator leakage phenomenon. In order to make the content of the present invention more unclear, the following examples are exemplified. As an example of the present invention, it can be implemented.

2 is a block diagram of a delta-sigma modulator according to an embodiment of the present invention. Referring to FIG. 2, the delta-sigma modulator 20 of the present embodiment utilizes a loop formed by its components to allow the circuit to push the input signal XS through the generated noise to noise-shaping, including Loop filter 210, quantizer 220, digital analog converter 230, and correction processor 240. In FIG. 2, the delta-sigma modulator 20 receives the input signal XS, the feedback signal FS, and the correction signal CS, which are to be modulated, and the loop filter 210 includes at least one integrator (not shown). . The quantizer 220 is coupled to the loop filter 210, and digitizes the output signal OS of the loop filter 210, and then outputs the digital data YS of the delta-sigma modulator 20. The digital analog converter 230 is coupled to the quantizer 220 to generate the quantizer The digital data YS is converted into an analog feedback signal FS, that is, the digital data YS output from the quantizer 220 is output to output the feedback signal FS to the feedback filter 210.

The delta-sigma modulator 20 of the present embodiment further includes a correction processor 240 for correcting each integrator in the loop filter 210 to overcome the problem of integrator distortion. The correction processor 240 includes N correction units 241-24N, and N is a positive integer and represents the number of integrators in the delta-sigma modulator. Each of the correction units 241-24N is coupled to the loop filter 210. Due to the input of the correction signal CS and the negative feedback connection of the circuit, each of the correction units 241 to 24N can calculate the error signal by the detection signals DS ₁ to DS _N received from the feedback filter 210. ES ₁ ~ES _N , and then input error signals ES ₁ ~ES _N to the feedback filter to adjust the operating pole of the integrator. That is, when the integrator pole caused case offset can be calculated by the detection signal DS ₁ ~ DS _N collection and correction unit 241 ~ 24N acquires error signal ES ₁ ~ ES _N integrator adjusted A capacitor value associated with the pole allows the integrator to respond to a preferred operating state.

In more detail, FIG. 2 illustrates another embodiment of the delta-sigma modulator of the present invention. The delta-sigma modulator 30 includes a loop filter 310, a quantizer 320, a digital analog converter 330, and a correction unit 340. The loop filter 310 further includes N integrators H ₁ to H _N , a plurality of adders 3111 to 311 (p), and gain elements b ₁ to b _N . The correction processor 340 includes N correction units CP ₁ to CP _N and N-1 correction quantizers ADC ₂ to ADC _N , and corrects quantizer ADC ₂ to ADC _N digital detection signals DS ₂ to DS _N to generate digital bits. The detection signals DDS ₂ ~ DDS _N make the circuit design of the correction unit simpler due to digitization.

As shown, the integrators H ₁ to H _{N are} coupled to their corresponding correction units CP ₁ to CP _N , that is, the i-th correction unit CP _{i is} coupled to the i-th integrator H _i . For example, the first integrator H _{1 is} coupled to the first correcting unit CP ₁ , the second integrator H _{2 is} coupled to the second correcting unit CP ₂ , and the Nth integrator H _{N is} coupled to the Nth Correction unit CP _N . Embodiment of the present embodiment the adder 3111 ~ 311 (p) is located in each of the integrator ₁ to the input terminal and the output terminal position H H _N positions of these adders 3111 ~ 311 (p) for the correction signal CS input to the respective integration The position of the output end behind the H ₁ ~H _N and the feedback signal FS is input to the input end of each integrator H ₁ ~H _N . In other words, the input method of the correction signal CS of the present invention is to input the correction signal CS after each of the integrators H ₁ to H _N to be corrected.

In the present exemplary embodiment, since the integrators H ₁ to H _N and the correction unit CP ₁ to CP _{N have} substantially the same circuit structure and operation principle, only the first integrator H ₁ and the first correction unit CP _{1 are} coupled. The connection relationship is slightly different. Therefore, the i-th integrator H _i and the i-th correction unit CP _{i will be} described as follows, and the coupling relationship between the first integrator H ₁ and the first correction unit CP ₁ will be additionally described.

In the embodiment of the present invention, when the i-th integrator H _i is to be corrected, the correction signal CS is first input to the adder 311(j). The output of the (i-1)th integrator H _i-1 is then collected as the detection signal DS _i . After the detection signal DS _i is quantized by the correction quantizer ADCi, the digital detection signal DDS _{i is} generated, and the i-th correction unit CP _i receives the digital detection signal DDS _i and calculates and processes it to obtain the error signal ES _i . Therefore, the i-th integrator H _i can adjust its operating pole by the error signal ES _i , so that the operating pole of the i-th integrator can be kept close to 1 to avoid the integrator leakage or distortion. problem.

It should be noted here that the first correction unit CP ₁ receives the digital data YS output by the triangular integral modulator 30 as the detection signal DS ₁ , and since the triangular integral modulator 30 has a natural quantizer 320, It is not necessary to quantize the detection signal DS ₁ through the correction quantizer. Therefore, the first correcting unit CP ₁ only needs to use the digital data YS output by the quantizer 320 as its detection signal to generate the error signal ES ₁ to the first integrator H ₁ , and the first integrator according to the error signal. ES ₁ of the first integrator to adjust the operation of the H ₁ pole. It can be found that each integrator of the present invention has its correction unit, and the calibration process can be individually adjusted for each integral, not only can shorten the time required for correction, but also can be corresponding to individual integrators. Adjustment.

Based on the above, in the case where the number of the above-mentioned integrators is one (N=1), that is, the triangular integral modulator including one integrator is taken as an example, the operation principle inside the correction unit will be described in detail. 4A is a block diagram of the correction unit of FIG. 4A, and FIG. 5 is a schematic diagram of the internal signal of the delta-sigma modulator of FIG. 4. Referring to FIG. 4A, FIG. 4B and FIG. 5, the delta-sigma modulator 40 includes a first integrator 411, a first corrector 440, adders 451 and 452, a quantizer 420, and a digital analog converter 430. The correcting unit 440 further includes a multiplier 441, a first accumulator 442, a bidirectional peak detector 443, and a second accumulator 444.

In the present embodiment, the delta-sigma modulator 40 is a standard delta-sigma modulator, and the integrator 411 is, for example, the adjustable pole-switching capacitive integrator shown in FIG. 1, and the integrator 411 includes a variable capacitor. Element C _f . In addition, the delta-sigma modulator 40 further includes a correction unit 440. When the delta-sigma modulator 40 performs signal processing on the input signal XS to generate the digital data YS, the integrator 411 may cause leakage due to various factors. The operating point of the integrator 411 is slowly deviated from the ideal value, causing the triangular integral modulator to gradually lose the effect of its noise-type change, and the correcting unit 440 is used to correct the integrator 411 by controlling the graph. The capacitance value of the variable capacitance element C _f in 1 is to adjust the operating pole of the integrator 411.

When the integrator 411 is to be corrected, the correction signal CS is first input to the adder 452. In this embodiment, as shown in FIG. 5, the correction signal CS is a periodic square wave. Due to the negative feedback mechanism of the delta-sigma modulator, the digital data YS of the delta-sigma modulator 40 generates digital data in addition to the input signal XS and the signal generated by the quantizer 420. The YS has a component of the response signal CRS as shown in FIG.

As shown in FIG. 5, the response signal CRS converges to a residual voltage every half cycle, and the polarity of the residual voltage is related to the polarity of the operating pole offset of the integrator. In other words, when there is a residual voltage, it represents a phenomenon in which the operating pole is offset. Therefore, the residual amount of the residual voltage can be calculated by the correcting unit 440 to determine the offset direction and extent of the pole of the integrator 411. Accordingly, the correcting unit 440 collects the collected digital data YS and generates an error signal ES ₁ by calculation to adjust the operating pole of the integrator 411.

Moreover, after the digital unit YS is received by the correcting unit, the multiplier 441 of the correcting unit 440 receives a filtered sequence signal GS, performs filtering and shaping on the digital data YS, and generates a filtered shaping signal GFS to the first accumulator 442. It should be noted here that the filtered sequence signal GS is a ternary sequence having a size of 0, +1 or -1, and the period is the same as the correction signal CS. As shown in FIG. 5, the edge of the GS from +1 to 0 is synchronized with the falling edge of the correction signal CS (falling-edage) or delayed by several sampling clocks. The clock edge of GS from -1 to 0 is synchronized with the rising-edage of the correction signal CS or delayed by several sampling clocks.

The filtering function of multiplying the filtered demodulation signal GS can be achieved by using a filter such as a guard band filter or a detail protection filter, which is not limited by the present invention. As shown in FIG. 5, because the filter shaping signal GS is multiplied, the signal that the response signal GRS has not stabilized in the previous period can be filtered out, and the residual voltage value after convergence is retained. The purpose of using this GRS with guard interval is to filter out the interference caused by the delta-sigma modulator to the detection signal, avoiding additional or complicated filter design, and easily and quickly extracting the digital data with YS. Information on the residual voltage component of the signal CRS.

The first accumulator 442 is coupled to the multiplier 441, receives the filtering and shaping signal GFS, and accumulates the filtering and shaping signal GFS to generate the accumulating signal SS. The dual-peak detector 443 is coupled to the first accumulator 442, and receives the accumulating signal SS to determine the accumulation. Whether the absolute value of the signal SS is greater than a critical value, if the judgment is yes, A stable detection signal BS is generated. The function of the bidirectional peak detector 443 is to monitor the accumulated signal SS. The accumulating signal SS is the accumulated result of the digital data YS received by the correcting unit 441 and multiplied by the filtering and shaping signal GS, and its polarity is related to the operating pole.

The bidirectional peak detector 443 is internally provided with a threshold. When the accumulating signal SS is higher than the threshold (Nth), the bidirectional peak detector 443 sends a signal with the stable detection signal BS being 1; when the accumulating signal SS is lower than the negative threshold (-Nth), the bidirectional peak detector 443 sends a signal that the stable detection signal BS is -1; in other cases, the stable detection signal BS remains at 0. In addition to detecting the extent of the integrator leakage, the above actions can also detect the polarity of the pole offset, and check that the operating pole is insufficient or too high. In addition, since the digital signal YS carries a plurality of other signal components, in order to avoid a momentary error caused by the correction unit being too sensitive, the bidirectional peak detector 443 and the first accumulator 442 collect certain signal information and then judge. Increase the stability and reliability of the calibration unit.

In addition, once the absolute value of the accumulated signal SS is greater than the threshold value, the bidirectional peak detector 443 sends a reset signal RS to the first accumulator 442 to return the accumulated signal SS to 0. Restart the accumulated action. The second accumulator 444 is coupled to the dual peak detector 443, receives the stable detection signal BS, and accumulates the stable detection signal BS to generate the error signal ES ₁ . The error signal ES ₁ can be used to adjust the pole of the integrator H ₁ . When the error signal ES _{1 is} increased by 1, the variable capacitance in the integrator H ₁ is increased by a fixed amount, so the operating pole of the integrator H ₁ also changed to an operating pole closer to the ideal value, to achieve the purpose of correcting the integrator H _1.

FIG. 6 is a schematic diagram of another embodiment of the present invention. Referring to FIG. 6, the delta-sigma modulator 60 includes two integrators 611 and 612. In this embodiment, the delta-sigma modulator 60 also includes a correction signal generator 660 and logic circuit 670. The correction signal generator 660 generates a correction signal CS to the adders 652 and 653 for correcting the integrators 611 and 612. The logic circuit 670 is coupled to the correction signal generator 660 to generate a filtered sequence signal GS to the correction units 642 and 641.

A first integrator ₁ H operating principle can be described with reference to embodiments shown in the FIG. 4 embodiment, it is not described herein. Further, the correction signal generator 660 inputs the correction signal CS to the adder 653 behind the second integrator. The correcting unit 642 detects the offset of the operating pole of the second integrator H ₂ by using the detecting signal DS ₂ outputted by the first integrator H ₁ , and adjusts the second integrator according to the error signal ES ₂ . The operating pole of H ₂ . The correction quantizer 643 digitizes the detection signal DS ₂ to generate the digital detection signal DDS ₂ to enable the correction unit 642 to perform simpler digital processing.

It should be noted that the filtered sequence signal GS in the present embodiment can be generated by the logic circuit 670 simply processing the correction signal CS of the correction signal generator 660, and input to the multiplier 6421 for filtering. That is, the multiplier 6421 multiplies the digital detection signal DDS ₂ generated by the correction quantizer by the filtered sequence signal GS generated by the logic circuit to obtain a filtered shaping signal GFS. For the rest of the operation principle of the second correction unit CP2, reference may be made to the description of the embodiment shown in FIG. 4, and details are not described herein again. The second correction unit generates an error signal CP ₂ FS _2, while the second integrator H ₂ according to the error signal ES ₂ to adjust its operating pole.

Here, although the above exemplary embodiment is described only by describing the operation principle inside the first correction unit CP ₁ and the coupling relationship of the triangular integral modulator including the two integrators, the other includes multiple integrators and The operation principle of the trigonometric integral modulator of the correction unit is similar, and can be similarly used by those skilled in the art, and thus will not be further described herein.

In summary, the present invention mainly solves the problem of leakage or distortion of the integrator by correcting the input of the signal, the acquisition of the detection signal, and the calculation of the correction unit, and adjusting the operating poles of each integrator one by one. By the calibration method proposed by the invention, the triangular integral modulator can be operated normally, and the correction amplitude can be corrected by itself to achieve the purpose of correction, so that the leakage phenomenon is maintained at a low level, and the normal operation of the triangular integrator is not affected. . The pole error of each integrator with leakage can be detected separately and is not limited by the architecture of the delta-sigma modulator. In addition, the present invention only requires a simple circuit design and can achieve the purpose, does not require additional filter addition, does not require complicated calculation processing circuit, greatly reduces the circuit required for correction, improves its processing speed, and saves power. Consumption.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

20, 30, 40, 60‧‧‧ triangular integral modulator

210, 310‧‧‧ loop filter

220, 320, 420, 620‧‧ ‧ quantizer

230, 330, 430, 630‧‧‧ digital analog converters

240, 340‧‧ ‧ correction processor

241~24N‧‧‧correction unit

3111, 3112, 311(i), 311(j), 311(o), 311(p)‧‧‧Adder

CP ₁ ~CP _N , CP _i , CP _i+1 ‧‧‧ calibration unit

H ₁ ~H _N , H _i , H _i+1 , H _i-1 , H _N-1 ‧‧‧ integrator

b ₁ ~b _N , b _i , b _i+1 ‧‧‧gain components

ADC ₂ ~ADC _N , ADC _i , ADC _i+1 ‧‧‧ Correction Quantizer

411, 611, 612‧‧ ‧ integrator

440, 641, 642‧‧ ‧ calibration unit

451, 452, 651, 652, 653 ‧ ‧ adders

441,6421‧‧‧multiplier

442, 6422‧‧‧ first accumulator

443, 6423‧‧‧Double peak detector

444, 6424‧‧‧ second accumulator

660‧‧‧Correction signal generator

670‧‧‧Logical Circuit

643‧‧‧correction quantizer

Vip, Vin‧‧‧ input voltage

Vop, Von‧‧‧ output voltage

T ₁ , T ₂ ‧‧ ‧ switch

C _s , C _i , C _j ‧‧‧ capacitor

C _f ‧‧‧Variable Capacitor

XS‧‧‧ input signal

CS‧‧‧correction signal

YS‧‧‧ digital data

OS‧‧‧ output signal

ES ₁ ~ES _N ‧‧‧Error signal

DS ₁ ~DS _N ‧‧‧Detection signal

FS‧‧‧Reward signal

DDS ₁ ~DDS _N ‧‧‧Digital Detection Data

GS‧‧‧Filter sequence signal

GFS‧‧‧Filtering and shaping signal

RS‧‧‧Reset signal

SS‧‧‧Accumulate signal

BS‧‧‧Stability Detection Signal

CRS‧‧‧ response signal

The following drawings are a part of the specification of the invention, and illustrate the embodiments of the invention

1 is a circuit diagram of an embodiment of a switched capacitor integrator of the present invention.

2 is a block diagram of a delta-sigma modulator according to an embodiment of the present invention.

3 is a block diagram of a delta-sigma modulator according to another embodiment of the present invention.

4A is a block diagram of a delta-sigma modulator according to another embodiment of the present invention.

4B is a block diagram of a correction unit according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a signal waveform of a delta-sigma modulator signal according to an embodiment of the invention.

6 is a block diagram of a delta-sigma modulator according to another embodiment of the present invention.

20‧‧‧Triangle integral modulator

210‧‧‧ Loop Filter

220‧‧‧Quantifier

230‧‧‧Digital Analog Converter

240‧‧‧Correction processor

241~24N‧‧‧correction unit

XS‧‧‧ input signal

CS‧‧‧correction signal

YS‧‧‧ digital data

OS‧‧‧ output signal

ES ₁ ~ES _N ‧‧‧Error signal

DS ₁ ~DS _N ‧‧‧Detection signal

FS‧‧‧Reward signal

Claims (21)

A delta-sigma modulator includes: a loop filter that receives an input signal, a feedback signal, and a correction signal, the loop filter includes N integrators, wherein the integrators are connected in series, wherein N is a positive integer a quantizer coupled to the loop filter, digitizing one of the loop filter output signals to output a digital data; a digital analog converter coupled to the quantizer to convert the digital data received from the quantizer And outputting the feedback signal; and a correction processor, comprising N correction units, each of the correction units being coupled to the corresponding integrator, wherein the i-th correction unit uses the (i-1) integrator output A detection signal is generated to generate an error signal to the i-th integrator, and the i-th integrator adjusts an operating pole according to the error signal, where i is an integer greater than 1 and less than or equal to N. The delta-sigma modulator of claim 1, wherein the loop filter further comprises a plurality of adders located at the input end of each of the integrators and at the output end. The triangular integral modulator according to claim 2, wherein the adders are used to input the correction signal to a position of an output end of each integrator, and input the feedback signal to each of the integrators. The location of the input. The triangular integral modulator according to claim 1, wherein the first correcting unit uses the digital output of the triangular integral modulator The error signal is generated to the first integrator, and the first integrator adjusts the operating pole according to the error signal. The delta-sigma modulator according to claim 1, wherein the correction processor further comprises (N-1) correction quantizers, wherein the i-th correction quantizer is used to digitize the (i-1)th The detection signal output by the integrator generates a digital detection signal to the i-th correction unit. The triangular integral modulator according to claim 1, wherein the correction signal is a periodic signal. The triangular integral modulator according to claim 5, wherein each of the correction units further comprises: a multiplier; a first accumulator coupled to the multiplier, receiving a filtering and shaping signal, and accumulating the filtering Forming a signal to generate a cumulative signal; a dual peak detector coupled to the first accumulator, receiving the accumulated signal, determining whether the absolute value of the accumulated signal is greater than a threshold, and if so, generating a stable detection signal; And a second accumulator coupled to the dual peak detector to receive the stable detection signal and accumulating the stable detection signal to generate the error signal, wherein the multiplier of the first correction unit is coupled to the An output of the delta-sigma modulator is configured to receive the digital data of the delta-sigma modulator, and the multiplier of the i-th correction unit is coupled to the i-th correction quantizer to receive the digital detection data. The triangular integral modulator according to claim 7, wherein the multiplier of each of the correcting units receives a filtered sequence signal for filtering and shaping the digital detecting signal. The triangular integral modulator according to claim 8, wherein the correction signal is a periodic signal, and the period of the filtered sequence signal is the same as the correction signal. The delta-sigma modulator of claim 7, wherein when the absolute value of the accumulating signal is greater than the threshold, the dual-peak detector generates a reset signal to the first accumulator. The triangular integral modulator according to claim 1, wherein the integrators are an adjustable pole switched capacitive integrator. The triangular integral modulator according to claim 1, wherein each of the integrators includes a variable capacitance element, and the capacitance value of the variable capacitance element is controlled according to the error signal to adjust the operation of each of the integrators. pole. The delta-sigma modulator of claim 1, further comprising a correction signal generator coupled to the loop filter for generating the correction signal. The delta-sigma-integrator as described in claim 13 further includes a logic circuit coupled to the correction signal generator for generating a filtered sequence signal. A method for correcting a triangular integral modulator, the triangular integrator receiving an input signal and outputting a digital data, the triangular integrator including N integrators and N correction units, wherein N is a positive integer, the correction method includes: inputting a correction signal to the delta-integral modulator at a position of an output end of each integrator, wherein each of the correction units is coupled Corresponding to each of the integrators; collecting, by the i-th correction unit, a detection signal output by the (i-1)th integrator at a position of the output end of the (i-1) integrator, wherein the first The correction unit collects the digital data of the triangular integral modulator, i is an integer greater than 1 and less than or equal to N; and the ith correction unit generates an error signal to the ith integrator according to the detection signal; An operating pole of the i-th integrator is adjusted by the i-th integrator according to the corresponding error signal. The method of claim 15, wherein the step of collecting the detection signal further comprises digitizing the detection signal by using a correction quantizer to generate a digital detection signal. The calibration method of claim 15, wherein the correction signal is a periodic signal. The method of claim 15, wherein the step of generating the error signal comprises: multiplying the digital detection signal by a filtering sequence signal to generate a filtering shaping signal; accumulating the filtering shaping signal to generate an accumulation Signal Determining whether the absolute value of the accumulated signal is greater than a threshold value, and if so, generating a stable detection signal; accumulating the stable detection signal, and outputting the error signal accordingly. The method of claim 18, wherein the step of determining whether the absolute value of the accumulated signal is greater than a threshold further comprises: if the absolute value of the accumulated signal is greater than the threshold, generating a reset signal to cause the The accumulated signal is returned to 0. The calibration method of claim 18, wherein the correction signal is a periodic signal, and the period of the filtering sequence signal is the same as the correction signal. The calibration method of claim 15, wherein the step of adjusting the operating pole of each of the integrators comprises controlling a capacitance value of a variable capacitance element according to the error signal to adjust the operating pole of each of the integrators.