CN111478702B - Analog-to-digital converter device and clock skew correction method - Google Patents
Analog-to-digital converter device and clock skew correction method Download PDFInfo
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Abstract
An analog-to-digital converter device and a clock skew correction method. The analog-to-digital converter device includes a plurality of analog-to-digital converter circuitry, correction circuitry, and skew adjustment circuitry. The plurality of analog-to-digital converter circuits convert the input signal according to the plurality of clock signals to generate a plurality of first quantized outputs. The correction circuitry performs a correction operation based on the first quantized outputs to generate a plurality of second quantized outputs. The skew adjusting circuit determines a plurality of maximum value signals respectively corresponding to the second quantized outputs within a predetermined period, averages the maximum value signals to generate reference signals, and compares the reference signals with the maximum value signals to generate a plurality of adjusting signals respectively so as to reduce clock skew in the analog-digital converter circuit. The clock skew information can be obtained for correction by simple operation without providing an additional analog-to-digital converter circuit. In this way, the overall power consumption and correction period can be reduced.
Description
Technical Field
The present disclosure relates to an analog-to-digital converter device, and more particularly to a time-interleaved analog-to-digital converter and a clock skew correction method thereof.
Background
Analog-to-digital converter (ADC) is commonly found in various electronic devices to convert analog signals to digital signals for signal processing. In practical applications, the ADC may affect its resolution or linearity due to gain errors, voltage errors, or timing errors. For timing errors, the prior art needs to set complicated circuits (such as additional reference ADC circuits and auxiliary ADC circuits) or make corrections by off-chip (off-chip) correction, so that the power consumption of the ADC or the period required for the correction is higher and higher.
Disclosure of Invention
In order to solve the above-mentioned problems, some aspects of the present invention provide an analog-to-digital converter device, which includes a plurality of analog-to-digital converter circuits, a correction circuit system and a skew adjustment circuit system. The analog-to-digital converter circuitry is configured to convert an input signal according to the interleaved clock signals to generate a first quantized output. The correction circuitry is configured to perform at least one correction operation based on the plurality of first quantized outputs to generate a plurality of second quantized outputs. The skew adjusting circuitry is configured to determine a plurality of maximum signals corresponding to the plurality of second quantized outputs within a predetermined period, average the plurality of maximum signals to generate a reference signal, and compare the reference signal with the plurality of maximum signals to generate a plurality of adjustment signals, respectively, to reduce a clock skew in the plurality of analog-to-digital converter circuitry.
Some aspects of the present disclosure provide a clock skew correction method, comprising: performing at least one correction operation based on the plurality of first quantized outputs output from the plurality of analog-to-digital converter circuitry to generate a plurality of second quantized outputs; determining a plurality of maximum value signals respectively corresponding to the plurality of second quantized outputs in a preset period; averaging the maximum value signals to generate a reference signal; and comparing the reference signal with the maximum value signals respectively to generate a plurality of adjustment signals so as to reduce clock skew in the analog-digital converter circuit systems.
In some embodiments, the skew adjustment circuitry is configured to perform a plurality of absolute value operations on a plurality of difference signals, respectively, to generate a plurality of absolute value signals, and to perform a plurality of maximum value operations on the plurality of absolute value signals, respectively, to generate the plurality of maximum value signals, wherein the plurality of difference signals are generated according to the plurality of second quantized outputs.
In some embodiments, the skew adjustment circuitry includes a delay circuit, a plurality of arithmetic circuits, a plurality of absolute value circuits, a plurality of maximum value circuits, an averaging circuit, and a plurality of comparator circuits. The delay circuit is used for delaying a first one of the second quantized outputs to generate a delayed quantized output. The plurality of operation circuits are used for sequentially receiving two signals in the delay quantized output and the plurality of second quantized outputs so as to respectively generate a plurality of difference signals. Each of the absolute value circuits is configured to perform an absolute value operation according to a corresponding one of the plurality of difference signals to generate a corresponding one of the plurality of absolute value signals. Each of the absolute value circuits is used for receiving a corresponding absolute value signal in the absolute value signals and executing a maximum value operation so as to output a maximum value of the corresponding absolute value signal in the preset period as a corresponding one of the maximum value signals. The average circuit is used for executing an average operation to average the maximum value signals so as to generate the reference signal. The comparator circuits respectively compare the maximum value signals with the reference signals to generate a plurality of detection signals.
In some embodiments, the skew adjustment circuitry outputs the plurality of detection signals as the plurality of adjustment signals.
In some embodiments, each of the plurality of difference signals satisfies the following in the time domain:
sin(2πf(k+1)T)-sin(2πfkT)＝2cos(2πfkT+πfT)·(πfT+πfΔt)
wherein k is used for indicating different sampling time points corresponding to the second quantized outputs, f is the frequency of the input signal, T is the period of each of the clock signals, and Δt is a time difference value.
In some embodiments, the reference signal satisfies the following equation in the time domain:
AVG[Max(sin(2πf(k+1)T)-sin(2πfkT))]＝2πfT
wherein AVG indicates the average operation and Max indicates the maximum operation.
In some embodiments, the skew adjustment circuitry further includes a plurality of filter circuits and a plurality of integrator circuits. The filter circuits are used for generating a plurality of trigger signals according to the detection signals and at least one critical value. Each of the plurality of integrator circuits is configured to accumulate a corresponding one of the plurality of trigger signals and output the accumulated corresponding trigger signal as a corresponding one of the plurality of adjustment signals.
In some embodiments, each of the plurality of filter circuits is configured to accumulate a corresponding one of the plurality of detection signals and output the accumulated corresponding detection signal as a corresponding one of the plurality of trigger signals when the accumulated corresponding detection signal is greater than the at least one threshold.
In some embodiments, the plurality of analog-to-digital converter circuitry operates as a time-interleaved analog-to-digital converter.
In summary, the ADC device and the clock skew correction method provided by the embodiments of the present invention can obtain the clock skew information for correction by simple operation without providing additional ADC circuits. Thus, the overall power consumption and correction period can be reduced.
Drawings
The drawings in the present case are described as follows:
FIG. 1A is a schematic diagram of an analog-to-digital converter device according to some embodiments of the present disclosure;
FIG. 1B is a schematic diagram of waveforms of the clock signals of FIG. 1A according to some embodiments of the present disclosure;
FIG. 2 is a circuit schematic diagram of the deskew circuitry of FIG. 1A according to some embodiments of the present disclosure;
FIG. 3 is a schematic diagram of simulation results for correcting clock skew according to some embodiments of the present disclosure; and
FIG. 4 is a diagram of some embodiments according to the present disclosure a flowchart of a method of clock skew correction.
Detailed Description
All terms used herein have their ordinary meaning. The foregoing definitions of words and phrases are provided throughout this specification and in all instances, there is no intention to limit the scope and meaning of the disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.
As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or that two or more elements may operate or function with each other.
The term "circuitry" is used herein to refer broadly to a single system comprising one or more circuits (circuits). The term "circuit" generally refers to an article of manufacture that is connected in a manner by one or more transistors and/or one or more active and passive elements to process signals.
As used herein, "about," "substantially" or "equivalent" generally refers to an error or range of values within about twenty percent, preferably within about ten percent, and more preferably within about five percent. Unless explicitly stated otherwise, all references to values are to be considered as approximations, by the use of the error or range as indicated by the terms "about," "substantially," or "equivalent".
Referring to fig. 1A and 1B, fig. 1A is a schematic diagram of an analog-to-digital converter (ADC) device 100 according to some embodiments of the present disclosure. FIG. 1B is a schematic diagram of waveforms of the clock signals CLK 0-CLKM in FIG. 1A according to some embodiments of the present disclosure. In some embodiments, the ADC device 100 operates as a time-interleaved (time-interleaved) ADC having multiple channels.
In some embodiments, the ADC device 100 includes a plurality of ADC circuitry 110, correction circuitry 120, skew (skew) adjustment circuitry 130, and output circuitry 140. Each ADC circuitry 110 operates as a single channel. In other words, in this example, the ADC device 100 includes m+1 channels.
As shown in fig. 1A, the ADC circuits 110 are configured to perform an analog-to-digital conversion on the input signal SIN according to a corresponding one of the clock signals CLK 0-CLKM to generate a corresponding one of the quantized outputs Q0-QM. As shown in fig. 1B, the period of each of the plurality of clock signals CLK0 to CLKM is set to TS, which is equal to 1/fs. In other words, the sampling frequency of the plurality of ADC circuitry 110 is fs.
In some embodiments, two adjacent ones of the plurality of clock signals CLK 0-CLKM have a predetermined delay TD. For example, as shown in fig. 1B, the clock signal CLK0 and the clock signal CLK1 have a predetermined delay TD therebetween. Thus, the 1 st channel and the 2 nd channel perform sampling operation and analog-to-digital conversion at different times. And so on, the M+1 channels may operate according to a plurality of staggered timings.
In some embodiments, the correction circuitry 120 may be a foreground correction circuit or a background correction circuit. For example, the calibration circuitry 120 may comprise a pseudo-random number generator circuit (not shown) and a digital processing circuit (not shown), wherein the pseudo-random number generator circuit generates a calibration signal to the ADC circuitry 110, and the digital processing circuit may perform an adaptive algorithm (i.e., at least one calibration operation described above) according to the quantized outputs Q0-QM to reduce the offset or error of the quantized outputs Q0-QM. The calibration circuitry 120 is only used for example, but the present invention is not limited thereto. Various types of correction operations and correction circuitry 120 are contemplated.
In some embodiments, the skew adjusting circuit 130 is configured to determine a plurality of maximum value signals (e.g., M0-MM in FIG. 2) corresponding to the quantized outputs CQ 0-CQM respectively during a predetermined period (e.g., ST in FIG. 2), and average the plurality of maximum value signals to generate a reference signal (e.g., REF in FIG. 2). The skew adjusting circuitry 130 further compares the reference signal with a plurality of maximum values and generates a plurality of adjustment signals T0-TM as described above after operation. The operation thereof will be described in detail with reference to fig. 2 in the following paragraphs.
In some embodiments, the ADC circuitry 110 adjusts the execution timing of the ADC operations according to the adjustment signals T0-TM to equivalently correct the clock skew. Alternatively, in some embodiments, the timing of the clock signals CLK 0-CLKM can be adjusted directly according to the adjusting signals T0-TM to reduce the clock skew. For example, the plurality of adjustment signals T0-TM are input to a clock generator, a phase interpolator or a digital delay control line for generating the plurality of clock signals CLK 0-CLKM to adjust the phases of the plurality of clock signals CLK 0-CLKM. The above-mentioned arrangement for reducing the clock skew according to the adjustment signals T0 to TM is used for example, and the disclosure is not limited thereto.
Referring to fig. 2, fig. 2 is a circuit diagram illustrating the skew adjustment circuitry 130 of fig. 1A according to some embodiments of the present disclosure. For ease of understanding, similar elements of fig. 2 will be designated with the same reference numerals with reference to fig. 1A.
In some embodiments, the skew adjustment circuitry 130 includes a delay circuit 205, a plurality of operation circuits 210, an absolute value circuit 220, a maximum circuit 230, an average circuit 240, and a comparator circuit 250.
The plurality of operation circuits 210 are coupled to the correction circuitry 120 in fig. 1A. The plurality of arithmetic circuits 210 sequentially receive two of the quantized outputs CQ-1 to CQM to generate a plurality of difference signals D0 to DM, respectively. Taking the 1 st arithmetic circuit 210 as an example, the 1 st arithmetic circuit 210 receives the quantized outputs CQ-1 and CQ0 and subtracts the quantized output CQ-1 from the quantized output CQ0 to generate the difference signal D0. The arrangement and operation of the remaining operation circuits 210 can be similarly deduced, so that the description thereof will not be repeated.
In some embodiments, the operation circuit 210 may be implemented by a subtractor circuit or other processing circuits with the same function. Various circuits for implementing the operation circuit 210 are within the scope of the present disclosure.
The absolute value circuits 220 are coupled to the operation circuits 210, respectively, to receive the difference signals D0-DM, respectively. Each absolute value circuit 220 performs an absolute value operation according to a corresponding one of the plurality of difference signals D0-DM to generate a corresponding one of the plurality of absolute value signals A0-AM. Taking the 1 st absolute value circuit 220 as an example, the 1 st absolute value circuit 220 receives the difference signal D0 and performs an absolute value operation to obtain an absolute value of the difference signal D0 to generate an absolute value signal A0. Arrangement of the remaining absolute value circuit 220 the manner and operation may be pushed in this way, therefore, the description will not be repeated.
In some embodiments, the absolute value circuit 220 may be implemented by a processing circuit or a rectifying circuit. Various circuits implementing the absolute value circuit 220 are within the scope of the present disclosure.
The maximum value circuits 230 are coupled to the absolute value circuits 220, respectively, to receive the absolute value signals A0-AM, respectively. Each maximum value circuit 230 is configured to continuously receive a corresponding absolute value signal among the absolute value signals A0 to AM within a predetermined period ST, and perform a maximum value operation to output a corresponding absolute value signal among the maximum value signals M0 to MM during the predetermined period ST. Taking the 1 ST maximum value circuit 230 as an example, the 1 ST maximum value circuit 230 continuously receives the absolute value signal A0 in the predetermined period ST, and performs a maximum value operation to output the maximum absolute value signal A0 received in the predetermined period ST as the maximum value signal M0. The arrangement and operation of the remaining maximum value circuit 230 can be similarly deduced, so that the description thereof will not be repeated.
In some embodiments, the maximum value circuit 230 may be implemented by a digital processing circuit, a comparator circuit and/or a register circuit, but the present invention is not limited thereto. Various circuits implementing the maximum value circuit 230 are within the scope of the present disclosure.
The averaging circuit 240 is coupled to the maximum circuits 230 to receive the maximum signals M0-MM. The averaging circuit 240 performs an averaging operation on the maximum signals M0-MM to average the maximum signals M0-MM to generate a reference signal REF. In some embodiments, the averaging circuit 240 may be implemented by a digital processing circuit, but the present disclosure is not limited thereto.
The plurality of comparator circuits 250 are coupled to the averaging circuit 240 to receive the reference signal REF. The comparator circuits 250 each compare a corresponding one of the maximum value signals M0-MM with the reference signal REF to generate a corresponding one of the detection signals SD 0-SDM. Taking the 1 st comparator circuit 250 as an example, the comparator circuit 250 compares the maximum value signal M0 with the reference signal REF to generate the detection signal SD0. The arrangement and operation of the remaining comparator circuit 250 can be similarly deduced, so that the description thereof will not be repeated.
In some embodiments. The comparator circuit 250 may be implemented by a comparator. Alternatively, in some embodiments. The comparator circuit 250 may be implemented as a subtractor circuit and subtracts a corresponding one of the maximum value signals M0-MM from the reference signal REF to generate a corresponding one of the plurality of detection signals SD 0-SDM. The above embodiments regarding the comparator circuit 250 are used for illustration, and the disclosure is not limited thereto.
In some embodiments, the detection signals SD 0-SDM can be directly output as the adjustment signals T0-TM of FIG. 1A. In some embodiments, the detection signals SD 0-SDM are associated with time information of clock skew, which may reflect the clock skew generated on the corresponding ADC circuitry 110. Taking the operation of the 1 st operation circuit 210 as an example, as shown in fig. 2, since the adjustment signal T0 is generated based on the difference between the quantized output CQ0 and the quantized output CQ-1, the adjustment signal T0 can be used to indicate the time difference between the time T0 (i.e., the sampling time point corresponding to the quantized output CQ 0) and the time T-1 (i.e., the sampling time point corresponding to the quantized output CQ-1). The difference signal D0 can be derived in the time domain as the following equation (1):
CQ 0 -CQ -1 ＝sin(2πf(k+1)T)-sin(2πfkT)
＝2cos(2πfkT+πfT)·sin(πfT+πfΔt)…(1)
wherein, (k+1) T corresponds to a sampling time point corresponding to the quantized output CQ0, k is used to indicate a sampling time point corresponding to each quantized output CQ0 or CQ-1, f is the frequency of the input signal SIN, T is the aforementioned period TS, and Δt is the time difference.
If the frequency f is much smaller than 1/2T, equation (1) can be further derived as equation (2) below:
sin(2πf(k+1)T)-sin(2πfkT)＝2cos(2πfkT+πfT)·(πfT+πfΔt)…(2)
from equation (2), it can be seen that the time difference Δt is related to the amplitude of the difference signal D0 (i.e., 2pi ft+2pi Δt) when the frequency f is satisfied to be much smaller than 1/2T. Thus, by the operation of the absolute value circuit 220 and the maximum value circuit 230, the maximum value signal M0 may reflect information of the time difference Δt.
Likewise, the reference signal REF can be derived therefrom as the following equation (3) under the condition that the frequency f is satisfied to be much smaller than 1/2T:
AVG[Max(sin(2πf(k+1)T)-sin(2πfkT))]＝2πfT…(3)
accordingly, the influence of the time difference Δt caused by the clock skew can be obtained by comparing the maximum value signal M0 with the reference signal REF. For example, if the maximum value signal M0 is greater than the reference signal REF, the effect of the representative time difference Δt is positive. Under this condition, the clock skew causes the phase of the clock signal CLK0 to lead incorrectly. Alternatively, if the maximum signal M0 is lower than the reference signal REF, the effect of the representative time difference Δt is negative. In this condition, the clock skew causes the phase of the clock signal CLK0 to incorrectly lag. Therefore, according to different comparison results, the detection signal SD0 has different logic values to reflect the phase information of the 1 st ADC circuit system 110 to be adjusted due to the clock skew. In this manner, the above operations are applicable to the adjustment signals T0-TM and the detection signals SD 0-SDM, and thus the description thereof will not be repeated.
In some related art, more or more complex additional circuitry (e.g., auxiliary ADC circuitry or reference ADC circuitry, etc.) is required to obtain the clock skew information. In these techniques, more calibration cycles are required to obtain sufficient clock skew information due to the complex circuit configuration. Compared with the above technology, the embodiment of the present invention does not need to provide an additional ADC circuit, and can obtain the clock skew information by using simple operations (subtraction, absolute value, maximum value, average operation, etc.). In this way, the embodiments of the present invention can achieve lower power consumption and fewer calibration periods compared to the above-described techniques.
In some further embodiments, the skew adjustment circuitry 130 can further include a plurality of filter circuits 260 and a plurality of integrator circuits 270. The filter circuits 260 are coupled to the comparator circuits 250, respectively, to receive the detection signals SD0 SDM.
The filter circuits 260 generate trigger signals TR0 to TRM according to the detection signals SD0 to SDM and at least one threshold TH 1. The integrator circuits 270 are coupled to the filter circuits 260, respectively, to receive the trigger signals TR0 to TRM, respectively. The integrator circuits 270 generate the adjustment signals T0 to TM according to the trigger signals TR0 to TRM.
Taking the 1 st filter circuit 260 and the 1 st integrator circuit 270 as an example, the filter circuit 260 is coupled to the 1 st comparator circuit 250 to receive the detection signal SD0. In some embodiments, the filter circuit 260 may continuously accumulate the detection signal SD0, and compare the accumulated detection signal SD0 with at least one threshold value TH1 to output one or more trigger signals TR0. For example, when the accumulated detection signal SD0 is greater than at least one threshold TH1, the filter circuit 260 outputs the accumulated detection signal SD0 as the corresponding trigger signal TR0. The 1 st integrator circuit 270 is coupled to the 1 st filter circuit 260 to receive the trigger signal TR0. The integrator circuit 270 is configured to accumulate the trigger signal TR0 and output the accumulated trigger signal TR0 as the adjustment signal T0 to match different control timing methods. The arrangement and operation of the remaining filter circuit 260 and the integrator circuit 270 can be similarly deduced, so that the description thereof will not be repeated.
By providing the filter circuit 260, the number of times of execution of the correction of the clock skew can be reduced to reduce the dynamic power consumption of the ADC apparatus 100. Meanwhile, jitter caused by the correction of clock skew can be reduced by providing the filter circuit 260. By providing the integrator circuit 270, the timing adjustment method can be matched to adjust the corresponding value. In practical applications, the filter circuit 260 and the integrator circuit 270 can be selectively set according to practical requirements. In addition, the threshold TH1 can be adjusted according to actual requirements.
In various embodiments, the filter circuit 260 and the integrator circuit 270 may be implemented by at least one comparator (e.g., for comparing the trigger signal with the threshold TH1 or comparing the accumulated trigger signal), at least one register (e.g., for storing the accumulated signal or the accumulated trigger signal, etc.), at least one clearing circuit (e.g., for clearing the data of the register), and/or at least one operation circuit (e.g., for generating the accumulated signal or for accumulating the trigger signal). The above-mentioned arrangements of the filter circuit 260 and the integrator circuit 270 are used for illustration, and the disclosure is not limited thereto.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating simulation results for correcting clock skew according to some embodiments of the present disclosure.
As shown in fig. 3, in an experimental example, the ADC device 100 of fig. 1A is configured to have 32 channels (i.e. 32 ADC circuits 110), and the sampling frequency fs is set to 3.6GHZ. By the correction operation of the foregoing embodiment, it can be seen that the phase error between the 32 channels can be gradually and correctly converged to 0.
Referring to fig. 4, fig. 4 is a flowchart of a method 400 for clock skew correction according to some embodiments of the present disclosure. For ease of understanding, the correction method 400 will be described with reference to the preceding figures.
In operation S410, at least one correction operation is performed according to the quantized outputs Q0-QM outputted from the analog-to-digital converter circuitry 110 to generate quantized outputs CQ 0-CQM.
In operation S420, a plurality of maximum value signals M0 to MM corresponding to the plurality of quantized outputs CQ0 to CQM respectively within a predetermined period ST are determined.
In operation S430, the maximum value signals M0-MM are averaged to generate a reference signal REF.
In operation S440, the reference signal REF is compared with the maximum value signals M0-MM to generate the adjustment signals T0-TM, respectively, to reduce a clock skew in the analog-to-digital converter circuits 110.
The description of each operation and the implementation manner thereof may refer to the description of each embodiment, so that the description is not repeated here.
The various operations of the above described clock skew correction method 400 are merely examples and are not limited to being performed in the order illustrated in this example. The various operations under the clock skew correction method 400 may be added, replaced, omitted, or performed in a different order as appropriate without departing from the manner and scope of operation of the various embodiments of the present disclosure.
In summary, the ADC device and the clock skew correction method provided by the embodiments of the present invention can obtain the clock skew information for correction by simple operation without providing additional ADC circuits. Thus, the overall power consumption and correction period can be reduced.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be variously modified and modified by those skilled in the art without departing from the spirit and scope of the present invention, and the scope of the present invention is accordingly defined by the appended claims.
Claims (18)
1. An analog-to-digital converter apparatus, comprising:
multiple analog-to-digital converter circuitry for converting an input signal according to the interleaved clock signals to generate a first quantized output;
a correction circuitry for performing at least one correction operation based on the plurality of first quantized outputs, to generate a plurality of second quantized outputs; and
and the skew adjusting circuit system is used for determining a plurality of maximum value signals corresponding to the second quantized outputs in a preset period respectively, averaging the maximum value signals to generate a reference signal, and comparing the reference signal with the maximum value signals to generate a plurality of adjusting signals so as to reduce clock skew in the analog-digital converter circuit systems.
2. The analog-to-digital converter device of claim 1, wherein the skew adjustment circuitry is configured to perform a plurality of absolute value operations on a plurality of difference signals, respectively, to generate a plurality of absolute value signals, and to perform a plurality of maximum value operations on the plurality of absolute value signals, respectively, to generate the plurality of maximum value signals, wherein the plurality of difference signals are generated based on the plurality of second quantized outputs.
3. The analog-to-digital converter apparatus of claim 1, wherein the skew adjustment circuitry comprises:
a delay circuit for delaying a first one of the plurality of second quantized outputs to generate a delayed quantized output;
a plurality of operation circuits for sequentially receiving two signals of the delay quantized output and the plurality of second quantized outputs to generate a plurality of difference signals respectively;
a plurality of absolute value circuits, wherein each of the absolute value circuits is configured to perform an absolute value operation according to a corresponding one of the plurality of difference signals to generate a corresponding one of the plurality of absolute value signals;
a plurality of maximum value circuits, wherein each of the absolute value circuits is configured to receive a corresponding absolute value signal of the absolute value signals and perform a maximum value operation to output a maximum value of the corresponding absolute value signal within the predetermined period as a corresponding one of the maximum value signals;
an averaging circuit for performing an averaging operation to average the maximum value signals, to generate the reference signal; and
and a plurality of comparator circuits for comparing the maximum value signals with the reference signal respectively to generate a plurality of detection signals.
4. The analog-to-digital converter apparatus of claim 3, wherein the skew adjustment circuitry outputs the plurality of detection signals as the plurality of adjustment signals.
5. The analog-to-digital converter device of claim 3, wherein each of the plurality of difference signals satisfies the following equation in the time domain:
sin(2πf(k+1)T)-sin(2πfkT)＝2cos(2πfkT+πfT)·(πfT+πfΔt)
wherein k is used for indicating different sampling time points corresponding to the second quantized outputs, f is the frequency of the input signal, T is the period of each of the clock signals, and Δt is a time difference value.
6. The analog-to-digital converter apparatus of claim 5, wherein the reference signal satisfies the following formula in the time domain:
AVG[Max(sin(2πf(k+1)T)-sin(2πfkT))]＝2πfT
wherein AVG indicates the average operation and Max indicates the maximum operation.
7. The analog-to-digital converter apparatus of claim 3, wherein the skew adjustment circuitry further comprises:
a plurality of filter circuits for generating a plurality of trigger signals according to the plurality of detection signals and at least one threshold value; and
a plurality of integrator circuits, wherein each of the plurality of integrator circuits is configured to accumulate a corresponding one of the plurality of trigger signals and to output the accumulated corresponding trigger signal as a corresponding one of the plurality of adjustment signals.
8. The adc device according to claim 7, wherein each of the plurality of filter circuits is configured to accumulate a corresponding one of the plurality of detection signals and output the accumulated corresponding detection signal as a corresponding one of the plurality of trigger signals when the accumulated corresponding detection signal is greater than the at least one threshold.
9. The analog-to-digital converter apparatus of any one of claims 1 to 8, wherein the plurality of analog-to-digital converter circuitry operates as a time-interleaved analog-to-digital converter.
10. A method for clock skew correction, comprising:
performing at least one correction operation based on a plurality of first quantized outputs output from a plurality of analog-to-digital converter circuitry, to generate a plurality of second quantized outputs;
determining a plurality of maximum value signals respectively corresponding to the plurality of second quantized outputs in a preset period;
averaging the maximum value signals to generate a reference signal; and
the reference signal is compared with the maximum value signals respectively to generate a plurality of adjustment signals so as to reduce clock skew in the analog-digital converter circuit systems.
11. The method of claim 10, wherein determining the plurality of maximum signals comprises:
performing a plurality of absolute value operations on a plurality of difference signals, respectively, to generate a plurality of absolute value signals, wherein the plurality of difference signals are generated according to the plurality of second quantized outputs; and
a plurality of maximum value operations are performed on the plurality of absolute value signals, respectively, to generate the plurality of maximum value signals.
12. The method of claim 10, wherein determining the plurality of maximum signals comprises:
delaying a first one of the plurality of second quantized outputs to generate a delayed quantized output;
generating a plurality of difference signals according to the delay quantized output and two signals in the plurality of second quantized outputs in sequence;
performing an absolute value operation according to a corresponding difference signal in the plurality of difference signals to generate a corresponding one of the plurality of absolute value signals;
receiving a corresponding absolute value signal in the absolute value signals, and executing a maximum value operation to output a maximum value of the corresponding absolute value signal in the preset period as a corresponding one of the maximum value signals;
performing an average operation to average the maximum value signals to generate the reference signal; and
comparing the maximum value signals with the reference signal respectively to generate a plurality of detection signals.
13. The method of claim 12, wherein the plurality of detection signals are output as the plurality of adjustment signals.
14. The method of claim 12, wherein the analog-to-digital converter circuitry converts an input signal according to interleaved clock signals to generate the first quantized outputs, and wherein each of the difference signals satisfies the following in time domain:
sin(2πf(k+1)T)-sin(2πfkT)＝2cos(2πfkT+πfT)·(πfT+πfΔt)
wherein k is used for indicating different sampling time points corresponding to the second quantized outputs, f is the frequency of the input signal, T is the period of each of the clock signals, and Δt is a time difference value.
15. The method of claim 14 wherein the reference signal in the time domain satisfies the following equation:
AVG[Max(sin(2πf(k+1)T)-sin(2πfkT))]＝2πfT
wherein AVG indicates the average operation and Max indicates the maximum operation.
16. The method of claim 12, further comprising:
generating a plurality of trigger signals according to the plurality of detection signals and at least one threshold value; and
and accumulating a corresponding trigger signal in the plurality of trigger signals to output as a corresponding adjustment signal in the plurality of adjustment signals.
17. The method of claim 16, wherein generating the plurality of trigger signals comprises:
accumulating a corresponding detection signal of the plurality of detection signals, and outputting the accumulated corresponding detection signal as a corresponding one of the plurality of trigger signals when the accumulated corresponding detection signal is greater than the at least one threshold.
18. The method of any one of claims 10 to 17, wherein the plurality of analog-to-digital converter circuitry operates as a time-interleaved analog-to-digital converter.
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| CN102386918A (en) * | 2010-08-27 | 2012-03-21 | 英特希尔美国公司 | Calibration of impairments in a multichannel time-interleaved ADC |
| US8519875B2 (en) * | 2011-04-12 | 2013-08-27 | Maxim Integrated Products, Inc. | System and method for background calibration of time interleaved analog to digital converters |
| WO2013129202A1 (en) * | 2012-02-29 | 2013-09-06 | ソニー株式会社 | Column a/d converter, column a/d conversion method, solid imaging device, and camera system |
| JP5835031B2 (en) * | 2012-03-13 | 2015-12-24 | 株式会社ソシオネクスト | Analog-to-digital converter (ADC), correction circuit thereof, and correction method thereof |
| TWI489784B (en) * | 2012-03-16 | 2015-06-21 | Ind Tech Res Inst | Timing calibration circuit and timing calibration method for time interleaved analog to digital converters |
| CN103812504B (en) * | 2012-11-06 | 2017-03-01 | 瑞昱半导体股份有限公司 | Phase correction unit and method for correcting phase |
| US8890739B2 (en) * | 2012-12-05 | 2014-11-18 | Crest Semiconductors, Inc. | Time interleaving analog-to-digital converter |
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| US4070707A (en) * | 1976-07-12 | 1978-01-24 | General Electric Company | Reduction of offsets in data acquisition systems |
| US9270291B1 (en) * | 2015-01-13 | 2016-02-23 | Broadcom Corporation | High speed time-interleaved ADC gain offset and skew mitigation |
| CN106656190A (en) * | 2015-11-04 | 2017-05-10 | 瑞昱半导体股份有限公司 | Continuous approximation type analog-to-digital conversion circuit and method therefor |
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