CN111478702A - Analog-to-digital converter device and clock skew correction method - Google Patents
Analog-to-digital converter device and clock skew correction method Download PDFInfo
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Abstract
An analog-to-digital converter and a clock skew correction method. The analog-to-digital converter device comprises a plurality of analog-to-digital converter circuit systems, a correction circuit system and a skew adjusting circuit system. The analog-to-digital converter circuits convert an input signal according to a plurality of clock signals to generate a plurality of first quantized outputs. The correction circuitry performs a correction operation based on the first quantized outputs to generate a plurality of second quantized outputs. The skew adjusting circuit system determines a plurality of maximum value signals respectively corresponding to the second quantization outputs in a preset period, averages the maximum value signals to generate reference signals, and respectively compares the reference signals with the maximum value signals to generate a plurality of adjusting signals so as to reduce clock skew in the analog-digital converter circuit systems. The scheme can obtain the information of the clock skew through simple operation for correction without arranging an additional analog-digital converter circuit. Thus, the overall power consumption and calibration period can be reduced.
Description
Technical Field
The present disclosure relates to an analog-to-digital converter device, and more particularly, to a time-interleaved analog-to-digital converter and a clock skew correction method thereof.
Background
Analog-to-digital converters (ADCs) are commonly used in various electronic devices to convert analog signals into digital signals for signal processing. In practical applications, the ADC may affect its own resolution or linearity due to gain error, voltage error or timing error. In the prior art, for timing errors, complicated circuits (e.g., additional reference ADC circuits and auxiliary ADC circuits) are required to be provided or off-chip (off-chip) correction is used for correction, so that power consumption of the ADC or a period required for correction is higher and higher.
Disclosure of Invention
In order to solve the above problems, some aspects of the present invention provide an adc device including a plurality of adc circuits, a correction circuit and a skew adjustment circuit. The analog-to-digital converter circuits are used for converting an input signal according to a plurality of staggered clock signals to generate a plurality of first quantized outputs. The correction circuitry is configured to perform at least one correction operation based on the first quantized outputs to generate second quantized outputs. The skew adjusting circuit system is used for determining a plurality of maximum value signals respectively corresponding to the plurality of second quantization outputs in a preset period, averaging the plurality of maximum value signals to generate a reference signal, and comparing the reference signal with the plurality of maximum value signals respectively to generate a plurality of adjusting signals so as to reduce a clock skew in the plurality of analog-digital converter circuit systems.
Some aspects of the present disclosure provide a method for clock skew correction, comprising: performing at least one correction operation according to a plurality of first quantized outputs output from a plurality of analog-to-digital converter circuitry to generate a plurality of second quantized outputs; determining a plurality of maximum value signals respectively corresponding to the plurality of second quantized outputs within a predetermined period; averaging the maximum signals to generate a reference signal; and comparing the reference signal with the maximum signals to generate a plurality of adjusting signals so as to reduce a clock skew in the analog-to-digital converter circuit systems.
In some embodiments, the skew adjustment circuitry is configured to perform a plurality of absolute value operations on a plurality of difference signals to generate a plurality of absolute value signals, and to perform a plurality of maximum value operations on the plurality of absolute value signals to generate the plurality of maximum value signals, wherein the plurality of difference signals are generated according to the plurality of second quantized outputs.
In some embodiments, the skew adjustment circuitry includes a delay circuit, a plurality of arithmetic circuits, a plurality of absolute value circuits, a plurality of maximum value circuits, an averaging circuit, and a plurality of comparator circuits. The delay circuit is used for delaying a first one of the plurality of second quantized outputs to generate a delayed quantized output. The plurality of arithmetic circuits are used for receiving the two signals in the delay quantization output and the plurality of second quantization outputs in sequence so as to generate a plurality of difference signals respectively. The plurality of absolute value circuits are each configured to perform an absolute value operation according to a corresponding one of the plurality of difference signals to generate a corresponding one of a plurality of absolute value signals. Each of the plurality of absolute value circuits is configured to receive a corresponding one of the plurality of absolute value signals and perform a maximum value operation to output a maximum value of the corresponding absolute value signal within the predetermined period as a corresponding one of the plurality of maximum value signals. The averaging circuit is used for performing an averaging operation to average the plurality of maximum value signals so as to generate the reference signal. The comparator circuits respectively compare the maximum value signals with the reference signal to generate a plurality of detection signals.
In some embodiments, the skew adjustment circuitry outputs the detection signals as the adjustment signals.
In some embodiments, each of the plurality of difference signals satisfies the following equation in the time domain:
sin(2πf(k+1)T)-sin(2πfkT)＝2cos(2πfkT+πfT)·(πfT+πfΔt)
where k is used to indicate different sampling time points corresponding to the second quantized outputs, f is the frequency of the input signal, T is the period of each of the clock signals, and Δ T is a time difference.
In some embodiments, the reference signal satisfies the following equation in the time domain:
AVG[Max(sin(2πf(k+1)T)-sin(2πfkT))]＝2πfT
where AVG indicates the average operation and Max indicates the maximum operation.
In some embodiments, the skew adjustment circuitry further includes a plurality of filter circuits and a plurality of integrator circuits. The filter circuits are used for generating a plurality of trigger signals according to the detection signals and at least one threshold value. The plurality of integrator circuits are each configured to accumulate a corresponding one of the plurality of trigger signals and output the accumulated corresponding trigger signal as a corresponding one of the plurality of adjustment signals.
In some embodiments, each of the plurality of filter circuits is configured to accumulate a corresponding detection signal of the plurality of detection signals and output the accumulated corresponding detection signal as a corresponding one of the plurality of trigger signals when the accumulated corresponding detection signal is greater than the at least one threshold.
In some embodiments, the plurality of analog-to-digital converter circuitry operates as a time-interleaved analog-to-digital converter.
In summary, the ADC device and the clock skew correction method provided by the embodiment of the present invention can obtain the clock skew information through simple operation without providing an additional ADC circuit for correction. Thus, the overall power consumption and calibration period can be reduced.
Drawings
The drawings of the present application are illustrated as follows:
fig. 1A is a schematic diagram of an adc device according to some embodiments of the disclosure;
FIG. 1B is a waveform diagram of the clock signals of FIG. 1A according to some embodiments of the disclosure;
FIG. 2 is a circuit diagram illustrating the skew adjustment circuitry of FIG. 1A according to some embodiments of the present disclosure;
FIG. 3 is a diagram illustrating simulation results of correcting clock skew according to some embodiments of the present disclosure; and
fig. 4 is a flowchart illustrating a clock skew correction method according to some embodiments of the disclosure.
Detailed Description
All terms used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the words discussed herein in the context of this specification is by way of example only and should not be construed as limiting the scope or meaning of the present disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.
As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to the mutual operation or action of two or more elements.
As used herein, the term "circuit system" generally refers to a single system comprising one or more circuits (circuits). The term "circuit" broadly refers to an object connected in some manner by one or more transistors and/or one or more active and passive components to process a signal.
As used herein, "about," "substantially," or "equivalent" generally means within about twenty percent, preferably within about ten percent, and more preferably within about five percent, of the error or range of values. Unless expressly stated otherwise, all numbers reported herein are to be interpreted as approximations, as indicated by the error or range of values expressed as "about", "substantially" or "equivalent".
Referring to fig. 1A and 1B, fig. 1A is a schematic diagram of an analog-to-digital converter (ADC) device 100 according to some embodiments of the disclosure, fig. 1B is a schematic diagram of waveforms of a plurality of clock signals C L K0-C L KM of fig. 1A according to some embodiments of the disclosure, and in some embodiments, the ADC device 100 operates as a time-interleaved ADC having multiple channels.
In some embodiments, the ADC device 100 includes a plurality of ADC circuitry 110, correction circuitry 120, skew adjustment circuitry 130, and output circuitry 140. Each ADC circuitry 110 operates as a single channel. In other words, in this example, the ADC device 100 includes M +1 channels.
As shown in FIG. 1A, the plurality of ADC circuits 110 are configured to perform analog-to-digital conversion on an input signal SIN according to a corresponding one of a plurality of clock signals C L K0-C L KM to generate a corresponding one of a plurality of quantized outputs Q0-QM, as shown in FIG. 1B, a period of each of the plurality of clock signals C L K0-C L KM is set to TS, which is equal to 1/fs., i.e., a sampling frequency of the plurality of ADC circuits 110 is fs.
In some embodiments, two adjacent clock signals of the plurality of clock signals C L K0-C L KM have a predetermined delay TD., e.g., as shown in FIG. 1B, clock signal C L K0 and clock signal C L K1 have a predetermined delay TD., such that the 1 st channel and the 2 nd channel perform sampling and analog-to-digital conversion at different times, and so on, the M +1 channels can operate according to a plurality of staggered timings.
The correction circuitry 120 is coupled to each ADC circuitry 110 to receive the plurality of quantized outputs Q0-QM. The correction circuitry 120 may perform at least one correction operation based on the quantized outputs Q0-QM to correct offset (offset) and gain (gain) errors in the ADC circuitry 110 and generate corrected quantized outputs CQ 0-CQM.
In some embodiments, the correction circuitry 120 may be a foreground correction circuit or a background correction circuit. For example, the correction circuitry 120 may include a pseudo-random number generator circuit (not shown) and a digital processing circuit (not shown), wherein the pseudo-random number generator circuit generates a correction signal to the ADC circuitry 110, and the digital processing circuit may perform an adaptive algorithm (i.e., at least one correction operation described above) according to the quantized outputs Q0-QM to reduce the offset or error of the quantized outputs Q0-QM. The calibration circuitry 120 is for example only and is not limited thereto. Various types of calibration calculation and calibration circuitry 120 are contemplated by the present disclosure.
The skew adjustment circuitry 130 is coupled to the correction circuitry 120 to receive a plurality of corrected quantized outputs CQ 0-CQM. In some embodiments, the skew adjustment circuitry 130 may analyze clock skew (corresponding to phase error) existing among the plurality of ADC circuitry 110 according to the quantized outputs CQ 0-CQM to generate a plurality of adjustment signals T0-TM. The skew adjustment circuitry 130 outputs a plurality of adjustment signals T0-TM to the plurality of ADC circuitry 110, respectively. In some embodiments, the adjustment signals T0-TM are used to indicate the timing of the ADC circuitry 110 to be adjusted due to clock skew.
In some embodiments, the skew adjustment circuitry 130 is configured to determine a plurality of maximum signals (e.g., M0 MM of FIG. 2) corresponding to the quantized outputs CQ0 CQM respectively during a predetermined period (e.g., ST of FIG. 2), and average the plurality of maximum signals to generate a reference signal (e.g., REF of FIG. 2). The skew adjustment circuitry 130 further compares the reference signal with a plurality of maximum values and generates the plurality of adjustment signals T0-TM after calculation. The operation of this will be described in detail with reference to fig. 2 in the following paragraphs.
In some embodiments, the ADC circuits 110 may adjust the timing of performing the ADC operations according to the adjustment signals T0-TM to equivalently correct the clock skew, or, in some embodiments, the timing of the clock signals C L K0-C L KM may be directly adjusted according to the adjustment signals T0-TM to equivalently reduce the clock skew, for example, the adjustment signals T0-TM may be input to a clock generator, a phase interpolator, or a digital delay control line for generating the clock signals C L K0-C L KM to adjust the phases of the clock signals C L K0-C L KM.
The output circuitry 140 is coupled to the correction circuitry 120 to receive the corrected quantized outputs CQ 0-CQM. The output circuit system 140 performs a data combining operation based on the corrected plurality of quantized outputs CQ0 to CQM to generate the digital signal SOUT. Through the data combining operation, the multiple quantized outputs CQ0 CQM provided by the M +1 channels may be combined into a single digital signal SOUT having M +1 times the sampling frequency fs. In some embodiments, the output circuitry 140 may be implemented by a multiplexer circuit, but the disclosure is not limited thereto.
Referring to fig. 2, fig. 2 is a circuit diagram illustrating the skew adjustment circuitry 130 of fig. 1A according to some embodiments of the disclosure. For ease of understanding, similar elements of FIG. 2 will be designated with the same reference numerals with reference to FIG. 1A.
In some embodiments, the skew adjustment circuitry 130 includes a delay circuit 205, a plurality of arithmetic circuits 210, an absolute value circuit 220, a maximum value circuit 230, an averaging circuit 240, and a comparator circuit 250.
The delay circuit 205 delays the quantized output CQM of fig. 1A to generate a delayed quantized output CQ-1. In some embodiments, the delay time introduced by the delay circuit 205 is equivalent to the period TS in fig. 1B. The delay circuit 205 may be implemented by various digital circuits, such as buffers, inverters, filters, and so on. The above-described implementation of the delay circuit 205 is used for example, and the present disclosure is not limited thereto.
The plurality of operation circuits 210 are coupled to the correction circuitry 120 in fig. 1A. The plurality of arithmetic circuits 210 sequentially receive two of the quantized outputs CQ-1 to CQM to generate a plurality of difference signals D0 to DM, respectively. Taking the 1 st arithmetic circuit 210 as an example, the 1 st arithmetic circuit 210 receives the quantized outputs CQ-1 and CQ0 and subtracts the quantized output CQ-1 from the quantized output CQ0 to generate a difference signal D0. The setting and operation of the rest of the operation circuits 210 can be analogized, and thus, the description thereof is not repeated.
In some embodiments, the operation circuit 210 can be implemented by a subtractor circuit or other processing circuits with the same function. Various circuits for implementing the operation circuit 210 are all within the scope of the present disclosure.
The absolute value circuits 220 are respectively coupled to the operation circuits 210 to respectively receive the difference signals D0 DM. Each absolute value circuit 220 performs an absolute value operation according to a corresponding one of the difference signals D0 DM to generate a corresponding one of the absolute value signals A0 AM. Taking the 1 st absolute value circuit 220 as an example, the 1 st absolute value circuit 220 receives the difference signal D0 and performs an absolute value operation to obtain the absolute value of the difference signal D0 to generate the absolute value signal a 0. The setting and operation of the remaining absolute value circuits 220 may be similar, and thus are not repeated.
In some embodiments, the absolute value circuit 220 may be implemented by a processing circuit or a rectifying circuit. Various circuits for implementing the absolute value circuit 220 are all within the scope of the present disclosure.
The maximum value circuits 230 are respectively coupled to the absolute value circuits 220 to respectively receive the absolute value signals a 0-AM. Each of the maximum value circuits 230 is configured to continuously receive a corresponding one of the plurality of absolute value signals a 0-AM during a predetermined period ST, and perform a maximum value operation to output a maximum value of the corresponding one of the plurality of absolute value signals a 0-MM during the predetermined period ST as a corresponding one of the plurality of maximum value signals M0-MM. Taking the 1 ST max circuit 230 as an example, the 1 ST max circuit 230 continuously receives the absolute value signal a0 during the predetermined period ST and performs a max operation to output the maximum absolute value signal a0 received during the predetermined period ST as the maximum value signal M0. The setting and operation of the remaining maximum value circuit 230 can be analogized, and thus, the description thereof is not repeated.
In some embodiments, the maximum circuit 230 may be implemented by a digital processing circuit, a comparator circuit and/or a register circuit, but the disclosure is not limited thereto. Various circuits for implementing the maximum circuit 230 are within the scope of the present disclosure.
The averaging circuit 240 is coupled to the plurality of maximum value circuits 230 to receive the plurality of maximum value signals M0 MM. The averaging circuit 240 performs an averaging operation on the plurality of maximum value signals M0 MM to average the plurality of maximum value signals M0 MM to generate a reference signal REF. In some embodiments, the averaging circuit 240 may be implemented by a digital processing circuit, but the disclosure is not limited thereto.
The plurality of comparator circuits 250 are coupled to the averaging circuit 240 to receive the reference signal REF. Each of the comparator circuits 250 compares a corresponding one of the maximum value signals M0 MM with the reference signal REF to generate a corresponding one of the detection signals SD0 SDM. Taking the 1 st comparator circuit 250 as an example, the comparator circuit 250 compares the maximum value signal M0 with the reference signal REF to generate the detection signal SD 0. The setting and operation of the remaining comparator circuits 250 can be analogized, and thus, the description thereof is not repeated.
In some embodiments. The comparator circuit 250 may be implemented by a comparator. Alternatively, in some embodiments. The comparator circuit 250 may be implemented by a subtractor circuit, and subtracts a corresponding one of the maximum value signals M0 MM from the reference signal REF to generate a corresponding one of the detection signals SD0 SDM. The above embodiments of the comparator circuit 250 are for illustration and the disclosure is not limited thereto.
In some embodiments, the detection signals SD0 SDM can be directly outputted as the adjustment signals T0 TM in FIG. 1A. In some embodiments, the detection signals SD 0-SDM are associated with timing information of clock skew, which reflects the clock skew generated on the corresponding ADC circuitry 110. Taking the operation of the 1 st arithmetic circuit 210 as an example, as shown in fig. 2, since the adjustment signal T0 is generated based on the difference between the quantized output CQ0 and the quantized output CQ-1, the adjustment signal T0 can be used to indicate the time difference between time T0 (i.e., the sampling time point corresponding to the quantized output CQ 0) and time T-1 (i.e., the sampling time point corresponding to the quantized output CQ-1). The difference signal D0 can be derived in the time domain as the following equation (1):
CQ0-CQ-1＝sin(2πf(k+1)T)-sin(2πfkT)
＝2cos(2πfkT+πfT)·sin(πfT+πfΔt)…(1)
where, (k +1) T is equivalent to the sampling time corresponding to the quantized output CQ0, k is used to indicate the sampling time corresponding to each quantized output CQ0 or CQ-1, f is the frequency of the input signal SIN, T is the period TS mentioned above, and Δ T is the time difference.
If the frequency f is much less than 1/2T, equation (1) can be further derived as equation (2):
sin(2πf(k+1)T)-sin(2πfkT)＝2cos(2πfkT+πfT)·(πfT+πfΔr)…(2)
from equation (2), it can be known that the time difference Δ T is related to the amplitude of the difference signal D0 (i.e., 2 π fT +2 π Δ T) when the condition that the frequency f is much less than 1/2T is satisfied. Therefore, the maximum value signal M0 reflects the information of the time difference Δ t through the operations of the absolute value circuit 220 and the maximum value circuit 230.
Similarly, when the condition that the frequency f is much less than 1/2T is satisfied, the reference signal REF can be derived as the following formula (3):
AVG[Max(sin(2πf(k+1)T)-sin(2πfkT))]＝2πfT…(3)
accordingly, the effect of the time difference Δ T caused by the clock skew can be known by comparing the maximum value signal D0 with the reference signal REF. for example, if the maximum value signal D0 is greater than the reference signal REF, it represents that the effect of the time difference Δ T is positive, under this condition, the clock skew causes the phase of the clock signal C L K0 to be incorrectly advanced, or, if the maximum value signal D0 is lower than the reference signal REF, it represents that the effect of the time difference Δ T is negative, under this condition, the clock skew causes the phase of the clock signal C L K0 to be incorrectly advanced.
In some related technologies, more or more complex additional circuits (e.g., an auxiliary ADC circuit or a reference ADC circuit, etc.) are required to obtain the clock skew information. In these techniques, since the circuit configuration is complicated, more calibration cycles are required to obtain sufficient clock skew information. Compared with the above-mentioned techniques, the embodiment of the present invention does not need to provide an additional ADC circuit, and can obtain the clock skew information by simple operations (subtraction, absolute value operation, maximum value operation, average operation, etc.). Thus, the embodiments achieve lower power consumption and fewer calibration cycles compared to the above techniques.
In some further embodiments, the skew adjustment circuitry 130 may further include a plurality of filter circuits 260 and a plurality of integrator circuits 270. The plurality of filter circuits 260 are respectively coupled to the plurality of comparator circuits 250 for respectively receiving the plurality of detection signals SD 0-SDM.
The filter circuits 260 generate trigger signals TR0 TRM according to the detection signals SD0 SDM and at least one threshold TH 1. The integrator circuits 270 are respectively coupled to the filter circuits 260 to respectively receive the trigger signals TR 0-TRM. The plurality of integrator circuits 270 generate a plurality of adjustment signals T0 to TM in accordance with the plurality of trigger signals TR0 to TRM.
Taking the 1 st filter circuit 260 and the 1 st integrator circuit 270 as examples, the filter circuit 260 is coupled to the 1 st comparator circuit 250 to receive the detection signal SD 0. In some embodiments, the filter circuit 260 may continuously accumulate the detection signal SD0 and compare the accumulated detection signal SD0 with at least one threshold TH1 to output one or more trigger signals TR 0. For example, when the accumulated detection signal SD0 is greater than at least one threshold value TH1, the filter circuit 260 outputs the accumulated detection signal SD0 as the corresponding trigger signal TR 0. The 1 st integrator circuit 270 is coupled to the 1 st filter circuit 260 to receive the trigger signal TR 0. The integrator circuit 270 is used for accumulating the trigger signal TR0 and outputting the accumulated trigger signal TR0 as an adjustment signal T0 to match different control timing methods. The arrangement and operation of the remaining filter circuit 260 and integrator circuit 270 can be analogized, and thus, the detailed description thereof is not repeated.
By providing the filter circuit 260, the number of clock skew correction operations can be reduced, thereby reducing the dynamic power consumption of the ADC apparatus 100. Meanwhile, jitter (jitter) caused by the corrected clock skew can be reduced by providing the filter circuit 260. By providing the integrator circuit 270, the timing adjustment method can be adjusted to a corresponding value. In practical applications, the filter circuit 260 and the integrator circuit 270 can be selectively configured according to actual requirements. In addition, the threshold TH1 can be adjusted according to actual requirements.
In various embodiments, the filter circuit 260 and the integrator circuit 270 may be implemented by at least one comparator (e.g., for comparing the trigger signal with the threshold TH1 or comparing the accumulated trigger signal), at least one register (e.g., for storing the accumulated trigger signal or the accumulated trigger signal, etc.), at least one clearing circuit (e.g., for clearing data from the register), and/or at least one arithmetic circuit (e.g., for generating the accumulated trigger signal or accumulating the trigger signal). The above arrangement of the filter circuit 260 and the integrator circuit 270 is used for illustration, and the disclosure is not limited thereto.
Referring to fig. 3, fig. 3 is a diagram illustrating simulation results of correcting clock skew according to some embodiments of the present disclosure.
As shown in fig. 3, in an experimental example, the ADC device 100 of fig. 1A is configured to have 32 channels (i.e., 32 ADC circuits 110), and the sampling frequency fs is set to 3.6 GHZ. Through the correction operation of the foregoing embodiment, it can be seen that the phase error between 32 channels can gradually and correctly converge to 0.
Referring to fig. 4, fig. 4 is a flowchart illustrating a clock skew correction method 400 according to some embodiments of the disclosure. For ease of understanding, the calibration method 400 will be described with reference to the preceding figures.
In operation S410, at least one correction operation is performed on the quantized outputs Q0-QM output from the adc circuitry 110 to generate quantized outputs CQ 0-CQM.
In operation S420, a plurality of maximum value signals M0 MM corresponding to the quantized outputs CQ0 CQM are determined within a predetermined period ST.
In operation S430, a plurality of maximum value signals M0 MM are averaged to generate a reference signal REF.
In operation S440, the reference signal REF is compared with the maximum signals M0 MM respectively to generate adjustment signals T0 TM to reduce a clock skew in the ADC circuitry 110.
The descriptions and the embodiments of the above operations can refer to the descriptions of the above embodiments, and thus the descriptions thereof are not repeated herein.
The operations of the clock skew correction method 400 are only exemplary and need not be performed in the order shown in this example. The various operations performed in the clock skew correction method 400 may be added, substituted, omitted, or performed in a different order, as appropriate, without departing from the scope and manner of operation of various embodiments of the disclosure.
In summary, the ADC device and the clock skew correction method provided by the embodiment of the present invention can obtain the clock skew information through simple operation without providing an additional ADC circuit for correction. Thus, the overall power consumption and calibration period can be reduced.
Although the present disclosure has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure is to be determined by the appended claims.
Claims (18)
1. An analog-to-digital converter apparatus, comprising:
a plurality of analog-to-digital converter circuits for converting an input signal according to a plurality of interleaved clock signals to generate a plurality of first quantized outputs;
a correction circuitry configured to perform at least one correction operation based on the first quantized outputs to generate second quantized outputs; and
a skew adjustment circuit system for determining a plurality of maximum value signals respectively corresponding to the plurality of second quantization outputs within a predetermined period, averaging the plurality of maximum value signals to generate a reference signal, and comparing the reference signal with the plurality of maximum value signals to generate a plurality of adjustment signals to reduce a clock skew in the plurality of analog-to-digital converter circuits.
2. The adc apparatus of claim 1, wherein the skew adjustment circuitry is configured to perform a plurality of absolute value operations on a plurality of difference signals, respectively, to generate a plurality of absolute value signals, and to perform a plurality of maximum value operations on the plurality of absolute value signals, respectively, to generate the plurality of maximum value signals, respectively, wherein the plurality of difference signals are generated according to the plurality of second quantized outputs.
3. The analog-to-digital converter device of claim 1, wherein the skew adjustment circuitry comprises:
a delay circuit for delaying a first one of the plurality of second quantized outputs to generate a delayed quantized output;
a plurality of arithmetic circuits for receiving the delayed quantized output and two signals of the second quantized outputs in sequence to generate a plurality of difference signals, respectively;
a plurality of absolute value circuits, wherein each of the plurality of absolute value circuits is configured to perform an absolute value operation according to a corresponding one of the plurality of difference signals to generate a corresponding one of a plurality of absolute value signals;
a plurality of maximum value circuits, wherein each of the plurality of absolute value circuits is configured to receive a corresponding one of the plurality of absolute value signals and perform a maximum value operation to output a maximum value of the corresponding absolute value signal within the predetermined period as a corresponding one of the plurality of maximum value signals;
an averaging circuit for performing an averaging operation to average the plurality of maximum value signals to generate the reference signal; and
the comparator circuits respectively compare the maximum value signals with the reference signal to generate a plurality of detection signals.
4. The ADC device of claim 3, wherein said skew adjustment circuitry outputs said plurality of detection signals as said plurality of adjustment signals.
5. The analog-to-digital converter device of claim 3, wherein each of the plurality of difference signals satisfies the following equation in time domain:
sin(2πf(k+1)T)-sin(2πfkT)＝2cos(2πfkT+πfT)·(πfT+πfΔt)
where k is used to indicate different sampling time points corresponding to the second quantized outputs, f is the frequency of the input signal, T is the period of each of the clock signals, and Δ T is a time difference.
6. The ADC device of claim 5, wherein the reference signal satisfies the following equation in time domain:
AVG[Max(sin(2πf(k+1)T)-sin(2πfkT))]＝2πfT
where AVG indicates the average operation and Max indicates the maximum operation.
7. The analog-to-digital converter device of claim 3, wherein the skew adjustment circuitry further comprises:
a plurality of filter circuits for generating a plurality of trigger signals according to the plurality of detection signals and at least one threshold value; and
a plurality of integrator circuits, wherein each of the plurality of integrator circuits is configured to accumulate a corresponding one of the plurality of trigger signals and output the accumulated corresponding trigger signal as a corresponding one of the plurality of adjustment signals.
8. The ADC device of claim 7, wherein each of the plurality of filter circuits is configured to accumulate a corresponding one of the plurality of detection signals and output the accumulated corresponding detection signal as a corresponding one of the plurality of trigger signals when the accumulated corresponding detection signal is greater than the at least one threshold.
9. The adc apparatus of any one of claims 1 to 8, wherein the plurality of adc circuitry operate as a time-interleaved adc.
10. A method for clock skew correction, comprising:
performing at least one correction operation according to a plurality of first quantized outputs output from a plurality of analog-to-digital converter circuitry to generate a plurality of second quantized outputs;
determining a plurality of maximum value signals respectively corresponding to the plurality of second quantized outputs within a predetermined period;
averaging the maximum signals to generate a reference signal; and
the reference signal is compared with the maximum value signals respectively to generate a plurality of adjusting signals so as to reduce a clock skew in the analog-to-digital converter circuit systems.
11. The method of claim 10, wherein determining the maximum signals comprises:
performing a plurality of absolute value operations on a plurality of difference signals, respectively, to generate a plurality of absolute value signals, wherein the plurality of difference signals are generated according to the plurality of second quantized outputs; and
performing a plurality of maximum value operations on the plurality of absolute value signals, respectively, to generate the plurality of maximum value signals.
12. The method of claim 10, wherein determining the maximum signals comprises:
delaying a first one of the plurality of second quantized outputs to generate a delayed quantized output;
sequentially generating a plurality of difference signals according to the delayed quantized output and two signals in the plurality of second quantized outputs;
performing an absolute value operation according to a corresponding difference signal of the plurality of difference signals to generate a corresponding one of a plurality of absolute value signals;
receiving a corresponding absolute value signal of the plurality of absolute value signals, and executing a maximum value operation to output a maximum value of the corresponding absolute value signal in the predetermined period as a corresponding one of the plurality of maximum value signals;
performing an averaging operation to average the plurality of maximum signals to generate the reference signal; and
the maximum value signals and the reference signal are respectively compared to generate a plurality of detection signals.
13. The clock skew correction method of claim 12, wherein the detection signals are output as the adjustment signals.
14. The method according to claim 12, wherein the adc circuitry converts an input signal according to interleaved clock signals to generate the first quantized outputs, and each of the difference signals satisfies the following equation in time domain:
sin(2πf(k+1)T)-sin(2πfkT)＝2cos(2πfkT+πfT)·(πfT+πfΔt)
where k is used to indicate different sampling time points corresponding to the second quantized outputs, f is the frequency of the input signal, T is the period of each of the clock signals, and Δ T is a time difference.
15. The method of claim 14, wherein the reference signal satisfies the following equation in time domain:
AVG[Max(sin(2πf(k+1)T)-sin(2πfkT))]＝2πfT
where AVG indicates the average operation and Max indicates the maximum operation.
16. The clock skew correction method of claim 12, further comprising:
generating a plurality of trigger signals according to the plurality of detection signals and at least one critical value; and
accumulating a corresponding one of the plurality of trigger signals to output as a corresponding one of the plurality of adjustment signals.
17. The method according to claim 16, wherein generating the plurality of trigger signals comprises:
accumulating a corresponding detection signal of the plurality of detection signals, and outputting the accumulated corresponding detection signal as a corresponding one of the plurality of trigger signals when the accumulated corresponding detection signal is greater than the at least one threshold value.
18. The method according to any of claims 10-17, wherein the adc circuitry operates as a time-interleaved adc.
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