CN113162622B - Analog-to-digital converter device and clock skew correction method - Google Patents
Analog-to-digital converter device and clock skew correction method Download PDFInfo
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- CN113162622B CN113162622B CN202010074212.XA CN202010074212A CN113162622B CN 113162622 B CN113162622 B CN 113162622B CN 202010074212 A CN202010074212 A CN 202010074212A CN 113162622 B CN113162622 B CN 113162622B
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
An analog-to-digital converter device and a clock skew correction method are disclosed. The analog-to-digital converter device includes: a plurality of analog-to-digital conversion circuits, a correction circuit, and a skew adjustment circuit. The analog-to-digital conversion circuits are used for converting input signals according to the interleaved clock signals to generate a plurality of first quantized outputs. The correction circuit is used for performing at least one correction operation according to the first quantized output so as to generate a plurality of second quantized outputs. The skew adjusting circuit is used for determining a plurality of calculation signals respectively corresponding to the second quantized output in a preset period, averaging the calculation signals to generate reference signals, comparing the reference signals with the calculation signals to generate a plurality of detection signals, judging whether to adjust the detection signals according to signal frequencies to generate a plurality of adjustment signals, wherein the adjustment signals are used for reducing clock skew of the analog-digital conversion circuit. Therefore, the effects of reducing the overall power consumption and correcting the period are achieved.
Description
Technical Field
The present invention relates to an adc device, and more particularly, to a time-interleaved adc and a clock skew correction method thereof.
Background
Analog-to-digital converter (ADC) is commonly used in various electronic devices for converting analog signals to digital signals for signal processing. In practical applications, the ADC may affect its resolution or linearity due to gain errors, voltage errors, or timing errors. For timing errors, the prior art needs to set complicated circuits (such as an additional reference ADC circuit and an auxiliary ADC circuit) or utilize off-chip (off-chip) correction to perform correction, so that the power consumption of the ADC or the period required for the correction is higher and higher.
Disclosure of Invention
In a first aspect, an analog-to-digital converter device is provided, comprising: a plurality of analog-to-digital conversion circuits, a correction circuit, and a skew adjustment circuit. The analog-to-digital conversion circuits are used for converting input signals according to the interleaved clock signals to generate a plurality of first quantized outputs. The correction circuit is used for performing at least one correction operation according to the first quantized output so as to generate a plurality of second quantized outputs. The skew adjusting circuit is used for determining a plurality of calculation signals respectively corresponding to the second quantized output in a preset period, averaging the calculation signals to generate reference signals, comparing the reference signals with the calculation signals to generate a plurality of detection signals, judging whether to adjust the detection signals according to signal frequencies to generate a plurality of adjustment signals, wherein the adjustment signals are used for reducing clock skew of the analog-digital conversion circuit.
According to an embodiment of the present invention, the skew adjusting circuit is further configured to perform a plurality of absolute value operations on a plurality of difference signals respectively to generate a plurality of absolute value signals, and to perform a plurality of maximum value operations on the absolute value signals respectively to generate a plurality of maximum value signals, wherein the difference signals are generated according to the second quantized outputs.
According to one embodiment, the skew adjusting circuit multiplies the detection signals with a first ratio to generate the adjustment signals when the signal frequency is greater than a frequency threshold.
According to one embodiment, the skew adjusting circuit multiplies the detection signals by a second ratio to generate the adjustment signals when the signal frequency is smaller than a frequency threshold.
According to one embodiment of the present invention, the skew adjustment circuit includes: a delay circuit for delaying a last one of the second quantized outputs to generate a delayed quantized output; the plurality of operation circuits are used for sequentially receiving the delay quantized output and the second quantized output, and the operation circuits are used for respectively generating a plurality of difference signals according to two signals in the delay quantized output and the second quantized output; the system comprises a plurality of absolute value circuits, a plurality of sampling circuits and a plurality of sampling circuits, wherein each absolute value circuit is used for executing an absolute value operation according to a corresponding difference signal in the difference signals so as to generate a corresponding absolute value signal; a plurality of maximum value circuits, wherein each of the maximum value circuits is used for receiving a corresponding absolute value signal and executing a maximum value operation to output a corresponding maximum value signal, and the corresponding maximum value signal is generated by a maximum value of the corresponding absolute value signal in the preset period; an averaging circuit for performing an averaging operation to average the maximum signals to generate the reference signal; a plurality of comparing circuits for comparing each of the maximum signals with the reference signal to generate the detection signals; and a plurality of multiplication circuits for multiplying the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the adjustment signals.
According to one embodiment of the present invention, the skew adjustment circuit includes: a first adjusting circuit for analyzing even number of the second quantized outputs to generate a first portion of the adjusting signals; and a second adjusting circuit for analyzing odd ones of the second quantized outputs to generate a second portion of the adjusting signals.
According to an embodiment, when the signal frequency is greater than a frequency threshold, the first adjusting circuit is configured to multiply even detection signals among the detection signals by a first ratio to generate the first portion of the adjusting signals; and the second adjusting circuit is used for multiplying odd-numbered detection signals in the detection signals with the first ratio to generate the second part of the adjusting signals.
According to an embodiment, when the signal frequency is smaller than a frequency threshold value, the first adjusting circuit is configured to multiply even-numbered detection signals among the detection signals by a second ratio to generate the first portion of the adjusting signals; and the second adjusting circuit is used for multiplying odd-numbered detection signals in the detection signals by the second ratio to generate the second part of the adjusting signals.
According to an embodiment of the present disclosure, the first adjusting circuit further includes: a delay circuit for delaying a last one of the even quantized outputs to generate a delayed quantized output; the plurality of operation circuits are used for sequentially receiving the delay quantized output and the even number quantized output, and the operation circuits are used for respectively generating a plurality of difference signals according to two signals in the delay quantized output and the second quantized output; the system comprises a plurality of absolute value circuits, a plurality of sampling circuits and a plurality of sampling circuits, wherein each absolute value circuit is used for executing an absolute value operation according to a corresponding difference signal in the difference signals so as to generate a corresponding absolute value signal; each of the plurality of statistical circuits is used for receiving the corresponding absolute value signal in the preset period and executing a statistical operation to output a corresponding calculation signal; an averaging circuit for performing an averaging operation to average the calculated signals to generate the reference signal; a plurality of comparison circuits for comparing each of the calculation signals with the reference signal to generate the detection signals; and a plurality of multiplication circuits for multiplying even number detection signals in the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the first part of the adjustment signals.
According to an embodiment of the present disclosure, the second adjusting circuit further includes: a delay circuit for delaying a last one of the odd quantized outputs to generate a delayed quantized output; a plurality of operation circuits for sequentially receiving the delayed quantized output and the odd quantized outputs, the operation circuits are used for respectively generating a plurality of difference signals according to two signals in the delay quantized output and the second quantized output; the system comprises a plurality of absolute value circuits, a plurality of sampling circuits and a plurality of sampling circuits, wherein each absolute value circuit is used for executing an absolute value operation according to a corresponding difference signal in the difference signals so as to generate a corresponding absolute value signal; each of the plurality of statistical circuits is used for receiving the corresponding absolute value signal in the preset period and executing a statistical operation to output a corresponding calculation signal; an averaging circuit for performing an averaging operation to average the calculated signals to generate the reference signal; a plurality of comparison circuits for comparing each of the calculation signals with the reference signal to generate the detection signals; and a plurality of multiplication circuits for multiplying even number detection signals in the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the first part of the adjustment signals.
In a second aspect of the present invention, a clock skew correction method is provided, including: performing at least one correction operation according to a plurality of first quantized outputs generated by a plurality of analog-to-digital conversion circuits to generate a plurality of second quantized outputs; determining a plurality of calculation signals respectively corresponding to the second quantized output in a preset period through a skew adjusting circuit, and averaging the calculation signals to generate a reference signal; comparing the reference signals with the calculation signals respectively through a skew adjusting circuit to generate a plurality of detection signals; judging whether to adjust the detection signals according to the signal frequency by using a skew adjusting circuit so as to generate a plurality of adjusting signals; the adjusting signal is used for reducing the clock skew of the analog-digital conversion circuit.
According to one embodiment, determining the computing signals further includes: performing a plurality of absolute value operations on a plurality of difference signals respectively to generate a plurality of absolute value signals, wherein the difference signals are generated according to the second quantized outputs; and respectively performing a plurality of maximum value operations on the absolute value signals to generate a plurality of maximum value signals.
According to one embodiment, the skew adjusting circuit multiplies the detection signals with a first ratio to generate the adjustment signals when the signal frequency is greater than a frequency threshold.
According to one embodiment, the skew adjusting circuit multiplies the detection signals by a second ratio to generate the adjustment signals when the signal frequency is greater than a frequency threshold.
According to one embodiment, determining the computing signals further includes: delaying a last one of the second quantized outputs to generate a delayed quantized output; sequentially receiving the delay quantized output and the second quantized outputs, and respectively generating a plurality of difference signals according to two signals in the delay quantized output and the second quantized outputs; performing an absolute value operation according to a corresponding difference signal in the difference signals to generate a corresponding absolute value signal; receiving the corresponding absolute value signal in the preset period, and executing a maximum value operation to output a corresponding maximum value signal, wherein the corresponding maximum value signal is generated by a maximum value of the corresponding absolute value signal in the preset period; performing an average operation to average the maximum signals to generate the reference signal; comparing each maximum value signal with the reference signal to generate detection signals; and multiplying the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the adjustment signals.
According to one embodiment, generating the adjustment signals includes: analyzing even number quantized outputs in the second quantized outputs by a first adjusting circuit to generate a first part of the adjusting signals; and analyzing odd term quantized outputs of the second quantized outputs by a second adjusting circuit to generate a second portion of the adjusting signals.
According to an embodiment, when the signal frequency is greater than a frequency threshold, the first adjusting circuit is configured to multiply even detection signals among the detection signals by a first ratio to generate the first portion of the adjusting signals; and the second adjusting circuit is used for multiplying odd-numbered detection signals in the detection signals with the first ratio to generate the second part of the adjusting signals.
According to an embodiment, when the signal frequency is smaller than a frequency threshold value, the first adjusting circuit is configured to multiply even-numbered detection signals among the detection signals by a second ratio to generate the first portion of the adjusting signals; and the second adjusting circuit is used for multiplying odd-numbered detection signals in the detection signals by the second ratio to generate the second part of the adjusting signals.
According to one embodiment, generating the first portion of the adjustment signals includes: delaying a last one of the even number of quantized outputs to produce a delayed quantized output; sequentially receiving the delay quantized output and the even number quantized output, and respectively generating a plurality of difference signals according to two signals in the delay quantized output and the second quantized output; performing an absolute value operation according to a corresponding difference signal in the difference signals to generate a corresponding absolute value signal; receiving the corresponding absolute value signal in the preset period, and executing a statistical operation to output a corresponding calculation signal; performing an averaging operation to average the calculated signals to generate the reference signal; comparing each of the calculated signals with the reference signal to generate the detection signals; and multiplying an even number of the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the first part of the adjustment signals.
According to one embodiment, generating the second portion of the adjustment signals includes: delaying a last one of the odd quantized outputs to generate a delayed quantized output; sequentially receiving the delayed quantized output and the odd term quantized output, and respectively generating a plurality of difference signals according to two signals in the delayed quantized output and the second quantized output; performing an absolute value operation according to a corresponding difference signal in the difference signals to generate a corresponding absolute value signal; receiving the corresponding absolute value signal in the preset period, and executing a statistical operation to output a corresponding calculation signal; performing an averaging operation to average the calculated signals to generate the reference signal; comparing each of the calculated signals with the reference signal to generate the detection signals; and multiplying the odd detection signal of the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the second part of the adjustment signals.
The analog-digital converter device and the clock skew correction method of the invention mainly selectively adjust the detection signal according to the signal frequency, so that the digital converter device can still obtain clock skew information for correction through simple operation when the input signal frequency is larger than the Nyquist frequency (Nyquist frequency). Thus, the overall power consumption and correction period can be reduced.
Drawings
The foregoing and other objects, features, advantages and embodiments of the disclosure will be apparent from the following description in which:
FIG. 1A is a schematic diagram of an analog-to-digital converter device according to some embodiments of the present disclosure;
FIG. 1B is a schematic diagram of waveforms of the clock signals of FIG. 1A according to some embodiments of the present disclosure;
FIG. 2 is a circuit schematic diagram of the deskew circuitry of FIG. 1A according to some embodiments of the present disclosure;
FIG. 3 is a flowchart of a method for clock skew correction according to some embodiments of the present disclosure;
FIG. 4 is a schematic diagram of an analog-to-digital converter device according to some embodiments of the present disclosure;
FIGS. 5A and 5B are schematic diagrams illustrating the adjusting circuit of FIG. 4 according to some embodiments of the present disclosure; and
FIG. 6 is a flowchart of a method for clock skew correction according to some embodiments of the present disclosure.
[ symbolic description ]
100 … analog-to-digital converter device
110 … analog-to-digital conversion circuit
120 … correction circuit
130 … skew adjusting circuit
132. 134 … regulating circuit
140 … output circuit
CLK 0 ～CLK M-1 … clock signal
Q 0 ～Q M-1 、CQ -2 ～CQ M-1 、CQ -1 … quantized output
SIN … input signal
fs … sampling frequency
TS … sampling period
ST … for a predetermined period
SOUT … digital signal
T 0 ～T M-1 … adjusting signal
205. 207, 209 … delay circuit
210. 212, 214 and … arithmetic circuit
220. 222, 224 and … absolute value circuit
230 … maximum value circuit
232. 234 … statistical circuit
240. 242, 244 … averaging circuit
250. 252, 254 and … comparison circuit
260. 262, 264 and … multiplication circuit
270. 272, 274: filtering circuit
280. 282, 284: integrating circuit
D 0 ～D M-1 … difference signal
A 0 ～A M-1 … absolute value signal
M 0 ～M M-1 … maximum signal
REF, REF1, REF2 … reference signals
SD 0 ～SD M-1 、TSD 0 ～TSD M-1 … detection signal
K … ratio
TH1 … threshold
TR 0 ～TR M-1 … trigger signal
300. 600 … clock skew correction method
Steps S310 to S340, S610 to S640 and 640 …
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or similar elements or method flows.
Referring to fig. 1A and 1B, fig. 1A is a schematic diagram of an analog-to-digital converter (ADC) device 100 according to some embodiments of the present disclosure. FIG. 1B illustrates the plurality of clock signals CLK of FIG. 1A according to some embodiments 0 ～CLK M-1 Is a waveform schematic diagram of (a). In some embodiments, the ADC device 100 operates as a time-interleaved (time-interleaved) ADC having multiple channels.
In some embodiments, the ADC device 100 includes a plurality of analog-to-digital conversion circuits 110 and a correction circuit120. Skew adjustment circuit 130 and output circuit 140. Notably, each ADC circuit 110 operates as a single channel. In other words, in this example, the ADC device 100 includes M channels. In some embodiments, M is an even number. As shown in FIG. 1A, the plurality of analog-to-digital conversion circuits 110 are configured to convert a plurality of clock signals CLK 0 ～CLK M-1 Analog-to-digital conversion of the input signal SIN to generate a corresponding quantized output Q 0 ～Q M-1 。
As shown in FIG. 1B, a plurality of clock signals CLK 0 ～CLK M-1 There is a time interval between two adjacent clock signals, so the 1 st channel and the 2 nd channel perform sampling operation and analog-to-digital conversion at different times. For example, the 1 st channel (i.e., according to the clock signal CLK 0 The operational analog-to-digital conversion circuit 110) samples the input signal SIN at the 1 st sampling time S1, performs analog-to-digital conversion, and the 2 nd channel (i.e., according to the clock signal CLK) 1 The operational analog-to-digital conversion circuit 110) samples the input signal SIN at the 2 nd sampling time S2 and performs analog-to-digital conversion. The difference between the sampling times S1 and S2 is a sampling period TS (the corresponding sampling frequency is fs, i.e., ts=1/fs., and so on), and M channels can operate according to a plurality of interleaving timings.
As mentioned above, the correction circuit 120 is coupled to each of the analog-to-digital conversion circuits 110 to receive a plurality of quantized outputs Q 0 ～Q M-1 . The correction circuit 120 can output Q according to quantization 0 ～Q M-1 Performing at least one correction operation to correct offset and gain errors in the analog-to-digital conversion circuits 110 and generate a plurality of corrected quantized outputs CQ 0 ～CQ M-1 。
In some embodiments, the correction circuit 120 may be a foreground correction circuit or a background correction circuit. For example, the calibration circuit 120 may include a pseudo-random number generator circuit (not shown) and a digital processing circuit (not shown), wherein the pseudo-random number generator circuit generates a calibration signal to the analog-to-digital conversion circuit 110 and is digital The processing circuit can output Q according to multiple quantization 0 ～Q M-1 Performing an adaptive algorithm (i.e., at least one correction algorithm) to reduce the quantization output Q 0 ～Q M-1 Offset or error of (a). The correction circuit 120 is only used for example, and the disclosure is not limited thereto. Various types of correction operations and correction circuits 120 are within the scope of the present disclosure.
As described above, the skew adjusting circuit 130 is electrically coupled to the correction circuit 120 to receive the plurality of corrected quantized output CQ 0 ～CQ M-1 . In some embodiments, the skew adjustment circuit 130 can output CQ according to quantization 0 ～CQ M-1 Analyzing clock skew (corresponding to phase error) existing between the analog-to-digital conversion circuits 110 to generate a plurality of adjustment signals T 0 ～T M-1 . In some embodiments, the skew adjustment circuitry 130 adjusts the plurality of adjustment signals T 0 ～T M-1 Respectively output to a plurality of analog-digital conversion circuits 110, a plurality of adjusting signals T 0 ～T M-1 To indicate the timing of the multiple analog-to-digital conversion circuits 110 to be adjusted due to the clock skew.
In some embodiments, the plurality of analog-to-digital conversion circuits 110 can be configured according to a plurality of adjustment signals T 0 ～T M-1 The execution timing of the sampling operation and/or the analog-to-digital conversion operation is adjusted to equivalently correct the clock skew. Alternatively, in some embodiments, multiple clock signals CLK 0 ～CLK M-1 Can be directly based on multiple adjusting signals T 0 ～T M-1 Is adjusted to equivalently reduce clock skew. For example, a plurality of adjustment signals T 0 ～T M-1 Is input to generate a plurality of clock signals CLK 0 ～CLK M-1 A clock generator, a phase interpolator or a digital delay control line for adjusting a plurality of clock signals CLK 0～ CLK M-1 Is a phase of (a) of (b). Based on the adjustment signal T 0 ～T M-1 The arrangement for reducing clock skew is used for example, and the disclosure is not limited thereto.
As mentioned above, the output circuit 140 is electrically coupled to the correction circuit 120 for connectionReceiving corrected quantized outputs CQ 0 ～CQ M-1 . The output circuit 140 outputs CQ according to the corrected plurality of quantization operations 0 ～CQ M-1 A data combining operation is performed to generate a digital signal SOUT. Multiple quantized outputs CQ provided by M channels can be combined by data 0 ～CQ M-1 The combination is a single digital signal SOUT with a sampling frequency fs, wherein the sampling frequency fs is M times the clock signal frequency. In some embodiments, the output circuit 140 may be implemented by a multiplexer circuit, but the disclosure is not limited thereto.
Referring to fig. 2, fig. 2 is a circuit diagram illustrating the skew adjustment circuitry 130 of fig. 1A according to some embodiments of the present disclosure. For ease of understanding, similar elements of fig. 2 will be designated with the same reference numerals with reference to fig. 1A. In some embodiments, the skew adjusting circuit 130 includes a delay circuit 205, a plurality of operation circuits 210, a plurality of absolute value circuits 220, a plurality of maximum circuits 230, an average circuit 240, a plurality of comparison circuits 250, and a plurality of multiplication circuits 260.
Delay circuit 205 is used to delay the quantized output CQ of FIG. 1A M-1 To generate delayed quantized output CQ -1 . In some embodiments, the delay time introduced by the delay circuit 205 corresponds to the period m×ts in fig. 1B. The delay circuit 205 may be implemented by various digital circuits, such as buffers, inverters, filters, and the like. The above-described implementation of the delay circuit 205 is for example, and the disclosure is not limited thereto.
The plurality of operation circuits 210 are electrically coupled to the calibration circuit 120 in fig. 1A. The plurality of arithmetic circuits 210 sequentially receive the quantized output CQ -1 To CQ M-1 Two of them to generate multiple difference signals D 0 ～D M-1 . Taking the 1 st arithmetic circuit 210 as an example, the 1 st arithmetic circuit 210 receives the quantized output CQ -1 And CQ (CQ) 0 And output the quantized CQ 0 Subtracting quantized output CQ -1 To generate a difference signal D 0 . The arrangement and operation of the remaining operation circuits 210 can be similarly deduced, so that the description thereof will not be repeated. In some embodiments, the operation circuit 210 may be a subtractor or the likeProcessing circuitry implementing the same functions. Various circuits implementing the operation circuit 210 are within the scope of the present disclosure.
The absolute value circuits 220 are electrically coupled to the operation circuits 210, respectively, to receive the difference signals D 0 ～D M-1 . Each absolute value circuit 220 is based on a plurality of difference signals D 0 ～D M-1 An absolute value operation is performed on a corresponding difference signal of the plurality of absolute value signals A to generate a plurality of absolute value signals A 0 ～A M-1 One of which corresponds to the other. Taking the 1 st absolute value circuit 220 as an example, the 1 st absolute value circuit 220 receives the difference signal D 0 And performs an absolute value operation to obtain a difference signal D 0 To generate an absolute value signal A 0 . The arrangement and operation of the remaining absolute value circuit 220 can be similarly deduced, so that the description thereof will not be repeated. In some embodiments, the absolute value circuit 220 may be implemented by a processing circuit or a rectifying circuit, and various circuits implementing the absolute value circuit 220 are within the scope of the present disclosure.
The maximum value circuits 230 are electrically coupled to the absolute value circuits 220, respectively, to receive the absolute value signals a 0 ～A M-1 . Each maximum value circuit 230 is configured to continuously receive a plurality of absolute value signals A in a predetermined period ST 0 ～A M-1 A corresponding absolute value signal of the first signal and a maximum value operation is performed to output a corresponding maximum value signal M 0 ～M M-1 . Corresponding maximum value signal M 0 ～M M-1 Is generated by a maximum value of the corresponding absolute value signal within a predetermined period ST. The arrangement and operation of the remaining maximum value circuit 230 can be similarly deduced, so that the description thereof will not be repeated.
In some embodiments, the maximum value circuit 230 may be implemented by a digital processing circuit, a comparison circuit and/or a register circuit, but the disclosure is not limited thereto. Various circuits implementing the maximum circuit 230 are within the scope of the present disclosure.
The averaging circuit 240 is electrically coupled to the plurality of maximum circuits 230 for receiving the plurality of maximum signals M 0 ～M M-1 . The averaging circuit 240 is configured to calculate a plurality of maximum valuesSignal M 0 ～M M-1 An averaging operation is performed to average the maximum value signals M 0 ～M M-1 To generate a reference signal REF. In some embodiments, the averaging circuit 240 may be implemented by a digital processing circuit, but the disclosure is not limited thereto.
The plurality of comparison circuits 250 are coupled to the averaging circuit 240 to receive the reference signal REF. Each comparing circuit 250 is used for comparing each maximum value signal M 0 ～M M-1 With the reference signal REF to generate a corresponding detection signal SD 0 ～SD M-1 . Taking the 1 st comparison circuit 250 as an example, the comparison circuit 250 compares the maximum value signal M 0 And a reference signal REF to generate a detection signal SD 0 . The arrangement and operation of the remaining comparison circuit 250 can be similarly deduced, so that the description thereof will not be repeated.
In some embodiments, the comparison circuit 250 may be implemented by a comparator. Alternatively, in some embodiments, the comparison circuit 250 may be implemented as a subtractor circuit and subtracts the corresponding maximum signal M from the reference signal REF 0 ～M M-1 To generate the corresponding detection signal SD 0 ～SD M-1 . The above embodiments regarding the comparator circuit 250 are used as examples, and the disclosure is not limited thereto.
The multiplication circuits 260 are electrically coupled to the comparison circuit 250 for receiving the detection signals SD 0 ～SD M-1 . Each multiplication circuit 260 is used for multiplying each detection signal SD according to the signal frequency 0 ～SD M-1 Multiplying the detection signal by a ratio K to generate a corresponding adjusted detection signal TSD 0 ～TSD M-1 . In some embodiments, multiplication circuit 260 may be implemented as a multiplier circuit. In other embodiments, the multiplication circuit 260 may be implemented by a multiplexer circuit, but the disclosure is not limited thereto.
As mentioned above, when the signal frequency is greater than the frequency threshold, the multiplication circuit 260 is used to multiply the detection signal SD 0 ～SD M-1 Multiplying the ratio K to generate an adjusted detection signal TSD 0 ～TSD M-1 . In one embodiment, the frequency threshold may be implemented as the Nyquist frequency (Nyquist frequency). For example, when the frequency of the input signal SIN is greater than the Nyquist frequency, the ratio K is set to-1, so that the adjusted detection signal TSD 0 ～TSD M Detection signal SD with negative value 0 ～SD M-1 。
As mentioned above, when the signal frequency is smaller than the frequency threshold (i.e. the frequency of the input signal SIN is smaller than the Nyquist frequency), the ratio K is set to 1, so that the adjusted detection signal TSD 0 ～TSD M-1 Detection signal SD 0 ～SD M-1 The same applies.
As described above, taking the operation of the 1 st operation circuit 210 as an example, as shown in FIG. 2, due to the adjustment signal T 0 Is based on quantization output CQ 0 And quantized output CQ -1 The difference between them generates, adjusts the signal T 0 Can be used for indicating time T 0 (i.e., quantized output CQ 0 Corresponding sampling time point) and time T -1 (i.e., quantized output CQ -1 Corresponding sampling time points). Difference signal D 0 The following formula (1) can be derived in the time domain:
CQ 0 -CQ -1 ＝sin(2πf(n+1)(T+Δt))-sin(2πfnT)
≈2cos(2πfnT+πf(T+ΔT))·sin(πfT-πfnΔt)…(1)
wherein (n+1) (T+DeltaT) corresponds to the quantized output CQ 0 Corresponding sampling time points, k, are used to indicate each quantized output CQ 0 Or CQ -1 The corresponding sampling time point, f is the frequency of the input signal SIN, deltat is the time difference, and T is the period TS.
When the frequency of the input signal SIN is much smaller than the nyquist frequency (1/2T), equation (1) can be further derived as the following equation (2):
sin(2πf(n+1)(T+Δt))-sin(2πfnT)≈2cos(2πfnT+πf(T+Δt))·(πfT-πfnΔt)…(2)
as can be seen from equation (2), the time difference Deltat and the difference signal D are calculated under the condition that the frequency f is far less than 1/2T 0 Is related to the amplitude (i.e., pi fT-pi fnDeltat). Thus, by operation of absolute value circuit 220 and maximum value circuit 230, maximum value signal M 0 Can reflect the timeInformation of the difference Δt.
Accordingly, the signal M is calculated by comparison 0 The influence of the time difference Δt due to the clock skew can be obtained from the reference signal REF 1. For example, if the signal M is calculated 0 Greater than the reference signal REF, the effect of the representative time difference Δt is positive. Under this condition, the clock skew causes the clock signal CLK 0 Is not correctly advanced. Alternatively, if the calculated signal M0 is lower than the reference signal REF, the effect of the representative time difference Δt is negative. Under this condition, the clock skew causes the clock signal CLK 0 Is incorrectly lagging behind. Therefore, according to different comparison results, the detection signal TSD is adjusted 0 Will have different logic values to reflect the phase information that the 1 st adc circuit 110 needs to adjust due to clock skew. And so on, the above operations can be applied to the respective adjustment signals T 0 ～T M-1 Adjusted detection signal TSD 0 ～TSD M-1 Therefore, the description is not repeated here.
When the frequency of the input signal SIN is greater than the nyquist frequency (1/2T), equation (1) may be further derived as the following equation (3):
sin(2πf(n+1)(T+Δt))-sin(2πfnT)≈2cos(2πfnT+πf(T+Δt))·sin(-πfT-πfnΔt)…(3)
as can be seen from the equation (3), the time difference Deltat and the difference signal D when the frequency f is greater than 1/2T 0 The difference Deltat and the difference signal D when the amplitude and the related frequency f are smaller than 1/2T 0 Is different by a negative value. In other words, when the frequency f is greater than 1/2T, the operation with the frequency f greater than 1/2T is the same as the operation with the frequency f less than 1/2T by multiplying the frequency f by a negative sign value in the following operation.
In the following operation, the adjusted detection signal TSD can be used when the signal frequency is greater than the Nyquist frequency 0 ～TSD M-1 To reflect the phase information that the analog-to-digital conversion circuit 110 needs to adjust due to the clock skew.
In some related art, the clock skew information is obtained when the signal frequency is smaller than the nyquist frequency. However, with the increase of the input frequency, in the case where it is difficult to increase the sampling frequency, a technique for obtaining information of the clock skew is also required when the signal frequency is greater than the nyquist frequency. In this way, compared with the above-mentioned technology, the embodiment of the present disclosure can achieve that when the input signal frequency is greater than the nyquist frequency, the digitizer device can still obtain the clock skew information for correction through simple operation, so as to achieve lower power consumption and less correction period.
In some further embodiments, the skew adjustment circuit 130 can further include a plurality of filter circuits 270 and a plurality of integrator circuits 280. The filter circuits 270 are respectively coupled to the multiplication circuits 260 for receiving the adjusted detection signals TSD 0 ～TSD M 。
The plurality of filter circuits 270 are configured to adjust the detection signals TSD according to the plurality of adjusted detection signals TSD 0 ～TSD M-1 Generating a plurality of trigger signals TR with at least one threshold TH1 0 ～TR M-1 . The integrating circuits 280 are coupled to the filtering circuits 270 to receive the trigger signals TR 0 ～TR M-1 . The integrating circuits 280 are used for integrating the plurality of signals according to the plurality of trigger signals TR 0 ～TR M-1 Generating a plurality of adjustment signals T 0 ～T M-1 。
As described above, taking the 1 st filter circuit 270 and the 1 st integrating circuit 280 as an example, the filter circuit 270 is electrically coupled to the 1 st multiplying circuit 260 to receive the adjusted detection signal TSD 0 . In some embodiments, the filter circuit 270 may continuously accumulate the adjusted detection signal TSD 0 And compares the accumulated adjusted detection signal TSD 0 And at least one threshold value TH1 for outputting one or more trigger signals TR 0 . For example, when the accumulated adjusted detection signal TSD 0 When the signal is greater than at least one threshold value TH1, the filter circuit 270 adds up the adjusted detection signal TSD 0 Output as corresponding trigger signal TR 0 . The 1 st integrating circuit 280 is coupled to the 1 st filtering circuit 270 for receiving the trigger signal TR 0 . The integrating circuit 280 is used for accumulating the trigger signal TR 0 And accumulate trigger signal TR 0 Output as an adjustment signal T 0 To match with different control timing methods. The arrangement and operation of the remaining filter circuit 270 and the integrating circuit 280 can be similarly deduced, so that the description thereof will not be repeated.
By providing the filter circuit 270, the number of times of execution of the correction of the clock skew can be reduced to reduce the dynamic power consumption of the ADC apparatus 100. Meanwhile, jitter caused by the correction clock skew can be reduced by providing the filter circuit 270. By providing the integrating circuit 280, the timing adjustment method can be matched to adjust the corresponding value. In the practical application of the present invention, the filter circuit 270 and the integrating circuit 280 may be selectively set according to practical requirements. In addition, the threshold TH1 can be adjusted according to actual requirements.
In various embodiments, the filter circuit 270 and the integrating circuit 280 may be implemented by at least one comparator (e.g. for comparing the trigger signal with the threshold TH1 or comparing the accumulated trigger signal), at least one register (e.g. for storing the accumulated trigger signal or the accumulated trigger signal, etc.), at least one clearing circuit (e.g. for clearing the data of the register), and/or at least one operation circuit (e.g. for generating the accumulated trigger signal or for accumulating the trigger signal). The above-mentioned arrangements of the filter circuit 270 and the integrating circuit 280 are used for illustration, and the disclosure is not limited thereto.
Referring to fig. 3, fig. 3 is a flowchart of a clock skew correction method 300 according to some embodiments of the present disclosure. For ease of understanding, the clock skew correction method 300 will be described with reference to the preceding figures. In one embodiment, the clock skew correction method 300 first performs step S310 according to a plurality of quantized outputs Q generated by a plurality of analog-to-digital conversion circuits 110 0 ～Q M-1 Performing at least one correction operation to generate a plurality of quantized output CQ 0 ～CQ M-1 。
The clock skew correction method 300 then proceeds to step S320, where the skew adjustment circuit 130 determines the quantized output CQ 0 ～CQ M-1 A plurality of maximum value signals M respectively corresponding to the predetermined period ST 0 ～M M-1 Average a plurality of maximum value signals M 0 ～M M-1 To generate a reference signal REF.
In step S330, the skew adjusting circuit 130 respectively compares the reference signal REF with the maximum signals M 0 ～M M-1 Comparing to generate a plurality of detection signals SD 0 ～SD M-1 。
In step S340, the skew adjusting circuit 130 determines whether to adjust the detection signal SD according to the signal frequency 0 ～SD M-1 To generate a plurality of adjusting signals T 0 ～T M-1 To reduce clock skew in the plurality of analog to digital conversion circuits 110. The foregoing descriptions of the operations and the implementation manner thereof may refer to the descriptions of the foregoing embodiments, so that the descriptions are not repeated herein.
In another embodiment, fig. 4 is a schematic diagram of an analog-to-digital converter device 400 according to some embodiments of the present disclosure. In some embodiments, the ADC device 400 operates as a time-interleaved (time-interleaved) analog-to-digital converter with multiple channels. In this embodiment, the ADC device 400 is similar to the ADC device 100, and the difference between the two is the implementation of the skew adjusting circuit 130.
As described above, in this embodiment, the skew adjustment circuit 130 includes adjustment circuits 132 and 134. The adjusting circuit 132 is used for analyzing the quantized output CQ 0 ～CQ M-1 Quantized output CQ of even term in (a) 0 、CQ 2 、…、CQ M-2 To generate the adjustment signals T 0 ～T M-1 Is the first part (i.e. T 0 、T 2 、…、T M-2 ) And the adjusting circuit 134 is used for analyzing the quantized output CQ 0 ～CQ M-1 The odd term of (1) quantizing the output CQ 1 、CQ 3 、…、CQ M-1 To generate a plurality of adjusting signals T 0 ～T M-1 Of the second part (i.e.T 1 、T 3 、…、T M-1 )。
The adjusting circuit 132 quantizes the output CQ according to an even number 0 、CQ 2 、…、CQ M-2 Analyzing even terms between analog-to-digital conversion circuits 110The clock skew (corresponding to the time difference information) exists to generate a plurality of adjustment signals T 0 、T 2 、…、T M-2 . Due to quantization of output CQ 0 Corresponds to the 1 st sampling time S1 and quantizes the output CQ 2 Corresponding to the 3 rd sampling time S3, the period difference between the two corresponding times is 2 sampling periods TS, so that the analysis quantization output CQ 0 Quantized output CQ 2 The clock signal CLK can be known 0 And clock signal CLK 2 Time difference information within 2 sampling periods TS. By so doing, the adjusting circuit 132 can analyze the clock signal CLK 0 、CLK 2 、…、CLK M-2 Time difference information within 2 sampling periods TS.
Similarly, the adjustment circuit 134 quantizes the output CQ according to the odd term 1 、CQ 3 、…、CQ M-1 Analyzing clock skew existing between the odd-numbered analog-to-digital conversion circuits 110 to generate a plurality of adjustment signals T 1 、T 3 、…、T M-1 . In this way, the adjusting circuit 134 can analyze the clock signal CLK 1 、CLK 3 、…、CLK M-1 Time difference information within 2 sampling periods TS.
Referring to fig. 5A and 5B, fig. 5A and 5B are schematic circuit diagrams of the adjusting circuit of fig. 4 according to some embodiments of the present disclosure. The adjusting circuit 132 is used to perform a statistical operation to determine an even-numbered quantized output CQ 0 、CQ 2 、…、CQ M-2 A plurality of computing signals respectively corresponding (e.g. M in FIG. 5A 0 、M 2 、…、M M-2 ) And averages these calculated signals to produce a reference signal (e.g., REF1 in fig. 5A). The adjusting circuit 132 further compares the reference signal with a plurality of calculated signals to generate a plurality of adjusting signals T 0 、T 2 、…、T M-2 . The operation thereof will be described in detail with reference to fig. 5A in the following paragraphs.
Accordingly, in some embodiments, the adjustment circuit 134 is configured to perform a statistical operation to determine the odd term quantized output CQ 1 、CQ 3 、…、CQ M-1 A plurality of computing signals respectively corresponding (e.g. M in FIG. 5B 1 、M 3 、…、M M-1 ) And averages these calculated signals to produce a reference signal (e.g., REF2 in fig. 5B). The adjusting circuit 134 further compares the reference signal with a plurality of calculated signals to generate a plurality of adjusting signals T 1 、T 3 、…、T M-1 。
In some embodiments, the analog-to-digital conversion circuits 110 may adjust the sampling operation and/or the execution timing of the analog-to-digital conversion operation according to the adjustment signals T0-TM-1 to equivalently correct the clock skew. The operation of the analog-to-digital conversion circuit 110 is similar to that of the previous embodiment, and will not be described again.
As shown in fig. 5A, the adjusting circuit 132 includes a delay circuit 207, a plurality of arithmetic circuits 212, an absolute value circuit 222, a statistics circuit 232, an averaging circuit 242, a comparator circuit 252, and a multiplication circuit 262. The operations of the delay circuit 207, the plurality of operation circuits 212, the absolute value circuit 222, the average circuit 242 and the comparator circuit 252 are similar to those of the delay circuit 205, the plurality of operation circuits 210, the absolute value circuit 220, the average circuit 240 and the comparator circuit 250 in the foregoing embodiments, and are not repeated herein.
As mentioned above, the plurality of statistics circuits 232 are respectively coupled to the plurality of absolute value circuits 222 for respectively receiving the plurality of absolute value signals A 0 、A 2 、…、A M-2 . Each of the statistics circuits 232 is configured to continuously receive a plurality of absolute value signals A during a predetermined period ST 0 、A 2 、…、A M-2 A corresponding absolute value signal of the plurality of calculation signals M is outputted by performing a statistical operation 0 、M 2 、…、M M-2 One of which corresponds to the above.
In some embodiments, the statistical operation may be a maximum value operation or an average operation. Taking the 1 ST statistical circuit 232 as an example, the 1 ST statistical circuit 232 continuously receives the absolute value signal A in the preset period ST 0 And performs a maximum value operation to output the maximum absolute value signal A received within the predetermined period ST 0 To calculate the signal M 0 . Alternatively, the 1 ST statistical circuit 232 may be configured to perform the statistical process within the predetermined period STContinuously receiving absolute value signal A 0 And performs an averaging operation to average all absolute value signals A received within the predetermined period ST 0 To calculate the signal M 0 . The setting and operation of the remaining statistics circuit 232 can be analogized, so that the detailed description is not repeated.
In some embodiments, the statistics circuit 232 may be implemented by digital processing circuits, comparator circuits, and/or register circuits, but the disclosure is not limited thereto. Various circuits implementing the statistics circuit 232 are within the scope of the present disclosure.
As described above, the operation of multiplication circuit 262 is similar to that of multiplication circuit 260. The multiplication circuits 262 are electrically coupled to the comparison circuit 252 for receiving the detection signals SD 0 、…、SD M-2 . Each multiplication circuit 262 is used for multiplying each detection signal SD according to the signal frequency 0 、…、SD M-2 Multiplying the detection signal by a ratio K to generate a corresponding adjusted detection signal TSD 0 、…、TSD M-2 。
As mentioned above, when the signal frequency is greater than the frequency threshold, the multiplication circuit 262 is used to multiply the detection signal SD 0 、…、SD M-2 Multiplying the ratio K to generate an adjusted detection signal TSD 0 、…、TSD M-2 . In one embodiment, the frequency threshold may be implemented as the nyquist frequency. For example, when the frequency of the input signal SIN is greater than the Nyquist frequency, the ratio K is set to-1, so that the adjusted detection signal TSD 0 、…、TSD M-2 Detection signal SD with negative value 0 、…、SD M-2 。
As mentioned above, when the signal frequency is smaller than the frequency threshold (i.e. the frequency of the input signal SIN is smaller than the Nyquist frequency), the ratio K is set to 1, so that the adjusted detection signal TSD 0 、…、TSD M-2 Detection signal SD 0 、…、SD M-2 The same applies.
As described above, taking the operation of the 2 nd operation circuit 212 as an example, as shown in FIG. 5A, since the adjustment signal T2 is based on the quantized output CQ 0 And quantized output CQ 2 The difference between them generates an adjustment signal T2 which can be used to indicate quantizationOutput CQ 0 Corresponding sampling time S1 and quantized output CQ 2 The time difference between the corresponding sampling times S3. The derivation of the difference signal D2 in the time domain is the same as that of the equation (1), and will not be described here again.
In some embodiments, the adjusting circuit 132 may further include a plurality of filtering circuits 272 and a plurality of integrating circuits 282. The filter circuits 272 are coupled to the multiplication circuits 262 to receive the adjusted detection signals TSD 0 、TSD 2 、…、TSD M-2 . The embodiments of the filter circuit 272 and the integration circuit 282 are similar to the filter circuit 270 and the integration circuit 280 described above, and are not repeated here.
Referring to fig. 5B, as shown in fig. 5B, the adjusting circuit 134 includes a delay circuit 209, a plurality of operation circuits 214, an absolute value circuit 224, a statistics circuit 234, an averaging circuit 244, a comparator circuit 254, a multiplication circuit 264, a filter circuit 274, and an integration circuit 284. The circuit structure of the adjusting circuit 134 is the same as that of the adjusting circuit 132, and the operation thereof is similar to that of the adjusting circuit 132, and will not be described again.
Referring to fig. 6, fig. 6 is a flowchart of a method 600 for clock skew correction according to some embodiments of the present disclosure. For ease of understanding, the clock skew correction method 600 will be described with reference to the preceding figures. In one embodiment, the clock skew correction method 600 first performs step S610 according to a plurality of quantized outputs Q generated by a plurality of analog-to-digital conversion circuits 110 0 ～Q M-1 Performing at least one correction operation to generate a plurality of quantized output CQ 0 ～CQ M-1 。
The clock skew correction method 600 then proceeds to step S620, where the quantized output CQ is determined by the adjustment circuit 132 0 、…、CQ M-2 A plurality of corresponding calculation signals M in a preset period ST 0 、…、M M-2 Average a plurality of calculated signals M 0 、…、M M-2 To generate a reference signal REF1; determining the quantized output CQ by the skew adjustment circuit 134 -1 、…、CQ M-1 A plurality of corresponding calculation signals M in a preset period ST 1 、…、M M-1 Average a plurality of calculated signals M 1 、…、M M-1 To generate a reference signal REF2.
In step S630, the reference signal REF1 is respectively coupled to the plurality of calculation signals M by the adjusting circuit 132 0 、…、M M-2 Comparing to generate a plurality of detection signals SD 0 、…、SD M-2 The method comprises the steps of carrying out a first treatment on the surface of the The reference signal REF2 is respectively coupled to a plurality of calculation signals M by the adjusting circuit 134 1 、…、M M-1 Comparing to generate a plurality of detection signals SD 1 、…、SD M-1 。
In step S640, the adjusting circuit 132 determines whether to adjust the detection signal SD according to the signal frequency 0 、…、SD M-2 To generate a plurality of adjusting signals T 0 、…、T M-2 And determining whether to adjust the detection signal SD according to the signal frequency by the adjusting circuit 134 1 、…、SD M-1 To generate a plurality of adjusting signals T 1 、…、T M-1 To reduce clock skew in the multiple analog to digital conversion circuits 110. The foregoing descriptions of the operations and the implementation manner thereof may refer to the descriptions of the foregoing embodiments, so that the descriptions are not repeated herein.
In summary, the adc device and the clock skew correction method of the present disclosure selectively adjust the detection signal according to the signal frequency, so that the adc device can still obtain the clock skew information for correction by simple operation when the input signal frequency is greater than the nyquist frequency (Nyquist frequency). Thus, the overall power consumption and correction period can be reduced.
Certain terms are used throughout the description and claims to refer to particular components. However, it will be understood by those of ordinary skill in the art that like elements may be referred to by different names. The description and claims do not take the difference in name as a way of distinguishing elements, but rather take the difference in function as a basis for distinguishing elements. In the description and claims, the terms "comprise" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, "coupled" herein encompasses any direct and indirect connection. Thus, if a first element couples to a second element, that connection may be through an electrical or wireless transmission, optical transmission, etc., directly to the second element, or through other elements or connections indirectly to the second element.
In addition, any singular reference is intended to encompass a plural reference unless the specification expressly states otherwise.
The foregoing is only one preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.
Claims (20)
1. An analog-to-digital converter apparatus, comprising:
the analog-digital conversion circuits are used for converting an input signal according to a plurality of staggered clock signals to generate a plurality of first quantized outputs;
a correction circuit for performing at least one correction operation according to the first quantized outputs to generate a plurality of second quantized outputs; and
and the skew adjusting circuit is used for determining a plurality of calculation signals respectively corresponding to the second quantized outputs in a preset period, averaging the calculation signals to generate a reference signal, comparing the reference signal with the calculation signals to generate a plurality of detection signals, judging whether to adjust the detection signals according to a signal frequency to generate a plurality of adjusting signals, wherein the adjusting signals are used for reducing clock skew of the analog-digital conversion circuits.
2. The adc device of claim 1, wherein the skew adjustment circuit is further configured to perform a plurality of absolute value operations on a plurality of difference signals, respectively, to generate a plurality of absolute value signals, and to perform a plurality of maximum value operations on the absolute value signals, respectively, to generate a plurality of maximum value signals, wherein the difference signals are generated according to the second quantized outputs.
3. The analog-to-digital converter apparatus of claim 1, wherein the skew adjustment circuit multiplies the detection signals by a first ratio to generate the adjustment signals when the signal frequency is greater than a frequency threshold.
4. The adc device of claim 1, wherein the skew adjustment circuit multiplies the detection signals by a second ratio to generate the adjustment signals when the signal frequency is less than a frequency threshold.
5. The analog-to-digital converter apparatus of claim 2, wherein the skew adjustment circuit comprises:
a delay circuit for delaying a last one of the second quantized outputs to generate a delayed quantized output;
the plurality of operation circuits are used for sequentially receiving the delay quantized output and the second quantized output, and the operation circuits are used for respectively generating a plurality of difference signals according to two signals in the delay quantized output and the second quantized output;
the system comprises a plurality of absolute value circuits, a plurality of sampling circuits and a plurality of sampling circuits, wherein each absolute value circuit is used for executing an absolute value operation according to a corresponding difference signal in the difference signals so as to generate a corresponding absolute value signal;
A plurality of maximum value circuits, wherein each of the maximum value circuits is used for receiving a corresponding absolute value signal and executing a maximum value operation to output a corresponding maximum value signal, and the corresponding maximum value signal is generated by a maximum value of the corresponding absolute value signal in the preset period;
an averaging circuit for performing an averaging operation to average the maximum signals to generate the reference signal;
a plurality of comparing circuits for comparing each of the maximum signals with the reference signal to generate the detection signals; and
the plurality of multiplication circuits are used for multiplying the detection signals with one of a first ratio and a second ratio according to the signal frequency to generate the adjustment signals.
6. The analog-to-digital converter apparatus of claim 1, wherein the skew adjustment circuit comprises:
a first adjusting circuit for analyzing even number of the second quantized outputs to generate a first portion of the adjusting signals; and
a second adjusting circuit is used for analyzing odd term quantized outputs in the second quantized outputs to generate a second part of the adjusting signals.
7. The analog-to-digital converter device of claim 6, wherein when the signal frequency is greater than a frequency threshold, the first adjusting circuit multiplies the even detection signal of the detection signals by a first ratio to generate the first portion of the adjusting signals; and the second adjusting circuit is used for multiplying odd-numbered detection signals in the detection signals with the first ratio to generate the second part of the adjusting signals.
8. The analog-to-digital converter apparatus of claim 6, wherein the first adjusting circuit multiplies even detection signals of the detection signals by a second ratio to generate the first portion of the adjusting signals when the signal frequency is less than a frequency threshold; and the second adjusting circuit is used for multiplying odd-numbered detection signals in the detection signals by the second ratio to generate the second part of the adjusting signals.
9. The analog-to-digital converter apparatus of claim 6, wherein the first adjusting circuit further comprises:
a delay circuit for delaying a last one of the even quantized outputs to generate a delayed quantized output;
The plurality of operation circuits are used for sequentially receiving the delay quantized output and the even number quantized output, and the operation circuits are used for respectively generating a plurality of difference signals according to two signals in the delay quantized output and the second quantized output;
the system comprises a plurality of absolute value circuits, a plurality of sampling circuits and a plurality of sampling circuits, wherein each absolute value circuit is used for executing an absolute value operation according to a corresponding difference signal in the difference signals so as to generate a corresponding absolute value signal;
each of the plurality of statistical circuits is used for receiving the corresponding absolute value signal in the preset period and executing a statistical operation to output a corresponding calculation signal;
an averaging circuit for performing an averaging operation to average the calculated signals to generate the reference signal;
a plurality of comparison circuits for comparing each of the calculation signals with the reference signal to generate the detection signals; and
the multiplication circuits are used for multiplying even number detection signals in the detection signals with one of a first ratio and a second ratio according to the signal frequency to generate the first part of the adjustment signals.
10. The analog-to-digital converter apparatus of claim 6, wherein the second adjusting circuit further comprises:
A delay circuit for delaying a last one of the odd quantized outputs to generate a delayed quantized output;
the plurality of operation circuits are used for sequentially receiving the delay quantized output and the odd term quantized output, and the operation circuits are used for respectively generating a plurality of difference signals according to two signals in the delay quantized output and the second quantized output;
the system comprises a plurality of absolute value circuits, a plurality of sampling circuits and a plurality of sampling circuits, wherein each absolute value circuit is used for executing an absolute value operation according to a corresponding difference signal in the difference signals so as to generate a corresponding absolute value signal;
each of the plurality of statistical circuits is used for receiving the corresponding absolute value signal in the preset period and executing a statistical operation to output a corresponding calculation signal;
an averaging circuit for performing an averaging operation to average the calculated signals to generate the reference signal;
a plurality of comparison circuits for comparing each of the calculation signals with the reference signal to generate the detection signals; and
and a plurality of multiplication circuits for multiplying odd detection signals of the detection signals by one of a first ratio and a second ratio according to the signal frequency to generate the second part of the adjustment signals.
11. A method for clock skew correction, comprising:
performing at least one correction operation according to a plurality of first quantized outputs generated by a plurality of analog-to-digital conversion circuits to generate a plurality of second quantized outputs;
determining a plurality of calculation signals respectively corresponding to the second quantized outputs in a preset period through a skew adjusting circuit, and averaging the calculation signals to generate a reference signal;
comparing the reference signal with the calculation signals respectively by the skew adjusting circuit to generate a plurality of detection signals; and
judging whether to adjust the detection signals according to a signal frequency by the skew adjusting circuit so as to generate a plurality of adjusting signals;
the adjusting signals are used for reducing clock skew of the analog-digital conversion circuits.
12. The method of claim 11, wherein determining the computing signals further comprises:
performing a plurality of absolute value operations on a plurality of difference signals respectively to generate a plurality of absolute value signals, wherein the difference signals are generated according to the second quantized outputs; and
a plurality of maximum value operations are respectively performed on the absolute value signals to generate a plurality of maximum value signals.
13. The method of claim 11, wherein the skew adjustment circuit multiplies the detection signals by a first ratio to generate the adjustment signals when the signal frequency is greater than a frequency threshold.
14. The method of claim 11, wherein the skew adjustment circuit multiplies the detection signals by a second ratio to generate the adjustment signals when the signal frequency is greater than a frequency threshold.
15. The method of claim 12, wherein determining the computing signals further comprises:
delaying a last one of the second quantized outputs to generate a delayed quantized output;
sequentially receiving the delay quantized output and the second quantized outputs, and respectively generating a plurality of difference signals according to two signals in the delay quantized output and the second quantized outputs;
performing an absolute value operation according to a corresponding difference signal in the difference signals to generate a corresponding absolute value signal;
receiving the corresponding absolute value signal in the preset period, and executing a maximum value operation to output a corresponding maximum value signal, wherein the corresponding maximum value signal is generated by a maximum value of the corresponding absolute value signal in the preset period;
Performing an average operation to average the maximum signals to generate the reference signal;
comparing each maximum value signal with the reference signal to generate detection signals; and
the detection signals are multiplied by one of a first ratio and a second ratio according to the signal frequency to generate the adjustment signals.
16. The method of claim 11, wherein generating the adjustment signals comprises:
analyzing even number quantized outputs in the second quantized outputs by a first adjusting circuit to generate a first part of the adjusting signals; and
the odd term quantized outputs of the second quantized outputs are analyzed by a second adjusting circuit to generate a second portion of the adjusting signals.
17. The method of claim 16, wherein the first adjusting circuit multiplies even detection signals of the detection signals by a first ratio to generate the first portion of the adjustment signals when the signal frequency is greater than a frequency threshold; and the second adjusting circuit is used for multiplying odd-numbered detection signals in the detection signals with the first ratio to generate the second part of the adjusting signals.
18. The method of claim 16, wherein the first adjusting circuit multiplies even detection signals of the detection signals by a second ratio to generate the first portion of the adjustment signals when the signal frequency is less than a frequency threshold; and the second adjusting circuit is used for multiplying odd-numbered detection signals in the detection signals by the second ratio to generate the second part of the adjusting signals.
19. The method of claim 16, wherein generating the first portion of the adjustment signals comprises:
delaying a last one of the even number of quantized outputs to produce a delayed quantized output;
sequentially receiving the delay quantized output and the even number quantized output, and respectively generating a plurality of difference signals according to two signals in the delay quantized output and the second quantized output;
performing an absolute value operation according to a corresponding difference signal in the difference signals to generate a corresponding absolute value signal;
receiving the corresponding absolute value signal in the preset period, and executing a statistical operation to output a corresponding calculation signal;
Performing an averaging operation to average the calculated signals to generate the reference signal;
comparing each of the calculated signals with the reference signal to generate the detection signals; and
the even number of the detection signals is multiplied by one of a first ratio and a second ratio according to the signal frequency to generate the first portion of the adjustment signals.
20. The method of claim 16, wherein generating the second portion of the adjustment signals comprises:
delaying a last one of the odd quantized outputs to generate a delayed quantized output;
sequentially receiving the delayed quantized output and the odd term quantized output, and respectively generating a plurality of difference signals according to two signals in the delayed quantized output and the second quantized output;
performing an absolute value operation according to a corresponding difference signal in the difference signals to generate a corresponding absolute value signal;
receiving the corresponding absolute value signal in the preset period, and executing a statistical operation to output a corresponding calculation signal;
performing an averaging operation to average the calculated signals to generate the reference signal;
Comparing each of the calculated signals with the reference signal to generate the detection signals; and
the odd detection signals of the detection signals are multiplied by one of a first ratio and a second ratio according to the signal frequency to generate the second part of the adjustment signals.
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| EP0838903A1 (en) * | 1996-10-25 | 1998-04-29 | THOMSON multimedia | Conversion of an analog signal into a digital signal, in particular a tv video signal |
| EP1445852A2 (en) * | 2003-02-07 | 2004-08-11 | Baumüller Nürnberg Gmbh | Device and method for active power factor correction |
| WO2011039859A1 (en) * | 2009-09-30 | 2011-04-07 | 株式会社日立製作所 | Analog/digital converter and semiconductor integrated circuit device using the same |
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