CN115225085A

CN115225085A - Analog-digital converter device and correction circuit control method

Info

Publication number: CN115225085A
Application number: CN202110430305.6A
Authority: CN
Inventors: 韩昕翰; 陈昱竹; 康文柱
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Priority date: 2021-04-21
Filing date: 2021-04-21
Publication date: 2022-10-21

Abstract

An analog-digital converter device and a correction circuit control method are provided, the device comprises a plurality of analog-digital conversion circuits, a correction circuit and a control circuit. The analog-to-digital conversion circuits are used for generating a plurality of first quantized outputs according to a plurality of clock signals. The correction circuit is used for executing at least one error operation according to the first quantized outputs to generate a plurality of second quantized outputs, and analyzing a plurality of time difference information of a plurality of clock signals according to the second quantized outputs to generate a plurality of adjusting signals. The control circuit is used for analyzing the first quantized outputs to generate at least one control signal to the correction circuit, wherein the at least one control signal is used for controlling the correction circuit to selectively execute at least one error operation and selectively analyze a plurality of time difference information of the clock signals. The control circuit generates at least one control signal for controlling the correction circuit, so that the problem that the correction carried out by the correction circuit is influenced because the input signal is weak is avoided.

Description

Analog-digital converter device and correction circuit control method

Technical Field

The present disclosure relates to an analog-to-digital converter and a control method of a calibration circuit, and more particularly, to a time-interleaved analog-to-digital converter and a control method of a calibration circuit.

Background

Analog-to-digital converters (ADCs) are commonly used in various electronic devices to convert analog signals into digital signals for signal processing. In practical applications, the ADC may affect its own resolution or linearity due to gain error, offset error or timing error. In which, when the input signal is weak (e.g., too small amplitude or too small power), the prior art is susceptible to the three errors, so that the phase errors between different channels may not be correctly converged.

Disclosure of Invention

One aspect of the present disclosure is an analog-to-digital converter device. The analog-digital converter device comprises a plurality of analog-digital conversion circuits, a correction circuit and a control circuit. The analog-to-digital conversion circuits are used for converting an input signal according to a plurality of staggered clock signals so as to generate a plurality of first quantized outputs. The correction circuit is used for executing at least one error operation according to the first quantized outputs to generate at least one correction information, correcting the first quantized outputs by using the at least one correction information to generate a plurality of second quantized outputs, and analyzing a plurality of time difference information of the clock signals according to the second quantized outputs to generate a plurality of adjustment signals, wherein the adjustment signals are used for reducing a clock skew of the analog-digital conversion circuits. The control circuit receives the first quantized outputs and analyzes the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is used for controlling the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.

In another embodiment, the control circuit analyzes the first quantized outputs of the nth cycle to generate the at least one control signal of the nth cycle, and the correction circuit selectively performs the at least one error operation on the first quantized outputs of the (N + 1) th cycle according to the at least one control signal of the nth cycle, and selectively analyzes the time difference information of the clock signals of the (N + 1) th cycle, where N is a positive integer.

In another embodiment, when the correction circuit performs the at least one error operation on the first quantized outputs of the (N + 1) th cycle, the correction circuit corrects the first quantized outputs of the (N + 1) th cycle by using the at least one correction information generated according to the first quantized outputs of the (N + 1) th cycle to generate the second quantized outputs of the (N + 1) th cycle.

In another embodiment, when the correction circuit does not perform the at least one error operation on the first quantized outputs of the (N + 1) th cycle, the correction circuit corrects the first quantized outputs of the (N + 1) th cycle by using the at least one correction information generated previously to generate the second quantized outputs of the (N + 1) th cycle.

In another embodiment, when the calibration circuit analyzes the time difference information of the clock signals of the (N + 1) th cycle, the calibration circuit analyzes the second quantized outputs of the (N + 1) th cycle to generate the adjustment signals of the (N + 1) th cycle.

In another embodiment, when the calibration circuit does not analyze the time difference information of the clock signals of the (N + 1) th cycle, the calibration circuit outputs the adjustment signals of the nth cycle.

In another embodiment, the control circuit comprises: a plurality of absolute value circuits for receiving the first quantized outputs to output a plurality of absolute value signals, wherein each absolute value circuit is configured to perform an absolute value operation according to a corresponding one of the first quantized outputs to generate a corresponding one of the absolute value signals; an averaging circuit for performing an averaging operation to average the absolute value signals to generate an average signal; a filter circuit for filtering the average signal; and a comparison circuit for comparing the filtered average signal with at least one threshold value to generate the at least one control signal.

In another embodiment, the calibration circuit comprises: a skew adjusting circuit for analyzing the second quantized outputs to generate the adjusting signals to the analog-to-digital converting circuits.

In another embodiment, the at least one calibration information comprises a gain calibration information, the at least one error operation comprises a gain error operation, and the calibration circuit further comprises: a gain correction circuit for performing the gain error operation to generate the gain correction information according to the first quantized outputs, and generating the second quantized outputs using the gain correction information.

In another embodiment, the at least one calibration message further comprises an offset calibration message, the at least one error operation further comprises an offset error operation, and the calibration circuit further comprises: an offset correction circuit receiving the first quantized outputs, performing the offset error operation according to the first quantized outputs to generate the offset correction information, and correcting the first quantized outputs by using the offset correction information to generate third quantized outputs, wherein the gain correction circuit corrects the third quantized outputs by using the gain correction information to generate the second quantized outputs.

Another aspect of the present disclosure is a calibration circuit control method. The correction circuit control method comprises the following steps: receiving a plurality of first quantized outputs generated by a plurality of analog-to-digital conversion circuits according to a plurality of staggered clock signals through a control circuit; analyzing the first quantized outputs by the control circuit to generate at least one control signal to a correction circuit; selectively performing at least one error operation according to the at least one control signal to generate at least one correction information and selectively analyzing a plurality of time difference information of the clock signals to generate a plurality of adjustment signals by the correction circuit, wherein the adjustment signals are used for reducing a clock skew of the analog-to-digital conversion circuits; and correcting the first quantized outputs by the correction circuit to generate a plurality of second quantized outputs.

In another embodiment, generating the at least one control signal comprises: performing an absolute value operation according to a corresponding one of the first quantized outputs to generate a corresponding one of a plurality of absolute value signals; performing an averaging operation to average the absolute value signals to generate an average signal; performing a filtering operation on the average signal; and comparing the filtered average signal with at least one threshold value to generate the at least one control signal.

In another embodiment, generating the adjustment signals comprises: the second quantized outputs are analyzed by a skew adjusting circuit of the correcting circuit to generate the adjusting signals to the analog-to-digital converting circuits.

In another embodiment, the at least one correction information comprises a gain correction information, the at least one error operation comprises a gain error operation, and generating the second quantized outputs comprises: the gain error operation is performed by a gain correction circuit of the correction circuit according to the first quantized outputs to generate the gain correction information, and the second quantized outputs are generated by using the gain correction information.

In another embodiment, the at least one correction information further comprises an offset correction information, the at least one error operation further comprises an offset error operation, and generating the second quantized outputs further comprises: receiving, by an offset correction circuit of the correction circuit, the first quantized outputs; and generating the offset correction information by the offset correction circuit performing the offset error operation according to the first quantized outputs, and generating a plurality of third quantized outputs by correcting the first quantized outputs using the offset correction information, wherein the gain correction circuit generates the second quantized outputs by correcting the third quantized outputs using the gain correction information.

In summary, the ADC device and the calibration circuit control method of the present disclosure analyze a plurality of first quantization outputs generated by a plurality of analog-to-digital conversion circuits through a control circuit to generate at least one control signal for controlling the calibration circuit. In the case of weak input signals (e.g., too small amplitude or too small power), the ADC device controls the calibration circuit to generate a plurality of second quantized outputs (or/and controls the calibration circuit to output a plurality of adjustment signals) according to the previously generated calibration information via at least one control signal, so as to avoid the problem that the calibration performed by the calibration circuit is affected by the weak input signals. Therefore, the problem that phase errors among a plurality of analog-digital conversion circuits are not converged correctly can be solved.

Drawings

FIG. 1A is a schematic diagram of an analog-to-digital converter according to some embodiments of the disclosure;

FIG. 1B is a schematic diagram of waveforms of the clock signals shown in FIG. 1A according to some embodiments;

FIG. 2 is a schematic diagram of a control circuit in an analog-to-digital converter according to some embodiments of the disclosure;

fig. 3 is a flowchart illustrating a control method of a correction circuit according to some embodiments of the disclosure.

[ notation ] to show

100 analog-to-digital converter device

110 analog-to-digital conversion circuit

120 correction circuit

Offset correction circuit 121

123 gain correction circuit

125 skew adjusting circuit

130 control circuit

131 absolute value circuit

133 averaging circuit

135 filter circuit

137 comparison circuit

300 correction circuit control method

331 first arithmetic circuit

333 second arithmetic circuit

CLK ₀ ～CLK _M-1 Clock signal

Control signals CSo, CSg, CSs

Q ₀ ～Q _M-1 ,CQ1 ₀ ～CQ1 _M-1 ,CQ2 ₀ ～CQ2 _M-1 Quantized output

A ₀ ～A _M-1 Absolute value signal

T ₀ ～T _M-1 Adjusting signals

SIN input signal

AVG average signal

SUM signal

Threshold value of TH

fs-sampling frequency

SP sampling period

S1, S2, S3 sampling time

S310 to S340

Detailed Description

The following embodiments are described in detail with reference to the accompanying drawings, but the embodiments are only for explaining the present invention and not for limiting the present invention, and the description of the structural operation is not for limiting the execution sequence thereof, and any structure obtained by recombining the elements and having an equivalent function is included in the scope of the present disclosure.

The term (terms) used throughout the specification and claims has the ordinary meaning as commonly understood in each art, in the disclosure herein and in the specific disclosure herein, unless otherwise indicated.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to the mutual operation or action of two or more elements.

Referring to fig. 1A and 1B, fig. 1A is a schematic diagram of an analog-to-digital converter (ADC) 100 according to some embodiments of the present disclosure. FIG. 1B illustrates a plurality of clock signals CLK shown in FIG. 1A according to some embodiments of the disclosure ₀ ～CLK _M-1 Schematic diagram of the waveform of (1). In some embodiments, the ADC device 100 operates as a time-interleaved (time-interleaved) ADC having multiple channels.

In some embodiments, the ADC device 100 includes a plurality of analog-to-digital conversion circuits 110, a correction circuit 120, and a control circuit 130. It is noted that each analog-to-digital conversion circuit 110 operates as a single channel. In other words, the ADC device 100 includes M channels. In some embodiments, M is an even number. Each analog number as shown in FIG. 1AThe word conversion circuit 110 is used for generating a plurality of clock signals CLK ₀ ～CLK _M-1 Wherein a pair of input signals SIN are analog-to-digital converted to generate a plurality of quantized outputs Q ₀ ～Q _M-1 Of the above.

As shown in FIG. 1B, a plurality of clock signals CLK ₀ ～CLK _M-1 Two adjacent clock signals have a time interval between each other, so that the adjacent 2 channels perform sampling operation and analog-to-digital conversion at different times. For example, the 1 st channel (i.e., according to the clock signal CLK) ₀ The operational ADC circuit 110) samples the input signal SIN at the 1 st sampling time S1 and performs ADC on the input signal SIN at the 2 nd channel (i.e., according to the clock signal CLK) ₁ The operational ADC circuit 110) samples the input signal SIN at the 2 nd sampling time S2 and performs ADC on the input signal SIN, and the 3 rd channel (i.e. according to the clock signal CLK) ₂ The operational adc circuit 110) samples the input signal SIN at the 3 rd sampling time S3 and performs adc. The difference between the sampling times S1 and S2 is a sampling period SP (which corresponds to a sampling frequency fs, i.e., SP = 1/fs). In this manner, the M channels may operate according to multiple staggered timings.

The calibration circuit 120 is coupled to each ADC circuit 110 for receiving a plurality of quantized outputs Q ₀ ～Q _M-1 . The calibration circuit 120 outputs Q according to the quantization ₀ ～Q _M-1 Performing at least one error operation to generate at least one correction information for correcting offset (offset) and gain (gain) errors in the analog-to-digital conversion circuits 110 and generating a plurality of corrected quantized outputs CQ2 ₀ ～CQ2 _M-1 . In addition, the correction circuit 120 may output CQ2 according to the quantized output after correction ₀ ～CQ2 _M-1 Analyzing the clock skew (corresponding to the time difference information) existing among the analog-to-digital conversion circuits 110 to generate a plurality of adjustment signals T ₀ ～T _M-1 。

As shown in fig. 1A, the correction circuit 120 includes an offset correction circuit 121, a gain correction circuit 123, and a skew adjustment circuit 125. Offset ofThe calibration circuit 121 is electrically coupled to each of the analog-to-digital conversion circuits 110 for receiving a plurality of quantized outputs Q ₀ ～Q _M-1 . In some embodiments, the offset correction circuit 121 is configured to output Q according to a plurality of quantization levels ₀ ～Q _M-1 Performing an offset error operation (i.e., the at least one error operation) to generate an offset correction information (i.e., the at least one correction information), and using the offset correction information to reduce the quantized outputs Q ₀ ～Q _M-1 To generate a plurality of quantized outputs CQ1 ₀ ～CQ1 _M-1 。

In light of the above, the gain calibration circuit 123 is electrically coupled to the offset calibration circuit 121 to receive the quantized outputs CQ1 ₀ ～CQ1 _M-1 . In some embodiments, the gain calibration circuit 123 is configured to output CQ1 according to a plurality of quantization values ₀ ～CQ1 _M-1 Performing a gain error operation (i.e., the at least one error operation) to generate a gain correction information (i.e., the at least one correction information), and using the gain correction information to reduce the plurality of quantized outputs CQ1 ₀ ～CQ1 _M-1 To produce a corrected plurality of quantized outputs CQ2 ₀ ～CQ2 _M-1 。

As mentioned above, the skew adjusting circuit 125 is electrically coupled to the gain correcting circuit 123 for receiving the corrected quantized outputs CQ2 ₀ ～CQ2 _M-1 . In some embodiments, the skew adjustment circuit 125 is used to analyze the corrected quantized output CQ2 ₀ ～CQ2 _M-1 To generate a plurality of adjusting signals T ₀ ～T _M-1 . In some embodiments, the skew adjustment circuit 125 adjusts the plurality of adjustment signals T ₀ ～T _M-1 Respectively output to a plurality of analog-to-digital conversion circuits 110, a plurality of adjustment signals T ₀ ～T _M-1 The timing adjustment module is used for indicating the timing required to adjust the plurality of analog-to-digital conversion circuits 110 due to clock skew.

In detail, the CQ2 is output due to quantization ₀ Corresponding to the 1 st sampling time S1 and the quantized output CQ21 corresponding to the 2 nd sampling time S2, the period difference between the two corresponding times is 1 sampling period SP, so that the quantized output CQ2 is analyzed ₀ And quantizes the output CQ2 ₁ Can obtain the clock signal CLK ₀ And a clock signal CLK ₁ The time difference information within 1 sampling period SP. By analogy, in this way, the skew adjusting circuit 125 can analyze the clock signal CLK ₀ ～CLK _M-1 The time difference information of each pair of adjacent clock signals in 1 sampling period SP.

The analysis clock signal CLK ₀ ～CLK _M-1 The time difference information of each pair of adjacent clock signals within 1 sampling period SP is set for illustration only, and the disclosure is not limited thereto. In some embodiments, the skew adjustment circuit 125 can respectively analyze the even-numbered clock signals CLK ₀ 、CLK ₂ 、…、CLK _M-2 Time difference information in 2 sampling periods SP and odd-numbered clock signal CLK ₁ 、CLK ₃ 、…、CLK _M-1 The time difference information within 2 sampling periods SP.

In some embodiments, the analog-to-digital conversion circuits 110 may be configured to adjust the adjustment signals T according to the adjustment signals T ₀ ～T _M-1 Adjusting the execution timing of the sampling operation and/or the analog-to-digital conversion operation to equivalently correct the clock skew. In some other embodiments, the plurality of clock signals CLK ₀ ～CLK _M-1 Can be directly based on a plurality of adjusting signals T ₀ ～T _M-1 Adjusted to equivalently correct the clock skew. For example, a plurality of adjustment signals T ₀ ～T _M-1 Is inputted to a clock signal CLK for generating a plurality of clock signals ₀ ～CLK _M-1 A clock generator, a phase interpolator, or a digital delay control line for adjusting a plurality of clock signals CLK ₀ ～CLK _M-1 The phase of (c). According to the adjusting signal T ₀ ～T _M-1 The setting manner of correcting the clock skew is only used for example, and the disclosure is not limited thereto.

As shown in fig. 1A, the control circuit 130 is electrically coupled to each of the analog-to-digital conversion circuit 110 and the calibration circuit 120 to receive a plurality of quantized outputs Q ₀ ～Q _M-1 . In some embodiments, the control circuit 130 is configured to analyze the quantized outputs Q ₀ ～Q _M-1 To generate at least one control signal (e.g., CSo, CSg, CSs shown in fig. 1A) to the calibration circuit 120. The operation of this will be described in detail with reference to fig. 2 in the following paragraphs.

Referring to fig. 2, fig. 2 is a circuit diagram of the control circuit 130 in fig. 1A according to some embodiments of the disclosure. In some embodiments, the control circuit 130 includes a plurality of absolute value circuits 131, an averaging circuit 133, a filter circuit 135, and a comparison circuit 137.

The absolute value circuits 131 are electrically coupled to the analog-to-digital conversion circuits 110 respectively to receive the quantized outputs Q respectively ₀ ～Q _M-1 . In some embodiments, each absolute value circuit 131 outputs Q according to a plurality of quantization levels ₀ ～Q _M-1 Performs an absolute value operation on a corresponding quantized output to generate a plurality of absolute value signals A ₀ ～A _M-1 One corresponding to the absolute value signal. Taking the 1 st absolute value circuit 131 as an example, the 1 st absolute value circuit 131 receives the quantized output Q ₀ And performing an absolute value operation to obtain a quantized output Q ₀ To generate an absolute value signal a ₀ . The setting and operation of the remaining absolute value circuits 131 can be analogized, and thus, the description thereof is not repeated. In some embodiments, the absolute value circuit 131 may be implemented by a processing circuit or a rectifying circuit, and various circuits for implementing the absolute value circuit 131 are all within the scope of the present disclosure.

The averaging circuit 133 is electrically coupled to the absolute value circuits 131 for receiving the absolute value signals A ₀ ～A _M-1 . In some embodiments, the averaging circuit 133 is configured to average the plurality of absolute value signals A ₀ ～A _M-1 Performing an averaging operation to average a plurality of absolute value signals A ₀ ～A _M-1 To generate an average signal AVG. In some embodiments, the averaging circuit 133 may be implemented by a digital processing circuit, but the disclosure is not limited thereto.

As shown in fig. 2, in some embodiments, the averaging circuit 133 includes a first operation circuit 331 and a second operation circuit 333. The first operational circuit 331 is electrically coupled to the plurality of absolute value circuits 131 for receiving a plurality of absolute value signals A ₀ ～A _M-1 . In some embodiments, the first operation circuit 331 is configured to operate according to a plurality of absolute value signals A ₀ ～A _M-1 Performing a summation operation to sum up a plurality of absolute value signals A ₀ ～A _M-1 To generate the SUM signal SUM. In some embodiments, the first operation circuit 331 can be implemented by an adder or other processing circuits with the same function. Various circuits for implementing the first operation circuit 331 are all within the scope of the present disclosure.

As mentioned above, the second operation circuit 333 is electrically coupled to the first operation circuit 331 for receiving the SUM signal SUM. In some embodiments, the second operation circuit 333 is configured to perform a division operation on the SUM signal SUM to generate the average signal AVG. Specifically, the second operation circuit 333 divides the SUM signal SUM by M (i.e., the number of channels) to generate the average signal AVG. In some embodiments, the second calculating circuit 333 may be implemented by a divider or other processing circuits with the same function. Various circuits for implementing the second operation circuit 333 are within the scope of the present disclosure.

The filter circuit 135 is electrically coupled to the averaging circuit 133 to receive the average signal AVG. In some embodiments, the filter circuit 135 is used for performing a filtering operation on the average signal AVG.

The comparing circuit 137 is electrically coupled to the filtering circuit 135 to receive the filtered average signal AVG. In some embodiments, the comparison circuit 137 is configured to compare the average signal AVG with at least one threshold (e.g., TH shown in fig. 2) to generate at least one control signal (e.g., CSo, CSg, CSs shown in fig. 2) to the calibration circuit 120.

Due to multiple quantized outputs Q ₀ ～Q _M-1 Is generated by converting the amplitude of the input signal SIN according to a plurality of quantized outputs Q by a plurality of analog-to-digital conversion circuits 110 ₀ ～Q _M-1 The resulting average signal AVG is related to the amplitude of the input signal SIN. In addition, the threshold TH for comparing with the average signal AVG is also related to the amplitude of the input signal SIN. Specifically, the average signal AVG may correspond to the amplitude of the current input signal SIN, and the threshold TH may correspond to a predetermined amplitude (e.g., a predetermined amplitude)The maximum amplitude of the input signal SIN of 20%). In other words, in the embodiment shown in fig. 2, the control circuit 130 is used for generating at least one control signal according to the amplitude of the input signal SIN, but the disclosure is not limited thereto. In other embodiments, the control circuit 130 may also be configured to generate at least one control signal according to the power level of the input signal SIN.

In some embodiments, the calibration circuit 120 selectively performs at least one error operation according to at least one control signal to generate at least one calibration information. In addition, the calibration circuit 120 can selectively analyze clock skew (corresponding to a plurality of clock signals CLK) existing among the plurality of analog-to-digital conversion circuits 110 according to at least one control signal ₀ ～CLK _M-1 Time difference information) to generate a plurality of adjustment signals T ₀ ～T _M-1 。

In some embodiments, the amplitude of the input signal SIN is larger (or the quantized output Q is) ₀ ～Q _M-1 A large amount of change in the values of the successive ones) such that the average signal AVG is greater than or equal to the threshold value TH. Accordingly, the control circuit 130 can generate three control signals CSo, CSg, CSs of the first voltage level (e.g., a high voltage level) to the calibration circuit 120, respectively, to simultaneously enable the offset calibration circuit 121, the gain calibration circuit 123, and the skew adjustment circuit 125. In other words, the offset correction circuit 121 performs an offset error operation according to the control signal CSo of the high voltage level to generate offset correction information, the gain correction circuit 123 performs a gain error operation according to the control signal CSg of the high voltage level to generate gain correction information, and the skew adjustment circuit 125 analyzes the plurality of clock signals CLK according to the control signal CSs of the high voltage level ₀ ～CLK _M-1 To generate a plurality of adjustment signals T ₀ ～T _M-1 。

In some embodiments, the input signal SIN has a smaller amplitude (or quantized output Q) ₀ ～Q _M-1 A small amount of change in the values of consecutive ones) such that the average signal AVG is less than the threshold value TH. Accordingly, the control circuit 130 can generate three control signals CSo, CSg, CSs of a second voltage level (e.g., a low voltage level) to the calibration circuit 120 respectively to simultaneously disableAn offset calibration circuit 121, a gain calibration circuit 123 and a skew adjustment circuit 125. In other words, the offset calibration circuit 121 does not generate the offset calibration information according to the low-voltage-level control signal CSo, the gain calibration circuit 123 does not generate the gain calibration information according to the low-voltage-level control signal CSg, and the skew adjustment circuit 125 does not analyze the clock signals CLK according to the low-voltage-level control signal CSs ₀ ～CLK _M-1 Time difference information of.

When the offset calibration circuit 121, the gain calibration circuit 123 and the skew adjustment circuit 125 are disabled, the calibration circuit 120 utilizes the calibration information generated previously to calibrate the quantized outputs Q ₀ ～Q _M-1 To generate a plurality of quantized outputs CQ2 ₀ ～CQ2 _M-1 . In addition, the calibration circuit 120 directly outputs the previously generated adjustment signal T ₀ ～T _M-1 To correct the clock skew. In some embodiments, the ADC device 110 includes a memory circuit (not shown) for storing the previously generated calibration information and the previously generated adjustment signal T ₀ ～T _M-1 。

For convenience of illustration, a plurality of clock signals CLK corresponding to the Nth cycle will be described below ₀ ～CLK _M-1 Multiple quantized outputs Q of ₀ ～Q _M-1 Multiple quantized outputs CQ1 ₀ ～CQ1 _M-1 And a plurality of quantized outputs CQ2 ₀ ～CQ2 _M-1 Multiple quantized outputs Q, each referred to as Nth cycle ₀ ～Q _M-1 Multiple quantized outputs CQ1 of Nth cycle ₀ ～CQ1 _M-1 And a plurality of quantized outputs CQ2 of Nth cycle ₀ ～CQ2 _M-1 The nomenclature for the remaining signals is repeated. In an example of practical application, the analog-to-digital conversion circuits 110 output quantized outputs Q of the Nth period ₀ ～Q _M-1 Wherein N is a positive integer. The correction circuit 120 corrects the quantized outputs Q of the Nth cycle through the offset correction circuit 121 and the gain correction circuit 123 ₀ ～Q _M-1 To generate a plurality of quantized outputs CQ2 of the Nth cycle ₀ ～CQ2 _M-1 . In addition, the correction circuit 120 adjusts the power by skewWay 125 analyzes multiple quantized outputs CQ2 for the Nth cycle ₀ ～CQ2 _M-1 To generate a plurality of adjusting signals T of Nth period ₀ ～T _M-1 。

As mentioned above, the control circuit 130 analyzes the quantized outputs Q of the Nth cycle ₀ ～Q _M-1 To generate a plurality of control signals CSo, CSg, CSs of the Nth cycle to the calibration circuit 120. Accordingly, the correction circuit 120 can selectively output Q to the N +1 th quantized outputs according to the N-th control signals CSo, CSg, and CSs ₀ ～Q _M-1 Performing at least one error operation and selectively analyzing the clock signals CLK of the (N + 1) th cycle ₀ ～CLK _M-1 Time difference information of.

For example, if the control signal CSo of the Nth cycle is at a high voltage level, the offset calibration circuit 121 of the calibration circuit 120 outputs Q according to the quantized outputs of the (N + 1) th cycle ₀ ～Q _M-1 Performing an offset error operation to generate offset correction information, and reducing the quantized outputs Q of the (N + 1) th cycle using the offset correction information ₀ ～Q _M-1 To generate a plurality of quantized outputs CQ1 of cycle N +1 ₀ ～CQ1 _M-1 . On the contrary, if the control signal CSo of the Nth cycle is at a low voltage level, the offset calibration circuit 121 does not perform the offset error operation and utilizes the offset calibration information generated previously (e.g., according to the quantized outputs Q of the Nth cycle) ₀ ～Q _M-1 Generated offset correction information) to reduce the plurality of quantized outputs Q of the N +1 th cycle ₀ ～Q _M-1 To generate a plurality of quantized outputs CQ1 of cycle N +1 ₀ ～CQ1 _M-1 。

If the control signal CSg of the Nth cycle is at a high voltage level, the gain calibration circuit 123 of the calibration circuit 120 outputs the CQ1 according to the quantized outputs of the (N + 1) th cycle ₀ ～CQ1 _M-1 Performing a gain error operation to generate gain correction information, and reducing the N +1 th period of the quantized outputs CQ1 by using the gain correction information ₀ ～CQ1 _M-1 To generate a plurality of quantized outputs CQ2 of the N +1 th cycle ₀ ～CQ2 _M-1 . Otherwise, if the control signal of the Nth periodCSg is low, the gain calibration circuit 123 does not perform the gain error operation and utilizes the previously generated gain calibration information (e.g., the quantized outputs CQ1 according to the Nth cycle) ₀ ～CQ1 _M-1 Generated gain correction information) to reduce the plurality of quantized outputs CQ1 of the N +1 th cycle ₀ ～CQ1 _M-1 To generate a plurality of quantized outputs CQ2 of the N +1 th cycle ₀ ～CQ2 _M-1 。

If the control signal CSs of the Nth cycle is at a high voltage level, the skew adjustment circuit 125 in the calibration circuit 120 analyzes the quantized outputs CQ2 of the (N + 1) th cycle ₀ ～CQ2 _M-1 To generate a plurality of adjusting signals T of the N +1 th period ₀ ～T _M-1 To a plurality of analog-to-digital conversion circuits 110. On the contrary, if the control signal CSs of the nth cycle is at the low voltage level, the skew adjustment circuit 125 does not output the quantized outputs CQ2 of the (N + 1) th cycle ₀ ～CQ2 _M-1 Analyzing and outputting a plurality of adjusting signals T generated previously ₀ ～T _M-1 (e.g., multiple quantized outputs CQ2 according to Nth cycle ₀ ～CQ2 _M-1 Generating a plurality of adjusting signals T of the Nth period ₀ ～T _M-1 ) To a plurality of analog-to-digital conversion circuits 110.

In the above embodiment, the comparison circuit 137 in the control circuit 130 generates a plurality of control signals CSo, CSg, and CSs according to the comparison result between the filtered average signal AVG and a threshold TH, so as to disable/enable the offset correction circuit 121, the gain correction circuit 123, and the skew adjustment circuit 125 in the correction circuit 120. However, the present disclosure is not limited thereto. In other embodiments, the comparison circuit 137 in the control circuit 130 may generate the control signals CSo, CSg, and CSs with different voltage levels according to the comparison result between the filtered average signal AVG and the threshold values, so as to disable/enable the offset correction circuit 121, the gain correction circuit 123, and the skew adjustment circuit 125 in the correction circuit 120, respectively.

For example, the comparing circuit 137 compares the average signal AVG with a first threshold value TH1 and a second threshold value TH2, wherein the second threshold value TH2 is greater than the first threshold value TH1. If the average signal AVG is smaller than the first threshold TH1, the control circuit 130 outputs a control signal CSo with a high voltage level and two control signals CSg and CSs with a low voltage level, so as to enable the offset calibration circuit 121 and disable the gain calibration circuit 123 and the skew adjustment circuit 125. If the average signal AVG is greater than the first threshold value TH1 but less than the second threshold value TH2, the control circuit 130 outputs two control signals CSo and CSg with high voltage levels and one control signal CSs with low voltage level, so as to enable the offset correction circuit 121 and the gain correction circuit 123, and disable the skew adjustment circuit 125. If the average signal AVG is greater than the second threshold TH2, the control circuit 130 outputs three control signals CSo, CSg, CSs with high voltage levels, so as to enable the offset correction circuit 121, the gain correction circuit 123, and the skew adjustment circuit 125. In other words, the smaller the amplitude of the input signal SIN, the larger the number of circuits that are disabled by the control circuit 130.

Referring to fig. 3, fig. 3 is a flowchart illustrating a control method 300 of a calibration circuit according to some embodiments of the disclosure. For ease of understanding, the correction circuit control method 300 will be described with reference to the foregoing figures. In some embodiments, the correction circuit control method 300 may be performed by the ADC unit 100 of fig. 1A. In one embodiment, the calibration circuit control method 300 first performs step S310 to receive the plurality of analog-to-digital conversion circuits 110 through the calibration circuit 120 according to a plurality of clock signals CLK ₀ ～CLK _M-1 The resulting plurality of quantized outputs Q ₀ ～Q _M-1 。

The correction circuit control method 300 then performs step S320 by analyzing the plurality of quantized outputs Q by the control circuit 130 ₀ ～Q _M-1 To generate at least one control signal (e.g., the aforementioned control signals CSo, CSg, CSs) to the calibration circuit 120.

The calibration circuit control method 300 then performs step S330 to selectively perform at least one error operation according to at least one control signal by the calibration circuit 120 to generate at least one calibration message and selectively analyze the plurality of clock signals CLK ₀ ～CLK _M-1 To generate a plurality of adjustment signals T ₀ ～T _M-1 。

Control of correction circuitThe method 300 then proceeds to step S340 where the plurality of quantized outputs Q are corrected by the correction circuit 120 ₀ ～Q _M-1 To generate a plurality of quantized outputs CQ2 ₀ ～CQ2 _M-1 . The descriptions and the implementation of the foregoing steps can refer to the descriptions of the foregoing embodiments, and thus the descriptions thereof are not repeated herein.

In summary, the ADC device 100 and the calibration circuit control method 300 of the present disclosure analyze the quantized outputs Q generated by the ADC circuits 110 through the control circuit 130 ₀ ～Q _M-1 To generate at least one control signal for controlling the calibration circuit 120. In the case where the input signal SIN is weak (e.g., too small amplitude or too small power), the ADC device 100 controls the correction circuit 120 via at least one control signal to generate a plurality of quantized outputs CQ2 according to the previously generated correction information ₀ ～CQ2 _M-1 (or/and control the calibration circuit 120 to output a plurality of previously generated adjustment signals T ₀ ～T _M-1 ) So as to avoid the problem that the correction performed by the correction circuit 120 is affected by the weak input signal. In this way, the problem of incorrect convergence of phase errors among the plurality of analog-to-digital conversion circuits 110 can be solved.

Although the present disclosure has been described with reference to the above embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore the scope of the disclosure should be determined by that defined in the appended claims.

Claims

1. An analog-to-digital converter apparatus, comprising:

a plurality of analog-to-digital conversion circuits for converting an input signal according to a plurality of interleaved clock signals to generate a plurality of first quantized outputs;

a correction circuit for performing at least one error operation according to the first quantized outputs to generate at least one correction information, correcting the first quantized outputs by the at least one correction information to generate second quantized outputs, and analyzing time difference information of the clock signals according to the second quantized outputs to generate adjustment signals for reducing clock skew of the analog-to-digital conversion circuits; and

a control circuit, receiving the first quantized outputs, for analyzing the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is used for controlling the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.

2. The ADC device of claim 1 wherein the control circuit analyzes the first quantized outputs of the Nth cycle to generate the at least one control signal of the Nth cycle,

the correction circuit selectively performs the at least one error operation on the first quantized outputs of the (N + 1) th cycle according to the at least one control signal of the (N) th cycle, and selectively analyzes the time difference information of the clock signals of the (N + 1) th cycle, wherein N is a positive integer.

3. The adc device of claim 2, wherein when the correction circuit performs the at least one error operation on the first quantized outputs of cycle N +1, the correction circuit corrects the first quantized outputs of cycle N +1 using the at least one correction information generated according to the first quantized outputs of cycle N +1 to generate the second quantized outputs of cycle N + 1.

4. The ADC device of claim 3, wherein when the correction circuit does not perform the at least one error operation on the first quantized outputs of cycle N +1, the correction circuit corrects the first quantized outputs of cycle N +1 by using the at least one correction information generated previously to generate the second quantized outputs of cycle N + 1.

5. The ADC apparatus of claim 2, wherein when the calibration circuit analyzes the time difference information of the clock signals of the (N + 1) th cycle, the calibration circuit analyzes the second quantized outputs of the (N + 1) th cycle to generate the adjustment signals of the (N + 1) th cycle.

6. The ADC device of claim 5, wherein the calibration circuit outputs the plurality of adjustment signals for an Nth cycle when the calibration circuit does not analyze the time difference information of the plurality of clock signals for an (N + 1) th cycle.

7. The analog-to-digital converter device of claim 1, wherein the control circuit comprises:

a plurality of absolute value circuits for receiving the first quantized outputs to output a plurality of absolute value signals, wherein each of the absolute value circuits is configured to perform an absolute value operation according to a corresponding one of the first quantized outputs to generate a corresponding one of the absolute value signals;

an averaging circuit for performing an averaging operation to average the plurality of absolute value signals to generate an average signal;

a filter circuit for filtering the average signal; and

a comparison circuit for comparing the filtered average signal with at least one threshold value to generate the at least one control signal.

8. The analog-to-digital converter device of claim 1, wherein the calibration circuit comprises:

a skew adjustment circuit for analyzing the second quantized outputs to generate the adjustment signals to the analog-to-digital conversion circuits.

9. The adc device of claim 1, wherein the at least one calibration message comprises a gain calibration message, the at least one error operation comprises a gain error operation, the calibration circuit further comprising:

a gain correction circuit for performing the gain error operation according to the first quantized outputs to generate the gain correction information, and for generating the second quantized outputs using the gain correction information.

10. The adc device of claim 9, wherein the at least one correction message further comprises an offset correction message, the at least one error operation further comprises an offset error operation, the correction circuit further comprising:

an offset correction circuit receiving the first quantized outputs, performing the offset error operation according to the first quantized outputs to generate offset correction information, and correcting the first quantized outputs using the offset correction information to generate third quantized outputs, wherein the gain correction circuit corrects the third quantized outputs using the gain correction information to generate the second quantized outputs.

11. A method for controlling a calibration circuit, comprising:

receiving a plurality of first quantized outputs generated by a plurality of analog-to-digital conversion circuits according to a plurality of staggered clock signals through a control circuit;

analyzing the first quantized outputs by the control circuit to generate at least one control signal to a correction circuit;

selectively performing at least one error operation according to the at least one control signal to generate at least one correction information and selectively analyzing a plurality of time difference information of the plurality of clock signals to generate a plurality of adjustment signals, wherein the plurality of adjustment signals are used for reducing a clock skew of the plurality of analog-to-digital conversion circuits; and

the plurality of first quantized outputs are corrected by the correction circuit to generate a plurality of second quantized outputs.

12. The calibration circuit control method of claim 11, wherein the control circuit analyzes the first quantized outputs of the Nth cycle to generate the at least one control signal of the Nth cycle,

13. The method according to claim 12, wherein when the correction circuit performs the at least one error operation on the first quantized outputs of cycle N +1, the correction circuit corrects the first quantized outputs of cycle N +1 using the at least one correction information generated based on the first quantized outputs of cycle N +1 to generate the second quantized outputs of cycle N + 1.

14. The method according to claim 13, wherein when the correction circuit does not perform the at least one error operation on the first quantized outputs of cycle N +1, the correction circuit corrects the first quantized outputs of cycle N +1 using the at least one correction information generated previously to generate the second quantized outputs of cycle N + 1.

15. The method as claimed in claim 12, wherein when the calibration circuit analyzes the time difference information of the clock signals of the (N + 1) th cycle, the calibration circuit analyzes the second quantized outputs of the (N + 1) th cycle to generate the adjustment signals of the (N + 1) th cycle.

16. The method according to claim 15, wherein the calibration circuit outputs the adjustment signals for an nth cycle when the calibration circuit does not analyze the time difference information of the clock signals for an (N + 1) th cycle.

17. The method of claim 11, wherein generating the at least one control signal comprises:

performing an absolute value operation according to a corresponding one of the first quantized outputs to generate a corresponding one of absolute value signals;

performing an averaging operation to average the plurality of absolute value signals to generate an average signal;

performing a filtering operation on the average signal; and

comparing the filtered average signal with at least one threshold value to generate the at least one control signal.

18. The method of claim 11, wherein generating the plurality of adjustment signals comprises:

and analyzing the second quantized outputs by a skew adjusting circuit of the correcting circuit to generate adjusting signals to the analog-to-digital converting circuits.

19. The method of claim 11, wherein the at least one calibration message comprises a gain calibration message, the at least one error operation comprises a gain error operation, and generating the plurality of second quantized outputs comprises:

generating the gain correction information by a gain correction circuit of the correction circuit performing the gain error operation according to the first quantized outputs, and generating the second quantized outputs using the gain correction information.

20. The method of claim 19, wherein the at least one calibration message further comprises an offset calibration message, the at least one error operation further comprises an offset error operation, and generating the plurality of second quantized outputs further comprises:

receiving, by an offset correction circuit of the correction circuit, the plurality of first quantized outputs; and

generating the offset correction information by the offset correction circuit performing the offset error operation according to the first quantized outputs, and generating third quantized outputs by correcting the first quantized outputs using the offset correction information, wherein the gain correction circuit corrects the third quantized outputs using the gain correction information to generate the second quantized outputs.