CN115149949A

CN115149949A - Analog-to-digital converter device and clock skew correction method

Info

Publication number: CN115149949A
Application number: CN202110347481.3A
Authority: CN
Inventors: 陈昱竹; 韩昕翰; 康文柱
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2022-10-04

Abstract

An analog-to-digital converter device and a clock skew correction method are provided, wherein the analog-to-digital converter device comprises a plurality of analog-to-digital conversion circuits, a correction circuit and a skew adjustment circuit. The analog-to-digital conversion circuit is used for converting an input signal according to a plurality of clock signals to generate a plurality of first quantized outputs. The correction circuit is used for correcting the first quantized output to generate a plurality of second quantized outputs. The skew adjustment circuit includes an estimation circuit and a feedback circuit. The estimation circuit is used for analyzing the second quantized output to generate a plurality of detection signals, wherein the skew adjustment circuit outputs the detection signals as a plurality of adjustment signals to reduce a clock skew of the analog-to-digital conversion circuit. The feedback circuit is used for analyzing the detection signal generated by the estimation circuit to generate a feedback signal to the estimation circuit. By analyzing the signal generated by the skew adjusting circuit to generate the feedback signal, the phase error between the analog-to-digital converting circuits can avoid generating incorrect convergence.

Description

Analog-to-digital converter device and clock skew correction method

Technical Field

The present disclosure relates to an analog-to-digital converter device and a clock skew correction method, and more particularly, to a time-interleaved analog-to-digital converter device and a clock skew correction method.

Background

Analog-to-digital converters (ADCs) are commonly used in various electronic devices to convert analog signals into digital signals for signal processing. In practical applications, the ADC may affect its own resolution or linearity due to gain error, offset error or timing error. In the prior art, the timing error is not corrected accurately enough, so that the phase errors between different channels may be converged incorrectly.

Disclosure of Invention

One aspect of the present disclosure is an analog-to-digital converter device. The analog-to-digital converter device comprises a plurality of analog-to-digital conversion circuits, a correction circuit and a skew adjusting circuit. The analog-to-digital conversion circuits are used for converting an input signal according to a plurality of clock signals to generate a plurality of first quantized outputs. The correction circuit is used for executing at least one correction operation according to the first quantized outputs to generate a plurality of second quantized outputs. The skew adjustment circuit includes an estimation circuit and a feedback circuit. The estimation circuit is configured to analyze the second quantized outputs to generate a plurality of detection signals, wherein the detection signals are associated with a plurality of time difference information of the clock signals, and the skew adjustment circuit outputs the detection signals as a plurality of adjustment signals, wherein the adjustment signals are used for reducing a clock skew of the analog-to-digital conversion circuits. The feedback circuit is used for analyzing the detection signals generated by the estimation circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit adjusts the detection signals according to the feedback signal.

In another embodiment, the estimation circuit comprises: a delay circuit for delaying a last one of the second quantized outputs to generate a delayed quantized output; a plurality of first arithmetic circuits for receiving the delayed quantized output and the second quantized outputs in sequence, and for generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs, respectively; a plurality of absolute value circuits for outputting a plurality of absolute value signals, wherein each absolute value circuit is configured to perform an absolute value operation according to a corresponding one of the difference signals to generate a corresponding one of the absolute value signals; a plurality of statistical circuits, wherein the statistical circuits are used for receiving the absolute value signals in a preset period and executing a maximum value operation or an average operation to output a plurality of calculation signals; an averaging circuit for performing an averaging operation to average the calculated signals to generate an average signal; a second operational circuit for performing an addition operation according to the average signal and the feedback signal to generate a reference signal; and a plurality of comparison circuits for comparing each calculation signal with the reference signal to generate the detection signals.

In another embodiment, the feedback circuit includes: a summing circuit for performing a summing operation to sum the detection signals to generate a summed signal; a filter circuit for generating a trigger signal according to the summation signal and at least one threshold value; and an integrating circuit for accumulating the trigger signal and outputting the accumulated trigger signal as the feedback signal.

In another embodiment, the feedback circuit further includes an amplifying circuit coupled between the filter circuit and the integrating circuit for amplifying the trigger signal.

In another embodiment, the at least one threshold comprises a positive threshold and a negative threshold, and the filter circuit compares the summed signal with the positive threshold and the negative threshold to generate the trigger signal.

Another aspect of the present disclosure is an analog-to-digital converter device. The analog-digital converter device comprises a plurality of analog-digital conversion circuits, a correction circuit and a skew adjusting circuit. The analog-to-digital conversion circuits are used for converting an input signal according to a plurality of clock signals to generate a plurality of first quantized outputs. The correction circuit is used for executing at least one correction operation according to the first quantized outputs to generate a plurality of second quantized outputs. The skew adjustment circuit includes an estimation circuit, an adjustment circuit and a feedback circuit. The evaluation circuit is configured to analyze the second quantized outputs to generate a plurality of detection signals, wherein the detection signals are associated with a plurality of time difference information of the clock signals. The adjusting circuit is used for generating a plurality of adjusting signals according to the detecting signals, wherein the adjusting signals are used for reducing a clock skew of the analog-digital conversion circuits. The feedback circuit is used for analyzing a plurality of first trigger signals generated by the adjusting circuit to generate a feedback signal to the estimating circuit, wherein the estimating circuit adjusts the detection signals according to the feedback signal.

In another embodiment, the adjusting circuit comprises: a plurality of first filter circuits for generating the first trigger signals according to the detection signals and at least one first threshold value; and a plurality of first integration circuits, wherein each of the integration circuits is configured to accumulate a corresponding one of the first trigger signals and output the accumulated corresponding one of the first trigger signals as a corresponding one of the adjustment signals.

In another embodiment, the feedback circuit comprises: a summing circuit for performing a summing operation to sum the first trigger signals to generate a summed signal; a second filter circuit for generating a second trigger signal according to the summed signal and at least one second threshold, wherein the at least one second threshold comprises a positive threshold and a negative threshold; and a second integrator circuit for accumulating the second trigger signal and outputting the accumulated second trigger signal as the feedback signal.

In another embodiment, the feedback circuit further includes an amplifying circuit coupled between the second filter circuit and the second integrating circuit for amplifying the second trigger signal.

Another aspect of the present disclosure is a method for clock skew correction. The clock skew correction method comprises: performing at least one correction operation according to the first quantized outputs generated by the analog-to-digital conversion circuits to generate second quantized outputs; analyzing the second quantized outputs by an evaluation circuit of a skew adjustment circuit to generate a plurality of detection signals, wherein the detection signals are associated with a plurality of time difference information of a plurality of clock signals received by the analog-to-digital conversion circuits, the skew adjustment circuit outputs the detection signals as a plurality of adjustment signals, and the adjustment signals are used for reducing a clock skew of the analog-to-digital conversion circuits; and analyzing the detection signals generated by the estimation circuit through a feedback circuit of the skew adjustment circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit adjusts the detection signals according to the feedback signal.

In another embodiment, generating the detection signals comprises: delaying a last one of the second quantized outputs to generate a delayed quantized output; sequentially receiving the delayed quantized output and the second quantized outputs, and respectively generating a plurality of difference signals according to two signals in the delayed quantized output and the second quantized outputs; performing an absolute value operation according to a corresponding one of the difference signals to generate a corresponding one of a plurality of absolute value signals; receiving the absolute value signals in a preset period, and executing a maximum value operation or an average operation to output a plurality of calculation signals; performing an averaging operation to average the calculated signals to generate an average signal; performing an addition operation according to the average signal and the feedback signal to generate a reference signal; and comparing each calculation signal with the reference signal to generate the detection signals.

In another embodiment, generating the feedback signal comprises: performing a summation operation to sum the detection signals to generate a summation signal; generating a trigger signal according to the sum signal and at least one threshold value; and accumulating the trigger signal and outputting the accumulated trigger signal as the feedback signal.

In another embodiment, the trigger signal is amplified after the trigger signal is generated.

In another embodiment, the at least one threshold comprises a positive threshold and a negative threshold, and generating the trigger signal comprises: the summed signal is compared to the positive threshold and the negative threshold.

Another aspect of the present disclosure is a method for clock skew correction. The clock skew correction method comprises: performing at least one correction operation according to the first quantized outputs generated by the analog-to-digital conversion circuits to generate second quantized outputs; analyzing the second quantized outputs by an evaluation circuit to generate a plurality of detection signals, wherein the detection signals are associated with a plurality of time difference information of a plurality of clock signals received by the analog-to-digital conversion circuits; generating a plurality of adjusting signals by an adjusting circuit according to the detecting signals, wherein the adjusting signals are used for reducing a clock skew of the analog-to-digital conversion circuits; and analyzing the plurality of first trigger signals generated by the adjusting circuit through a feedback circuit to generate a feedback signal to the estimating circuit, wherein the estimating circuit adjusts the detection signals according to the feedback signal.

In another embodiment, generating the adjustment signals comprises: generating the first trigger signals according to the detection signals and at least one first threshold value; and accumulating a corresponding one of the first trigger signals and outputting the accumulated corresponding one of the first trigger signals as a corresponding one of the adjustment signals.

In another embodiment, generating the feedback signal comprises: performing a summation operation to sum the first trigger signals to generate a summation signal; generating a second trigger signal according to the sum signal and at least one second threshold value, wherein the at least one second threshold value comprises a positive threshold value and a negative threshold value; and accumulating the second trigger signal and outputting the accumulated second trigger signal as the feedback signal.

In another embodiment, the second trigger signal is amplified after the second trigger signal is generated.

In summary, the adc apparatus of the present disclosure analyzes the signals generated by the skew adjustment circuit through the design of the feedback circuit to generate the feedback signal, so as to compensate the reference signal for correcting the phase error between the adc circuits. Therefore, the phase error among the analog-digital conversion circuits can avoid convergence of the upper limit value or the lower limit value of the circuit.

Drawings

FIG. 1A is a schematic diagram of an analog-to-digital converter according to some embodiments of the disclosure;

FIG. 1B is a schematic diagram of waveforms of the clock signals shown in FIG. 1A according to some embodiments;

fig. 2 is a schematic diagram of a skew adjustment circuit in an adc device according to some embodiments of the disclosure;

fig. 3 is a schematic circuit diagram of a skew adjustment circuit in an analog-to-digital converter according to some embodiments of the disclosure;

fig. 4 is a schematic diagram of a feedback circuit in an adc device according to some embodiments of the disclosure;

fig. 5 is another schematic diagram of a feedback circuit in an adc device according to some embodiments of the disclosure;

FIG. 6 is a flowchart illustrating a method for clock skew correction according to some embodiments;

fig. 7 is another schematic diagram of a skew adjustment circuit in an adc device according to some embodiments of the disclosure.

[ notation ] to show

100 analog-to-digital converter device

110 analog-to-digital conversion circuit

120 correction circuit

130 skew adjustment circuit

131 evaluation circuit

133 adjusting circuit

135 feedback circuit

140 output circuit

201 delay circuit

211 first arithmetic circuit

221 absolute value circuit

231 statistical circuit

241 averaging circuit

251 second arithmetic circuit

261 comparison circuit

215 summing circuit

213,225 Filter Circuit

223,235 integrating circuit

245 amplifier circuit

600 clock skew correction method

CLK ₀ ～CLK _M-1 Clock signal

Q ₀ ～Q _M-1 ,CQ _-1 ～CQ _M-1 Quantized output

D ₀ ～D _M-1 Difference signal

A ₀ ～A _M-1 Absolute value signal

M ₀ ～M _M-1 Computing signals

SD ₀ ～SD _M-1 Detection signal

TR1 ₀ ～TR1 _M-1 TR2 trigger signal

T ₀ ～T _M-1 Adjusting signals

SIN input signal

SOUT output signal

AVG average signal

F is a feedback signal

REF reference signal

STR1: sum signal

TH1,TH2 ⁺ ,TH2 ^- Critical value

fs sampling frequency

SP sampling period

ST: predetermined period

S610-S640 step

Detailed Description

The following embodiments are described in detail with reference to the accompanying drawings, but the embodiments are only for explaining the present invention and not for limiting the present invention, and the description of the structural operation is not for limiting the execution sequence thereof, and any structure obtained by recombining the elements and having an equivalent function is included in the scope of the present disclosure.

The term (terms) used throughout the specification and claims has the ordinary meaning as commonly understood in each art, in the disclosure herein and in the specific disclosure herein, unless otherwise indicated.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to the mutual operation or action of two or more elements.

Referring to fig. 1A and 1B, fig. 1A is a schematic diagram of an analog-to-digital converter (ADC) 100 according to some embodiments of the present disclosure. FIG. 1B illustrates a plurality of clock signals CLK shown in FIG. 1A according to some embodiments of the disclosure ₀ ～CLK _M-1 Schematic diagram of the waveform of (1). In some embodiments, the ADC device 100 operates as a time-interleaved ADC with multiple channels.

In some embodiments, the ADC device 100 includes a plurality of analog-to-digital conversion circuits 110, a correction circuit 120, a skew (skew) adjustment circuit 130, and an output circuit 140. It is noted that each analog-to-digital conversion circuit 110 operates as a single channel. In other words, the ADC device 100 includes M channels. In some embodiments, M is an even number. As shown in FIG. 1A, the analog-to-digital conversion circuits 110 are configured to convert a plurality of clock signals CLK ₀ ～CLK _M-1 Wherein a pair of input signals SIN are analog-to-digital converted to generate corresponding quantized outputs Q ₀ ～Q _M-1 。

As shown in FIG. 1B, a plurality of clock signals CLK ₀ ～CLK _M-1 Two adjacent clock signals have a time interval between them, so that the adjacent 2 channels perform sampling operation and analog-to-digital conversion at different times. For example, the 1 st channel (i.e., according to the clock signal CLK) ₀ The operational ADC circuit 110) samples the input signal SIN at the 1 st sampling time S1 and performs ADC on the input signal SIN at the 2 nd channel (i.e. according to the clock signal CLK- ₁ The analog-to-digital conversion circuit 110) operating at the 2 nd samplingThe input signal SIN is sampled at the time S2 and analog-to-digital converted, and the 3 rd channel (i.e. based on the clock signal CLK- ₂ The operational adc circuit 110) samples the input signal SIN at the 3 rd sampling time S3 and performs adc. The difference between the sampling times S1 and S2 is a sampling period SP (which corresponds to a sampling frequency fs, i.e., SP = 1/fs). By analogy, the M channels can operate according to a plurality of staggered timings.

As mentioned above, the calibration circuit 120 is coupled to each adc circuit 110 for receiving a plurality of quantized outputs Q ₀ ～Q _M-1 . The calibration circuit 120 may output Q according to quantization ₀ ～Q _M-1 Performing at least one correction operation to correct offset (offset) and gain (gain) errors in the analog-to-digital conversion circuits 110 and generate a plurality of corrected quantized outputs CQ ₀ ～CQ _M-1 。

In some embodiments, the calibration circuit 120 may be a foreground calibration circuit or a background calibration circuit. For example, the calibration circuit 120 may include a pseudo-random number generator circuit (not shown) and a digital processing circuit (not shown), wherein the pseudo-random number generator circuit generates a calibration signal (not shown) to the analog-to-digital conversion circuit 110, and the digital processing circuit outputs Q according to a plurality of quantization values ₀ ～Q _M-1 An adaptive algorithm (i.e., the aforementioned at least one correction operation) is performed to reduce the quantized output Q ₀ ～Q _M-1 Offset or error of. The calibration circuit 120 is only used for illustration, and the disclosure is not limited thereto. Various types of calibration circuits 120 are contemplated by the present disclosure.

In light of the above, the skew adjusting circuit 130 is electrically coupled to the correcting circuit 120 to receive the plurality of corrected quantized outputs CQ ₀ ～CQ _M-1 . In some embodiments, the skew adjustment circuit 130 may output the CQ according to the corrected quantization ₀ ～CQ _M-1 Analyzing the clock skew (corresponding to phase error) existing among the analog-to-digital conversion circuits 110 to generate a plurality of adjusting signals T ₀ ～T _M-1 . In some embodiments, the skew adjustment circuitThe path 130 couples a plurality of adjustment signals T ₀ ～T _M-1 Respectively output to a plurality of analog-to-digital conversion circuits 110, a plurality of adjustment signals T ₀ ～T _M-1 The timing adjustment module is used for indicating the timing required to adjust the plurality of analog-to-digital conversion circuits 110 due to clock skew.

In detail (taking M as an even number as an example), the skew adjustment circuit 130 outputs CQ according to a plurality of quantized signals ₀ ～CQ _M-1 Analyzing the clock skew (corresponding to the time difference information) existing among the analog-to-digital conversion circuits 110 to generate a plurality of adjustment signals T ₀ ～T _M-1 . Output CQ due to quantization _0- Corresponding to the 1 st sampling time S1 and quantizing the output CQ ₁ Corresponding to the 2 nd sampling time S2, the period difference between the two corresponding times is 1 sampling period SP, so that the analysis and quantization output CQ _0- And quantizing the output CQ ₁ Can obtain the clock signal CLK ₀ And a clock signal CLK ₁ The time difference information within 1 sampling period SP. By analogy, in this way, the skew adjusting circuit 130 can analyze the clock signal CLK ₀ ～CLK _M-1 The time difference information of each pair of adjacent clock signals in 1 sampling period SP.

The analysis clock signal CLK ₀ ～CLK _M-1 The time difference information of each pair of adjacent clock signals within 1 sampling period SP is set for illustration only, and the disclosure is not limited thereto. In some embodiments, the skew adjustment circuit 130 can analyze the even-numbered clock signals CLK respectively ₀ 、CLK ₂ 、…、CLK _M-2 Time difference information in 2 sampling periods SP and odd-numbered clock signal CLK ₁ 、CLK ₃ 、…、CLK _M-1 The time difference information within 2 sampling periods SP.

In some embodiments, the analog-to-digital conversion circuits 110 may be configured to adjust the adjustment signals T according to the adjustment signals T ₀ ～T _M-1 Adjusting the execution timing of the sampling operation and/or the analog-to-digital conversion operation to equivalently correct the clock skew. In some other embodiments, the clock signals CLK ₀ ～CLK _M-1 Can be directly based on a plurality of adjusting signals T ₀ ～T _M-1 Adjusted to equivalently reduce clock skew. For example, a plurality of adjustment signals T ₀ ～T _M-1 Is inputted to a clock signal CLK for generating a plurality of clock signals ₀ ～CLK _M-1 A clock generator, a phase interpolator, or a digital delay control line for adjusting a plurality of clock signals CLK ₀ ～CLK _M-1 The phase of (c). According to the adjusting signal T ₀ ～T _M-1 The arrangement for reducing the clock skew is only for example, and the disclosure is not limited thereto.

In light of the above, the output circuit 140 is electrically coupled to the calibration circuit 120 for receiving the calibrated multiple quantized outputs CQ ₀ ～CQ _M-1 . The output circuit 140 outputs CQ according to the plurality of quantized outputs after correction ₀ ～CQ _M-1 The data combining operation is performed to generate the digital signal SOUT. Through the data combination operation, a plurality of quantized output CQ provided by M channels can be output ₀ ～CQ _M-1 Are combined into a single digital signal SOUT having a sampling frequency fs, wherein the sampling frequency fs is M times the clock signal frequency. In some embodiments, the output circuit 140 may be implemented by a multiplexer circuit, but the disclosure is not limited thereto.

Referring to fig. 2, fig. 2 is a schematic diagram of a skew adjustment circuit 130 according to some embodiments of the disclosure. The skew adjustment circuit 130 includes an estimation circuit 131, an adjustment circuit 133, and a feedback circuit 135. The evaluation circuit 131 is used for performing a statistical operation to determine a corrected quantized output CQ ₀ ～CQ _M-1 Respectively corresponding multiple calculation signals (for example, M in FIG. 3) ₀ ～M _M-1 ) And averages these calculated signals to generate a reference signal (e.g., REF in fig. 3). The evaluation circuit 131 further compares the reference signal with a plurality of calculation signals to generate a plurality of detection signals SD ₀ ～SD _M-1 . The adjusting circuit 133 is used for adjusting the signal SD according to the detection signal SD ₀ ～SD _M-1 Generating the aforementioned plurality of adjusting signals T ₀ ～T _M-1 . The operation of this will be described in detail with reference to fig. 3 in the following paragraphs.

Referring to fig. 3, fig. 3 is a circuit diagram of the skew adjustment circuit 130 of fig. 2 according to some embodiments of the disclosure. The estimation circuit 131 includes a delay circuit 201, a plurality of first arithmetic circuits 211, a plurality of absolute value circuits 221, a plurality of statistical circuits 231, an averaging circuit 241, a second arithmetic circuit 251, and a comparison circuit 261.

As mentioned above, the delay circuit 201 is used to delay the quantized output CQ _M-1 To generate a delayed quantized output CQ _-1 . In some embodiments, the delay time introduced by the delay circuit 201 is equal to M times the sampling period SP in fig. 1B. The delay circuit 201 may be implemented by various digital circuits, such as buffers, inverters, filters, and so on. The above-described implementation of the delay circuit 201 is used for example, and the disclosure is not limited thereto.

The plurality of first operation circuits 211 are electrically coupled to the calibration circuit 120 in fig. 1A. The plurality of first operation circuits 211 sequentially receive the quantized output CQ _-1 ～CQ _M-1 To respectively generate a plurality of difference signals D ₀ ～D _M-1 . Taking the 1 st first operational circuit 211 as an example, the 1 st first operational circuit 211 receives the quantized output CQ _-1 And CQ ₀ And outputs the quantization CQ ₀ Subtract the quantized output CQ _-1 To generate a difference signal D ₀ . The setting and operation of the remaining first operational circuits 211 can be analogized, and thus, the description thereof is not repeated. In some embodiments, the first operation circuit 211 can be implemented by a subtractor or other processing circuits with the same function. Various circuits for implementing the first operation circuit 211 are all within the scope of the present disclosure.

The absolute value circuits 221 are electrically coupled to the first operational circuits 211 respectively to receive the difference signals D respectively ₀ ～D _M-1 . Each absolute value circuit 221 is based on a plurality of difference signals D ₀ ～D _M-1 Performs an absolute value operation on a corresponding difference signal to generate a plurality of absolute value signals A ₀ ～A _M-1 One corresponding to the other. Taking the 1 st absolute value circuit 221 as an example, the 1 st absolute value circuit 221 receives the difference signal D ₀ And performing an absolute value operation to obtain a difference signal D ₀ To generate an absolute value signal a ₀ . The setting and operation of the remaining absolute value circuits 221 may be similar, and thus are not repeated. In some embodiments, the absolute value circuit 221 may be implemented by a processing circuit or a rectifying circuit, and various circuits for implementing the absolute value circuit 221 are all within the scope of the present disclosure.

In light of the above, the plurality of statistical circuits 231 are respectively coupled to the plurality of absolute value circuits 221 to respectively receive the plurality of absolute value signals a ₀ ～A _M-1 . Each statistic circuit 231 is used for continuously receiving a plurality of absolute value signals A in a predetermined period ST ₀ ～A _M-1 And performing a statistical operation to output a plurality of calculation signals M ₀ ～M _M-1 A corresponding one of (1).

In some embodiments, the statistical operation may be a maximum operation or an average operation. Taking the 1 ST statistic circuit 231 as an example, the 1 ST statistic circuit 231 continuously receives the absolute value signal A during the predetermined period ST ₀ And performing a maximum value operation to output a maximum absolute value signal A received within a predetermined period ST ₀ For calculating the signal M ₀ . Alternatively, the 1 ST statistic circuit 231 continues to receive the absolute value signal a for a predetermined period ST ₀ And performing an averaging operation to average all absolute value signals A received during a predetermined period ST ₀ For calculating the signal M ₀ . The setting and operation of the other statistical circuits 231 can be analogized, and thus the description thereof is not repeated.

In some embodiments, the statistical circuit 231 may be implemented by a digital processing circuit, a comparator circuit and/or a register circuit, but the disclosure is not limited thereto. Various circuits for implementing the statistical circuit 231 are all within the scope of the present disclosure.

In light of the above, the averaging circuit 241 is electrically coupled to the plurality of statistical circuits 231 for receiving the plurality of calculation signals M ₀ ～M _M-1 . The averaging circuit 241 is used for calculating a plurality of signals M ₀ ～M _M-1 Performing an averaging operation to average a plurality of computation signals M ₀ ～M _M-1 To generate an average signal AVG. In some embodiments, the averaging circuit 241 may be implemented by a digital processing circuit, but the disclosure is not so limitedThe number is limited.

In summary, the second operational circuit 251 is electrically coupled to the averaging circuit 241 and the feedback circuit 135 for receiving the average signal AVG and the feedback signal F. The second operation circuit 251 receives the average signal AVG and the feedback signal F to generate the reference signal REF. For example, the second operation circuit 251 receives the average signal AVG and the feedback signal F, and adds or subtracts the average signal AVG to or from the feedback signal F to generate the reference signal REF. In some embodiments, the second operation circuit 251 can be implemented by an adder, a subtractor or other processing circuits with the same function. Various circuits for implementing the first operation circuit 251 are all within the scope of the present disclosure.

The plurality of comparison circuits 261 are coupled to the second operation circuit 251 to receive the reference signal REF. Each comparison circuit 261 is used for comparing the calculation signal M ₀ ～M _M-1 Corresponds to the reference signal REF to generate the detection signal SD ₀ ～SD _M-1 To a corresponding one of them. Taking the 1 st comparator 261 as an example, the comparator 261 compares the calculation signal M ₀ And a reference signal REF to generate a detection signal SD ₀ . The setting and operation of the remaining comparison circuits 261 can be analogized, and thus, the description thereof is not repeated. In some embodiments, the comparing circuit 261 may be implemented by a comparator. In some other embodiments, the comparing circuit 261 may be implemented by a subtractor circuit, and subtracts the corresponding calculation signal from the reference signal REF to generate the detection signal. The above-described embodiments of the comparison circuit 261 are provided for illustration, and the disclosure is not limited thereto.

In some embodiments, the detecting signals SD ₀ ～SD _M-1 Can be directly output as a plurality of adjusting signals T of FIG. 1A ₀ ～T _M-1 . In some embodiments, the plurality of difference signals D ₀ ～D _M-1 (or a plurality of detection signals SD ₀ ～SD _M-1 ) Associated with multiple channels (or multiple clock signals CLK) ₀ ～CLK _M-1 ) The time information of the middle clock skew reflects the clock skew generated by the corresponding analog-to-digital conversion circuit 110. Taking the operation of the 2 nd first operation circuit 211 as an example, as shown in FIG. 3, due to the adjustment signalT ₁ Based on quantizing the output CQ ₀ And the quantized output CQ ₁ The difference between them generating the adjusting signal T ₁ Can be used to indicate the quantized output CQ ₀ Corresponding sampling time S1 and quantized output CQ ₁ The corresponding time difference between the sampling times S2.

Calculating the signal M by comparison ₀ With reference to the reference signal REF, the clock skew with respect to the clock signal CLK can be known _-0 The resulting time difference. For example, if the signal M is calculated ₀ Greater than the reference signal REF, represents a positive effect of the time difference. Under this condition, the clock skew causes the clock signal CLK ₀ Is incorrectly advanced. Or, if the signal M is calculated ₀ Below the reference signal REF, the effect of the representative time difference is negative. Under this condition, the clock skew causes the clock signal CLK _-0 Lags behind the incorrect phase of (b). Therefore, the signal SD is detected according to different comparison results ₀ Will have different logic values to reflect the phase information of the 1 st adc circuit 110 to be adjusted due to clock skew. By analogy, the above operations can be applied to the adjustment signals T ₀ ～T _M-1 And a detection signal SD ₀ ～SD _M-1 Therefore, the description is not repeated herein.

In some other embodiments, as shown in fig. 3, the adjusting circuit 133 includes a plurality of filtering circuits 213 and a plurality of integrating circuits 223. The plurality of filter circuits 213 are respectively coupled to the plurality of comparison circuits 261 for respectively receiving the plurality of detection signals SD ₀ ～SD _M-1 。

In light of the above, the plurality of filter circuits 213 are arranged according to the plurality of detection signals SD ₀ ～SD _M-1 Generating a plurality of trigger signals TR1 with at least one threshold value TH1 ₀ ～TR1 _M-1 . The integrating circuits 223 are respectively coupled to the filtering circuits 213 for respectively receiving the triggering signals TR1 ₀ ～TR1 _M-1 . The plurality of integration circuits 223 are based on a plurality of trigger signals TR1 ₀ ～TR1 _M-1 Generating the aforementioned plurality of adjusting signals T ₀ ～T _M-1 。

In light of the above, the 1 st filter circuit 213 and the 1 st productFor the sub-circuit 223 as an example, the filter circuit 213 is electrically coupled to the 1 st operational circuit 261 for receiving the detection signal SD ₀ . In some embodiments, the filter circuit 213 can continuously accumulate the detection signal SD ₀ And comparing the accumulated detection signals SD ₀ And at least one threshold value TH1 for outputting one or more trigger signals TR1 ₀ . For example, when the accumulated detection signal SD ₀ When the accumulated detection signal is greater than at least one threshold value TH1, the filter circuit 213 will accumulate the detection signal SD ₀ Output as a corresponding trigger signal TR1 ₀ . The 1 st integration circuit 223 is coupled to the 1 st filter circuit 213 for receiving the trigger signal TR1 ₀ . The integration circuit 223 is used to accumulate the trigger signal TR1 ₀ And the accumulated trigger signal TR1 is used ₀ Output as an adjustment signal T ₀ To match different timing control methods. The arrangement and operation of the remaining filter circuit 213 and the integrating circuit 223 can be the same, and thus are not repeated.

By providing the filter circuit 213, the number of execution times of correcting the clock skew can be reduced, so as to reduce the dynamic power consumption of the ADC apparatus 100. Meanwhile, jitter (jitter) caused by correcting clock skew can be reduced by providing the filter circuit 213. By providing the integration circuit 223, the corresponding value can be adjusted according to the timing adjustment method. In practical applications, the filter circuit 213 and the integrator circuit 223 can be selectively configured according to actual requirements. In addition, the threshold TH1 can be adjusted according to actual requirements.

In various embodiments, the filter circuit 213 and the integrator circuit 223 can be implemented by at least one comparator (e.g., for comparing the trigger signal with the threshold TH1 or comparing the accumulated trigger signal), at least one register (e.g., for storing the accumulated trigger signal or the accumulated trigger signal, etc.), at least one clearing circuit (e.g., for clearing data from the register), and/or at least one operational circuit (e.g., for generating the accumulated trigger signal or accumulating the trigger signal). The above arrangement of the filter circuit 213 and the integrator circuit 223 is for example, and the disclosure is not limited thereto.

In the foregoing description, the signal M is calculated according to each ₀ ～M _M-1 As a result of comparison with the reference signal REF, the phase information of each adc circuit 110 to be adjusted due to clock skew can be obtained. However, if the reference signal REF generated by the evaluation circuit 131 is inaccurate, the previously obtained phase information of each adc 110 required to be adjusted due to clock skew may be inaccurate, so that the phase errors among the adcs 110 may be incorrectly converged after being adjusted by the skew adjustment circuit 130. Assuming that the reference signal REF is inaccurate, as shown in FIGS. 2 and 3, the present disclosure may utilize the feedback circuit 135 to analyze the signals (e.g., TR1 in FIG. 3) generated by the adjusting circuit 133 ₀ ～TR1 _M-1 ) To generate a feedback signal F to the estimation circuit 131. Accordingly, the estimation circuit 131 can adjust the inaccurate reference signal REF according to the feedback signal F, so that the reference signal REF approaches to be accurate. Therefore, the estimation circuit 131 can generate a plurality of accurate detection signals SD according to the accurate reference signal REF ₀ ～SD _M-1 (corresponding to the adjustment of the plurality of detection signals SD ₀ ～SD _M-1 ) So as to more accurately adjust the phase information of each analog-to-digital conversion circuit 110, which needs to be adjusted due to clock skew.

Referring to fig. 4, fig. 4 is a schematic diagram of the feedback circuit 135 shown in fig. 2 and 3 according to a partial embodiment of the disclosure. The feedback circuit 135 includes a summing circuit 215, a filter circuit 225, and an integrating circuit 235.

In some embodiments, the summing circuit 215 is electrically coupled to the plurality of filtering circuits 213 for receiving the plurality of trigger signals TR1 ₀ ～TR1 _M-1 . The summing circuit 215 is used for generating a plurality of trigger signals TR1 ₀ ～TR1 _M-1 Performing a summation operation to sum the trigger signals TR1 ₀ ～TR1 _M-1 To generate a summed signal STR1.

In some embodiments, the summing circuit 215 may be implemented by a digital processing circuit and/or an arithmetic circuit, but the disclosure is not limited thereto.

As mentioned above, the filter circuit 225 is electrically coupled to the summing circuit 215 to receive the summed signal STR1. In some embodiments, the filter circuit 225 may continuously accumulate the summed signalSTR1, and comparing the accumulated sum signal STR1 with at least one threshold (e.g., TH2 in FIG. 4) ⁺ 、TH2 ^- ) A comparison operation is performed to output one or more trigger signals TR2. According to different comparison operation results, the trigger signal TR2 will have different logic values (e.g., 1, 0, -1) to reflect whether the phase errors between the analog-to-digital conversion circuits 110 will converge correctly after being adjusted by the skew adjustment circuit 130.

As shown in fig. 4, in some embodiments, the filter circuit 225 sums the accumulated sum signal STR1 with a positive threshold TH2 ⁺ And a negative threshold value TH2 ^- And performing comparison operation. For example, when the accumulated sum signal STR1 is greater than the positive threshold TH2 ⁺ The filter circuit 225 outputs a corresponding trigger signal TR2 (e.g., 1) to reflect that the phase error may converge toward an upper limit of the circuit after being adjusted by the skew adjustment circuit 130. When the accumulated sum signal STR1 is less than the negative threshold TH2 ^- The filter circuit 225 outputs a corresponding trigger signal TR2 (e.g., -1) to reflect that the phase error may converge toward a lower limit of the circuit after being adjusted by the skew adjustment circuit 130. When the accumulated sum signal STR1 is between the positive threshold value TH2 ⁺ And a negative threshold value TH2 ^- In between, the filter circuit 225 will output the corresponding trigger signal TR2 (e.g., 0) to reflect that the phase error may be properly converged toward 0 after being adjusted by the skew adjustment circuit 130. In some embodiments, the implementation of the filter circuit 225 is similar to that of the filter circuit 213, and is not repeated herein.

As mentioned above, the integrating circuit 235 is electrically coupled to the filter circuit 225 for receiving the trigger signal TR2. The integrating circuit 235 is used for accumulating the trigger signal TR2 and outputting the accumulated trigger signal TR2 as the feedback signal F to be transmitted to the second operation circuit 251 in fig. 3. As mentioned above, the second operational circuit 251 can add or subtract the feedback signal F from the average signal AVG to adjust the reference signal REF. Accordingly, a plurality of comparison circuits 261 can compare each of the calculation signals M ₀ ～M _M-1 Comparing the reference signal with the adjusted reference signal REF to generate a corresponding detection signal SD ₀ ～SD _M-1 . The following operations are similar to the above description and are not repeated herein. Therefore, the phase errors between the analog-to-digital conversion circuits 110 can be prevented from generating incorrect convergence after being adjusted by the skew adjusting circuit 130. In some embodiments, the implementation of the integrating circuit 235 is similar to that of the integrating circuit 223, and is not described herein again.

Referring to fig. 5, in another embodiment, the feedback circuit 135 further includes an amplifying circuit 245. The amplifying circuit 245 is electrically coupled between the filter circuit 225 and the integrating circuit 235 for amplifying the trigger signal TR2 outputted by the filter circuit 225. The following operation is similar to the previous description, and the integrating circuit 235 receives and accumulates the amplified trigger signal TR2 to output the feedback signal F. The following operations are similar to the above description and are not repeated herein.

Referring to fig. 6, fig. 6 is a flowchart illustrating a clock skew correction method 600 according to some embodiments of the disclosure. For ease of understanding, the clock skew correction method 600 will be described with reference to the aforementioned figures. In some embodiments, the clock skew correction method 600 may be performed by the ADC device 100 of fig. 1A. In an embodiment, the clock skew correction method 600 first executes step S610, and the correction circuit 120 outputs Q according to the quantized outputs Q generated by the analog-to-digital conversion circuits 110 ₀ ～Q _M-1 Performing at least one correction operation to generate a plurality of quantized outputs CQ ₀ ～CQ _M-1 。

The clock skew correction method 600 then proceeds to step S620, where the estimation circuit 131 analyzes the plurality of quantized output CQs ₀ ～CQ _M-1 To generate a reference signal REF and a plurality of detection signals SD ₀ ～SD _M-1 。

The clock skew correction method 600 then proceeds to step S630, where the adjusting circuit 133 adjusts the clock skew according to the detected signals SD ₀ ～SD _M-1 Generating a plurality of adjustment signals T ₀ ～T _M-1 。

The clock skew correction method 600 then executes step S640 to analyze a plurality of signals (e.g., TR1 in fig. 3) generated by the adjusting circuit 133 through the feedback circuit 135 ₀ ～TR1 _M-1 ) To do so byGenerates the feedback signal F, and further causes the estimation circuit 131 to generate the reference signal REF according to the feedback signal F. The descriptions and the implementation of the foregoing steps can refer to the descriptions of the foregoing embodiments, and thus the descriptions thereof are not repeated herein.

In the embodiments of fig. 2 to 6, the feedback circuit 135 is used for analyzing the plurality of trigger signals TR1 generated by the adjusting circuit 133 ₀ ～TR1 _M-1 To generate a feedback signal F to the estimation circuit 131. However, the present disclosure is not limited thereto. Referring to fig. 7, in another embodiment, the feedback circuit 135 can be used to analyze the detection signals SD generated by the estimation circuit 131 ₀ ～SD _M-1 To generate a feedback signal F to the estimation circuit 131. That is, the summing circuit 215 is coupled to the comparing circuits 261 for receiving the detecting signals SD ₀ ～SD _M-1 . The feedback circuit 135 is based on the detection signal SD ₀ ～SD _M-1 The operation of generating the feedback signal F is similar to the foregoing description, and thus, the description is not repeated.

In summary, the ADC device 100 of the present disclosure analyzes the signals generated by the skew adjusting circuit 130 by the design of the feedback circuit 135 to generate the feedback signal F to compensate the reference signal REF for correcting the phase errors between the analog-to-digital conversion circuits 110. In this way, the phase error between the analog-to-digital conversion circuits 110 can avoid convergence to the upper limit or the lower limit of the circuit.

Although the present disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be determined by that defined in the appended claims.

Claims

1. An analog-to-digital converter device, comprising:

a plurality of analog-to-digital conversion circuits for converting an input signal according to a plurality of clock signals to generate a plurality of first quantized outputs;

a correction circuit for performing at least one correction operation according to the first quantized outputs to generate second quantized outputs; and

a skew adjustment circuit, comprising:

an evaluation circuit for analyzing the second quantized outputs to generate a plurality of detection signals, wherein the detection signals are associated with time difference information of the clock signals, and the skew adjustment circuit outputs the detection signals as adjustment signals for reducing a clock skew of the analog-to-digital conversion circuits; and

a feedback circuit for analyzing the plurality of detection signals generated by the estimation circuit to generate a feedback signal to the estimation circuit, wherein the estimation circuit adjusts the plurality of detection signals according to the feedback signal.

2. The analog-to-digital converter device of claim 1, wherein the evaluation circuit comprises:

a delay circuit for delaying a last one of the plurality of second quantized outputs to generate a delayed quantized output;

a plurality of first operational circuits for sequentially receiving the delayed quantized output and the second quantized outputs, and for generating a plurality of difference signals according to two signals of the delayed quantized output and the second quantized outputs, respectively;

a plurality of absolute value circuits for outputting a plurality of absolute value signals, wherein each of the absolute value circuits is configured to perform an absolute value operation according to a corresponding one of the plurality of difference signals to generate a corresponding one of the plurality of absolute value signals;

a plurality of statistical circuits, wherein the statistical circuits are configured to receive the absolute value signals within a predetermined period and perform a maximum operation or an average operation to output calculation signals;

an averaging circuit for performing an averaging operation to average the plurality of calculation signals to generate an average signal;

a second operational circuit for performing an addition operation according to the average signal and the feedback signal to generate a reference signal; and

and the comparison circuits are used for comparing each calculation signal with the reference signal so as to generate the detection signals.

3. The adc device of claim 1, wherein the feedback circuit comprises:

a summing circuit for performing a summing operation to sum the plurality of detection signals to generate a summed signal;

a filter circuit for generating a trigger signal according to the summation signal and at least one threshold value; and

an integrating circuit for accumulating the trigger signal and outputting the accumulated trigger signal as the feedback signal.

4. The ADC device of claim 3 wherein the feedback circuit further comprises an amplifying circuit coupled between the filter circuit and the integrating circuit for amplifying the trigger signal.

5. The ADC device of claim 3 wherein the at least one threshold comprises a positive threshold and a negative threshold, the filter circuit comparing the summed signal with the positive threshold and the negative threshold to generate the trigger signal.

6. An analog-to-digital converter device, comprising:

a skew adjustment circuit, comprising:

an evaluation circuit configured to analyze the second quantized outputs to generate a plurality of detection signals, wherein the detection signals are associated with time difference information of the clock signals;

the adjusting circuit is used for generating a plurality of adjusting signals according to the detecting signals, wherein the adjusting signals are used for reducing a clock skew of the analog-digital conversion circuits; and

the feedback circuit is used for analyzing the plurality of first trigger signals generated by the adjusting circuit to generate a feedback signal to the estimating circuit, wherein the estimating circuit adjusts the plurality of detection signals according to the feedback signal.

7. The analog-to-digital converter device of claim 6, wherein the evaluation circuit comprises:

8. The analog-to-digital converter device of claim 6, wherein the adjusting circuit comprises:

a plurality of first filter circuits for generating the plurality of first trigger signals according to the plurality of detection signals and at least one first threshold value; and

a plurality of first integration circuits, wherein each of the plurality of integration circuits is configured to accumulate a corresponding one of the plurality of first trigger signals and output the accumulated corresponding one of the plurality of first trigger signals as a corresponding one of the plurality of adjustment signals.

9. The adc device of claim 8, wherein the feedback circuit comprises:

a summing circuit for performing a summing operation to sum the first trigger signals to generate a summed signal;

a second filter circuit for generating a second trigger signal according to the summed signal and at least one second threshold, wherein the at least one second threshold comprises a positive threshold and a negative threshold; and

a second integration circuit for accumulating the second trigger signal and outputting the accumulated second trigger signal as the feedback signal.

10. The adc of claim 9, wherein the feedback circuit further comprises an amplifying circuit coupled between the second filter circuit and the second integrator circuit for amplifying the second trigger signal.

11. A method for clock skew correction, comprising:

performing at least one correction operation according to a plurality of first quantized outputs generated by a plurality of analog-to-digital conversion circuits to generate a plurality of second quantized outputs;

analyzing the second quantized outputs by an evaluation circuit of a skew adjustment circuit to generate detection signals, wherein the detection signals are associated with time difference information of clock signals received by the analog-to-digital conversion circuits, the skew adjustment circuit outputs the detection signals as adjustment signals, and the adjustment signals are used for reducing clock skew of the analog-to-digital conversion circuits; and

the detecting signals generated by the estimating circuit are analyzed by a feedback circuit of the skew adjusting circuit to generate a feedback signal to the estimating circuit, wherein the estimating circuit adjusts the detecting signals according to the feedback signal.

12. The clock skew correction method according to claim 11, wherein generating the plurality of detection signals comprises:

delaying a last one of the plurality of second quantized outputs to generate a delayed quantized output;

sequentially receiving the delayed quantized output and the plurality of second quantized outputs, and respectively generating a plurality of difference signals according to two signals of the delayed quantized output and the plurality of second quantized outputs;

performing an absolute value operation according to a corresponding difference signal of the plurality of difference signals to generate a corresponding absolute value signal of a plurality of absolute value signals;

receiving the absolute value signals in a preset period, and executing a maximum value operation or an average operation to output a plurality of calculation signals;

performing an averaging operation to average the plurality of calculated signals to generate an average signal;

performing an addition operation according to the average signal and the feedback signal to generate a reference signal; and

comparing each of the calculated signals with the reference signal to generate the plurality of detection signals.

13. The method of claim 11, wherein generating the feedback signal comprises:

performing a summation operation to sum the detection signals to generate a summation signal;

generating a trigger signal according to the sum signal and at least one threshold value; and

the trigger signal is accumulated, and the accumulated trigger signal is output as the feedback signal.

14. The method according to claim 13, wherein the trigger signal is amplified after the trigger signal is generated.

15. The method according to claim 13, wherein the at least one threshold comprises a positive threshold and a negative threshold, and generating the trigger signal comprises:

the summed signal is compared to the positive threshold and the negative threshold.

16. A method for clock skew correction, comprising:

analyzing the second quantized outputs by an evaluation circuit to generate a plurality of detection signals, wherein the detection signals are associated with time difference information of clock signals received by the analog-to-digital conversion circuits;

generating a plurality of adjusting signals according to the plurality of detecting signals through an adjusting circuit, wherein the plurality of adjusting signals are used for reducing a clock skew of the plurality of analog-to-digital conversion circuits; and

a feedback circuit analyzes the first trigger signals generated by the adjusting circuit to generate a feedback signal to the estimating circuit, wherein the estimating circuit adjusts the detecting signals according to the feedback signal.

17. The clock skew correction method according to claim 16, wherein generating the plurality of detection signals comprises:

sequentially receiving the delayed quantized output and the plurality of second quantized outputs, and generating a plurality of difference signals according to two signals of the delayed quantized output and the plurality of second quantized outputs respectively;

18. The method according to claim 16, wherein generating the plurality of adjustment signals comprises:

generating a plurality of first trigger signals according to the plurality of detection signals and at least one first threshold value; and

and accumulating a corresponding first trigger signal in the plurality of first trigger signals, and outputting the accumulated corresponding first trigger signal as a corresponding adjusting signal in the plurality of adjusting signals.

19. The method of claim 18, wherein generating the feedback signal comprises:

performing a summation operation to sum the first trigger signals to generate a summation signal;

generating a second trigger signal according to the sum signal and at least one second threshold value, wherein the at least one second threshold value comprises a positive threshold value and a negative threshold value; and

the second trigger signal is accumulated, and the accumulated second trigger signal is output as the feedback signal.

20. The method of claim 19, wherein the second trigger signal is amplified after the second trigger signal is generated.