TWI493467B - Interrupt signal processing method and computer system - Google Patents

Description

Interrupt signal processing method and computer system

The invention relates to an interrupt signal processing method and a computer system, in particular to a method and a computer system for processing SW-SMI signal by using the effective bit length corresponding to the software system management interrupt signal value.

Please refer to the first figure, which is a schematic diagram of a common computer system function, which mainly includes a central processing unit (CPU) 101, a north bridge wafer 103, a south bridge wafer 105, a display wafer 117, a memory controller 111, a memory unit 109, The peripheral device 113 and a basic input/output system (hereinafter referred to as BIOS) 107. The function blocks of the system operation are as follows: the central processing unit 101 is a unit for managing and computing the computer system; the north bridge chip 103 and the south bridge chip 105 are external communication bridges of the central processing unit 101, wherein the north bridge chip 103 is responsible for connecting the memory. The body controller 111 and the high-speed components such as the display wafer 117, and the south bridge wafer 105 is responsible for connecting the slower peripheral devices 113 such as a hard disk, a USB, a network chip, etc.; and the basic output input system 107 is a set of records in a non-volatile state. A program in memory that remembers the computer-related hardware-related settings to allow the computer to properly manage and operate the system.

In a computer system, a system management interrupt (SMI) can be classified into a hardware system management interrupt (HW-SMI) or a software system management interrupt due to different triggering reasons. (Software System Management Interrupt, hereinafter referred to as SW-SMI). Regardless of the cause of the trigger, the computer system initiates the system management interrupt procedure to be substantially the same, that is, a system management interrupt signal is transmitted to the central processing unit 101 via the system management interrupt pin SMI# on the south bridge wafer 105. Then, the central processing unit 101 is triggered to enter a system management mode (hereinafter referred to as SMM), which is the highest privilege mode of the central processing unit 101. After entering this mode, the task originally executed by the computer system will be interrupted. Then, the central processing unit 101 reads the special area located in the memory unit 109 through the memory controller 111, that is, the program in the system configuration random access memory (SMRAM) area. To determine which interrupt handler should be executed. In particular, the program in the SMRAM is referred to as an SMI processing program which is previously loaded into the memory unit 109 by the basic output input system 107 at the beginning of the startup of the computer system.

Further, the SMI generated by the software program writing to a specific hardware is called a software system management interrupt, and the specific hardware is in the Advanced Configuration and Power Interface (Advanced Configuration and Power Interface, ACPI) is called the SMI command (Command Port), and its instruction length is 1 byte.

In general, if the software program requires the BIOS to perform some control on a certain hardware, it will inform the BIOS of what it wants by issuing a specific SW-SMI command. For example, according to the definition in ACPI, the BIOS will provide an ACPI enable command to the operating system (OS). When the OS wants to enter the ACPI mode, it will write the ACPI enable command to the SMI command. If the ACPI enable command is 068h, the OS will fill 068h into the SMI command. On the other hand, regardless of the value written to the SMI command, the write behavior will trigger the system management interrupt pin SMI# transfer system management interrupt signal on the south bridge wafer 105 to the central processing unit 101, and the central processing unit 101 Enter system management mode. In the system management mode, the central processing unit 101 reads the SMI processing program in the memory unit 109 that is planned to be in the system configuration dynamic access memory area through the memory controller 111. For example, if the SMI command 写入 written in the south bridge chip 105 is 068h, the value 068h is used to compare with the program in the system configuration dynamic access memory area to determine the corresponding processing for issuing the software system management interrupt event. The address of the program, and the program counter is moved to the start address, and then the control flow in the interrupt handler is executed.

In short, the processing of one SW-SMI involves the communication between the south bridge chip 105, the basic output input system 107, the memory controller 111 and the central processing unit 101, and the program related to this control flow is placed in the memory. The system in unit 109 configures the dynamic access memory area. The program in the area is loaded by the basic output input system when the computer system is powered on, and for SW-SMI instructions, the program must be clearly defined once When the BIOS loads the memory unit, the program content should not be changed arbitrarily.

As can be seen from the above description, when judging the flow of the SW-SMI event, the computer system must rely heavily on the SMI processing program provided by the basic output input system 107 to process the SW-SMI command issued by the software. In the practice of the prior art, the BIOS manufacturer is responsible for managing the correspondence between the SW-SMI processing program and the SW-SMI instruction. For each SW-SMI, a unique instruction is assigned, and each SW-SMI instruction is one byte long. Since SW-SMI commands and SW-SMI handlers are managed by BIOS vendors, system vendors or chipset vendors must first confirm the BIOS if they want to add other SW-SMI handlers to handle other events. Which SW-SMI instructions have not been used yet, and then select one of these unused SW-SMI instructions to add the new SW-SMI handler. Such a development model leads to the problem that the system or chipset manufacturer cooperates with more than one basic output input system manufacturer, and different basic output input system vendors allocate SW-SMI instructions and SMI processing for the same event processing. The starting address of the program is also different; on the other hand, the event processing of the same basic output input system manufacturer is not necessarily the same for the same SW-SMI instruction. Therefore, in the current situation, in the system of the same basic output input system manufacturer, the same SW-SMI command value may be used due to poor management, thereby causing conflicts in system execution. Moreover, different basic output input system vendors may also be plagued by the fact that the overall planning of the SW-SMI command values is different.

In addition, because in the definition of advanced configuration and power interface specifications, the length of the SW-SMI instruction is fixed to the length of one tuple (ie, the length of 8 bits), which represents the SW that the SMI handler can recognize. - The total number of SMI commands is at most one number that can be supported by one byte, that is, 2^8=256 interrupt instructions. According to the definition of this specification, the maximum number of SW-SMI handlers that can be supported on a computer system is 256. This also makes the expansion of the SW-SMI processing program supported by the computer system limited by the authorities.

According to the above description, the conventional technology uses the SW-SMI command to determine that the SW-SMI processing program is missing: different basic output input system manufacturers may have different definitions for each SW-SMI instruction, and once the SW-SMI processing program is added, Need to find available instructions in the program structure of the basic output input system, and the SW-SMI processing program that the computer system is equipped with is increasing. Only the support of 256 different SW-SMI processing programs will not be used, so There is an urgent need to address the aforementioned shortcomings.

One aspect of the present invention is a software system management interrupt signal processing method, which is applied to a computer system capable of executing a software, the method comprising the following steps: corresponding to a software write to a first register of a core logic circuit A software system manages a set of values of an interrupt instruction, the core logic circuit sends a system management interrupt signal to a central processing unit; the central processing unit executes a system management interrupt processing program; the system management interrupt processing program determines the set of values The effective bit length; and the system management interrupt processing program executes a software system management interrupt processing program corresponding to a memory unit according to the effective bit length and the set of values in the first temporary register.

Another aspect of the present invention is a computer system applied to a software system management interrupt, the computer system comprising: a core logic circuit having a first register, and writing a set of values to the first register The core logic circuit sends a system management interrupt signal; a memory unit electrically connected to the core logic circuit, which records a plurality of software system management interrupt processing programs; and a central processing unit electrically connected to the memory unit and The core logic circuit receives the system management interrupt signal and executes a software system management interrupt processing program corresponding to the content execution according to the effective length of the set of values.

In computer systems, the conventional technique uses a SW-SMI instruction with a fixed length of the length of the byte to determine the SW-SMI processing program. It has a limited number of SW-SMI instructions and is prone to definition conflicts, and relies too much on the basic output. The input system vendors are missing, and this case is used as a starting point. I hope to find a solution to the conflict between SW-SMI instructions and the flexibility of the system and chipset manufacturers to reduce the excessive dependence on the basic output input system manufacturers during the development process. Interrupt instruction configuration settings.

As mentioned above, the purpose of this case is to develop a processing method for SW-SMI signal discrimination, and apply it to the software system management interrupt of the computer system. The computer system here comprises: a memory unit, a core logic circuit and a central processing unit, which are electrically connected with each other by a bus bar or the like, and the core logic circuit has an interrupt instruction register (ie, a conventional technology) SMI command 埠, hereinafter referred to as SMI register).

The core method of this case is as follows: When the software writes a set of values corresponding to a SW-SMI instruction to the SMI instruction register in the core logic circuit, the core logic circuit sends an SMI signal to the central processing unit. Next, the central processing unit begins executing the SMI processing program. The SMI handler is then caused to determine the effective bit length of the set of values corresponding to the set of SMI instructions stored in the instruction register. Thereafter, the SMI processing program is executed to execute the software system management interrupt processing program corresponding to the memory unit based on the effective bit length and the value in the SMI instruction register.

Based on the architecture of the prior art, the above core logic circuit can be a general south bridge chip or another dedicated logic circuit specially used to assist in judging system management interrupts; and SMI can be used between the core logic circuit and the central processing unit. The #pin method directly transfers the interrupt signal, or is indirectly transmitted from the core logic circuit to the central processing unit through the bus; and the step of writing the value corresponding to the SW-SMI command to the SMI instruction register According to the planning of the computer system, the software executed by the central processing unit writes the value of the SW-SMI command into the SMI instruction register through the system bus. Further, the SMI processing program can be used by the basic output input system. Provided, the application can be used by the system bus bar to write each SW-SMI processing program in the system to the memory unit and indirectly to the central processing unit for execution.

In this case, the information of the actual effective bit length corresponding to the value of the SW-SMI instruction is used, and when the SMI processing program determines the SW-SMI processing program to be executed, the effective bit length of the SW-SMI instruction is provided to the SMI processing program, and The manner of providing valid bit length information may be that the SMI instruction register (ie, the first register) that records the bit length information representing the length of the effective bit and the SW-SMI value content is combined in the core logic circuit. ), or separately recorded in a scratchpad dedicated to the storage length (ie, the second scratchpad), and then the SMI processing program to the core logic circuit to read the first scratchpad or the second scratchpad Record information about the length; or use other logic circuits or system busses (such as PCI system bus) to be directly or indirectly provided to the SMI handler using the SW-SMI command during the control of the system management interrupt handler Bit length information.

In the preferred embodiment of the present invention, in addition to the byte-length SW-SMI instruction used in the conventional art, a SW-SMI instruction using a word (Word) and a double word (Double Word) length is additionally provided. In order to provide the identification of the newly added software system management interrupt, the SMI processing program can read from the same clock to the core control logic through the central processing unit through the assistance of the other logic circuits or system bus. Record the value of the value in the SMI instruction register.

The correspondence between the SW-SMI command and the SW-SMI handler can be quite flexible, for example, for a completely different SW-SMI command content, or a new SW-SMI handler associated with a SW-SMI handler. Sex, you can define the common related information content in the SW-SMI instruction content by the first byte near the Most Significant Bit (MSB), and close to the Least Significant Bit (LSB). The bytes can define different information content. Since the system bus and the like provide information corresponding to the effective bit length of the SW-SMI command, the SMI handler can use this information to avoid malfunctions when reading data, that is, when writing a one-tuple data, SMI The other bits on the instruction register may also have a value because the length of the previous SW-SMI instruction is a word length or a double word length, etc., and the length alignment mechanism can know the part. The value is independent of this SW-SMI instruction.

Adding a way to judge the effective bit length in the program, in addition to improving the aforementioned shortcomings, is also quite simple to implement on existing computer systems. That is, it is only necessary to first determine the value of the SW-SMI instruction corresponding to the interrupt program with different effective bit lengths in the flow, and arrange the SW-SMI processing program corresponding to the values in the existing SMI interrupt processing. Before the program block, when the software enters the system management mode, the program that is judged by the entry point (that is, the starting point of the system configuration dynamic access memory) enters the SMI processing corresponding to the new SW-SMI command group. Program.

The subsequent preferred embodiment is described by the SW-SMI instruction as the effective bit length of the block (ie, 16 bits), but the actual application is not limited to the length of the block as the effective bit length of the SW-SMI instruction. An example of a decision, that is, other possible lengths such as a double word, quad block, or other non-byte length of the SW-SMI instruction may also be employed.

Since the system management interrupt has only one entry point, all system management interrupt events will be processed in the same processing program. When the system management interrupt is generated, the south bridge chip will set the state of the system management interrupt event, so the system management interrupt handler must judge Which system management interrupt event is handled, so the application starting point of the present invention corresponds to the "entry SMM" mentioned by the prior art, and the end point corresponds to the "control flow in the execution interrupt processing program" proposed by the prior art.

Please refer to the second figure, which is a schematic diagram of the flow of a preferred embodiment of the personal computer system developed in order to improve the lack of conventional means. First, the central processing unit enters the system management mode by the SMI# signal (step 401), and then the SMI processing program determines whether the effective bit length of the SW-SMI command provided by the core logic circuit is the byte length (step 403), and if so, The processing program indicating the software system management interrupt follows the interrupt signal generally judged by the basic output input system, so the flow enters the general judgment interrupt processing flow (step 405); if not, the process proceeds to a table lookup comparison process. The processing of the SW-SMI processing program represented by the value of the length of the effective bit is greater than the length of the block (step 407), and the details of the table lookup may be different, but the method is not only in the table comparison. In the process, the individually defined SMI instruction is compared with the received data, and once it matches, the system management mode is executed to execute the corresponding processing program; after the corresponding interrupt processing program is executed (step 405, step 407), the central The processing unit will return to the original normal processing flow. For further explanation of the table lookup comparison (step 407), please refer to the third and fourth figures.

Please refer to the third figure (a) (b), which is the memory configuration diagram and control flow chart in the system configuration dynamic access memory corresponding to the first implementation of the table lookup comparison process. The SMI interrupt processing program in the third diagram (a) includes: SW-SMI processing program α, SW-SMI processing program β, SW-SMI processing program γ, etc., and a memory space I, II, III is respectively configured. The contents of the individual software system management interrupt handler are stored, and in the flowchart of the third diagram (b), it can be seen that the central processing unit first reads the SW-SMI command after entering the software system management interrupt (step 501). The value (step 503) compares the SW-SMI command value with the value read from the SMI command register (step 505), if the value of the SW-SMI command in the memory unit conforms to the self-bridge chip The value stored in the SMI instruction register starts executing the SW-SMI processing program corresponding to the SW-SMI instruction (step 507), and exits the interrupt processing flow after executing the contents of the SW-SMI processing program ( Step 511); if the central processing unit compares the value of the SW-SMI instruction with the result of the value in the SMI instruction register, the program counter is moved to the start address of the next SW-SMI processing program (step 509), then repeat the aforementioned reading SW-SMI instruction (step Step 503) and the action of the judgment (step 505).

For example, after the system management interrupt is triggered, it firstly jumps to the starting point of the SW-SMI processing program α and reads the contents of the SW-SMI instruction α, and compares the SW-SMI instruction α with the self-SMI instruction register. Whether the read values x are equal, if not equal, the program will continue to jump to the starting point of the SW-SMI processing program β, that is, the content of the SMI command β is read where the SW-SMI command β is stored. In this way, it is assumed that in the third figure (b), the content of x is the same as the content of the SW-SMI instruction γ, the SMI control flow will enter the SW-SMI processing program γ, and the execution of the SW-SMI processing program γ will be started. The steps inside.

Referring to FIG. 4(a)(b), it is a second system configuration dynamic access memory configuration diagram and control flow chart corresponding to the table lookup comparison process that may be used to implement the interrupt processing program. In this method, an individual SW-SMI processing program is recorded in the first recording block in the memory unit and the corresponding starting address is obtained, and then the SW-SMI processing program corresponds to the SW- The value of the SMI instruction is written in the second record block in the memory unit together with the start address, thereby providing a function of obtaining the position of the SW-SMI handler according to the figure when the comparison result is met.

As shown in the fourth figure (a), this type of lookup table is to plan a dedicated lookup table at the starting point of the system configuration dynamic access memory, that is, the second record block, and the interrupt control flow is After entering the system management mode (step 601), the operation of querying the SW-SMI command is performed through the dedicated look-up table area (step 603), and the value obtained by the SMI instruction register in the core logic circuit is triggered (ie, the SMI state is triggered). The SW-SMI value is compared with each SW-SMI command in the dedicated lookup table (step 605). If the comparison is unsuccessful, the value of the next SW-SMI command in the lookup table is continuously obtained ( Step 607), and then restart the comparison (step 605), once the value of the SW-SMI instruction matches the result of the value in the SMI instruction register, the reading is continued after the SW-SMI instruction is recorded. The start address of each interrupt flow (step 609), and then the SMI handler will move the program counter to the start address of the obtained SW-SMI processing program (step 611) and start executing the record in the first record block. SW-SMI processing program (step 613), for example, from the SW-SMI processing program β Point in step executes interrupt processing program SW-SMI β, and away from the SMM is performed (step 615) After completion of the step SW-SMI processing program of beta].

Please refer to the fifth figure, which is a schematic diagram of a program configuration processed by a basic output input system manufacturer in actual application according to a preferred embodiment of the present invention. The figure shows the program configuration in the system configuration dynamic access memory block where the basic output input system writes to the memory unit when the program is booted, which can be further distinguished in the system configuration dynamic access memory block. The first program block and the second program block, wherein the area formed by the SW-SMI processing program A, the SW-SMI processing program B, the SW-SMI processing program C, and the like, that is, the first program block, is The block used by the SMI program in the existing computer system is used to store the interrupt processing program group corresponding to the SW-SMI instruction having the byte length; the other block, that is, the second program block, is used. The second type interrupt processing program such as the SW-SMI processing program α, the SW-SMI processing program β, the SW-SMI processing program γ, etc., which store the SW-SMI command, is a non-byte group length.

Therefore, when the preferred embodiment of the present invention performs the SW-SMI instruction disassembly determination, once in the step of interpreting the valid bit (step 403 of FIG. 2), the valid bit corresponding to the SW-SMI instruction is known. The length information conforms to the length defined internally by the advanced configuration and the power interface specification (one tuple length), and then enters the original entry point and begins the correspondence and processing of the general interrupt process (step 405); The effective bit length information of the SW-SMI instruction shows that the effective bit length is different effective bit lengths defined according to the present invention, such as a block length, a double block length, and a quad block length, etc., and the interrupt processing is performed. The process will enter the segment indicated by the new entry point, and the start point will determine which of the interrupt handlers is the interrupt source corresponding to the trigger event (step 407).

In short, the method of the present invention only needs to change the judgment process of the program, and the basic output input system can be easily integrated into the existing computer system development process by adding a part of the interrupt processing program before the original judgment starting point. The basic output input system manufacturer is still responsible for the interrupt processing program in the original memory block. The newly added SW-SMI processing program coordinated by the chipset manufacturer and the system manufacturer and placed in the new memory block will be greatly reduced. The inconvenience of close communication between the three parties is required in the existing development process. Because the planning of the new interrupt handler block is independent of the interrupt handler block used by the basic output input system, a different development process can be used, so it can be used with any basic output input system manufacturer to make the computer system The development time schedule is more time-sensitive, and it is not necessary to rewrite the corresponding interrupt judgment process because the plans of different basic output input system manufacturers are different from each other.

In summary, this case adds the judgment of SW-SMI instruction length in the judgment process of software system management interruption. In addition to solving the problem that the conventional technology relies on too many basic output input systems, this method has the following advantages. : The practice of this case is compatible with the current technology, and will not cause additional cost; solve the conflict problem in the basic output input system and application, driver, and graphics chip when using the software system to manage the interrupt event; trigger the software system management interrupt At the same time, more information can be transferred at the same time; it is compatible with the cores of different basic output input system vendors; and only one clock cycle is required to complete this method.

While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the invention may be modified by those skilled in the art, and the invention is not intended to be protector.

The components included in the drawings of the present invention are as follows:

100. . . Interrupt control register

101. . . Central processing unit

103. . . North Bridge Chip

105. . . South Bridge Chip

107. . . Basic input and output unit

109. . . Memory unit

111. . . Memory controller

113. . . Peripheral device

117. . . Display chip

The case can be further understood by the following diagrams and explanations:

The first picture is a block diagram of the common computer system function.

The second figure is a schematic flow chart of a preferred embodiment of the software system management interrupt signal processing developed in order to improve the lack of conventional means.

The third figure (a) (b) is the memory configuration diagram and control flow chart in the system configuration dynamic access memory corresponding to the first implementation of the table lookup comparison process.

The fourth figure (a) and (b) are the memory configuration diagram and control flow chart in the system configuration dynamic access memory corresponding to the second implementation of the table lookup comparison process.

The fifth figure is a schematic diagram of a program configuration that is processed by a basic output input system manufacturer in the actual application of the present invention.

Claims (22)

A software system management interrupt signal processing method is applied to a computer system capable of executing a software, the method comprising the steps of: writing a corresponding software system management interrupt instruction to a first temporary register of a core logic circuit; a set of values, the core logic circuit sends a system management interrupt signal to a central processing unit; the central processing unit executes a system management interrupt processing program; and the system management interrupt processing program determines the effective bit length of the set of values, If the effective bit length is greater than one tuple length, entering a table lookup comparison process; wherein the lookup table comparison process is the system management interrupt processing program according to the effective bit length and the first temporary storage The set of values in the device executes a corresponding software system management interrupt processing program in the memory unit to process the software system management interrupt processing program represented by the value whose effective bit length is longer than one word. . The software system management interrupt signal processing method according to claim 1, wherein the interrupt signal is transmitted by a pin between the core logic circuit and the central processing unit. The software system management interrupt signal processing method according to claim 1, wherein the software writes the set of values to the first temporary register in the core logic circuit to control the central processing unit by the software. The set of values is written to the register via a system bus. The software system management interrupt signal processing method according to claim 1, wherein the interrupt processing program is provided by a basic output input system of the computer system, and the interrupt is in the basic output input system. The program program writes the memory unit through a system bus. The software system management interrupt signal processing method according to claim 1, wherein the effective bit length is one-bit tuple length, one-word group length, one double-word group length or one quad-word group length. The software system management interrupt signal processing method according to claim 1, wherein the method further comprises the step of: recording, in the core logic circuit, bit length information representing one of the effective bit lengths. The software system management interrupt signal processing method according to claim 6, wherein the bit length information is recorded in one of the core logic circuits and the second register. The software system management interrupt signal processing method according to claim 6, wherein the step of determining the effective bit length of the set of values is performed by the system management interrupt processing program from the core logic circuit. Information comes. The software system management interrupt signal processing method according to claim 1, wherein the first temporary register is a system management interrupt instruction register. The software system management interrupt signal processing method according to claim 1, wherein the method further comprises the following steps: a plurality of software system management interrupt processing programs corresponding to the plurality of values according to the effective bit length of the plurality of values Dividing into a first type of software system management interrupt processing program and a second type software system management interrupt processing program; and writing the plurality of interrupt processing programs into the memory unit Specific block. The software system management interrupt signal processing method according to claim 10, wherein the step of writing the plurality of interrupt processing programs to a specific block in the memory unit is to manage the first type software system. The interrupt handler and the second type of software system management interrupt handler are respectively written in one of the first program block and the second program block in the specific block. The software system management interrupt signal processing method according to claim 10, wherein the step of recording the plurality of software system management interrupt processing programs in the specific block is performed by a basic output input system of the computer system through a system bus This is done by writing to the memory unit. The software system management interrupt signal processing method according to claim 1, wherein the method further comprises the following steps: a plurality of software system management interrupt processing programs corresponding to the plurality of values and including the software system management interrupt processing program Write to this memory unit. The software system management interrupt signal processing method according to claim 13, wherein the system management interrupt processing program executes the corresponding software system management in the memory unit according to the set of values in the first temporary register. The method for interrupting the processing program includes the steps of: comparing the software system management interrupt instruction written in the first temporary register with the plurality of values written in the memory unit; and when the comparison is met The program counter points to the start address of the software system management interrupt handler corresponding to the set of values. Software system management interrupt signal as described in claim 13 The processing method, wherein the step of writing a plurality of software system management interrupt processing programs corresponding to the plurality of values into the memory unit is to write one of the plurality of values into the memory unit, and then write The software system management interrupt processing program corresponding to the first value; and writing the second value of the plurality of values to the memory unit, and then writing the software system management interrupt processing program corresponding to the second value. The software system management interrupt signal processing method according to claim 13, wherein the step of writing a plurality of software system management interrupt processing programs corresponding to the plurality of values into the memory unit is to manage the plurality of software systems. The interrupt processing program records one of the first record blocks in the memory unit, and writes the plurality of values to the memory unit in the memory unit corresponding to the start address corresponding to the plurality of software system management interrupt processing programs. A second record block. A computer system for applying a software system management interrupt, the computer system comprising: a core logic circuit having a first register, writing a set of values to the first register to enable the core logic circuit to issue a system Management interrupt signal; a memory unit electrically connected to the core logic circuit, which records a plurality of software system management interrupt processing programs; a central processing unit electrically connected to the memory unit and the core logic circuit, the system receives The system manages the interrupt signal, and the software system management interrupt processing program corresponding to the content execution according to the effective bit length of the set of values; a system bus bar electrically connected to the core logic circuit, the memory And the central processing unit writes the set of values to the first register; and a basic output input system electrically connected to the system bus, which provides the plurality of software system management interrupt processing programs, And recorded in the memory unit through the system bus. The computer system of claim 17, wherein the core logic circuit further comprises a second register, which records information on the length of one bit representing the length of the effective bit. The computer system of claim 17, wherein the core logic circuit and the central processing unit have a pin, which transmits the system management interrupt signal. The computer system of claim 17, wherein the plurality of software system management interrupt instruction values have a valid bit length of one tuple length, one block length, one double word length, or one fourth. The length of the block. The computer system of claim 17, wherein the plurality of software system management interrupt processing programs are recorded in a specific block of the memory unit, and the specific block is based on the plurality of software systems The effective bit length of the plurality of values corresponding to the management interrupt processing program is divided into a first program block and a second program block. The computer system of claim 17, wherein one of the first recording blocks of the memory unit records the plurality of software system management interrupt processing programs, and a second recording block records the plurality of The value is the starting address corresponding to the plurality of software system management interrupt handlers.