JP2001142712A - Start-up controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a start-up controller which improves the operation speed of the whole system by improving the transfer operation of a BIOS at CPU start-up time. SOLUTION: A CPU start-up control part 107 makes a transfer start signal 213 active when a start-up signal 116 becomes active. An SDRAM control part 108 and a PAGEROM control part 109 performs BIOS transfer from a PAGEROM to an SDRAM once the transfer start signal is made active. After this transfer of the BIOS, a transfer end status 214 is made active. Once the transfer end status is made active, the CPU start-up control part 107 makes a CPUREST 111 active for a specific time. A CPU is started up at this time for the 1st time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an activation control device for controlling activation of a computer system.

[0002]

2. Description of the Related Art Generally, in a system using a microcomputer, an instruction code in which basic processing contents such as receiving a character string input from a keyboard or displaying a specific character on a display are programmed, and a system including the instruction code The contents of the processing to be executed at the time of activation are compiled into instruction codes, which are stored in a ROM as a basic input / output system (BIOS). When the CPU is started, the system is started by reading and executing the BIOS program from the ROM. Alternatively, the BIOS program may be called as a subroutine after the system is started for the purpose of facilitating program creation.

[0003] Since the BIOS collects instruction codes necessary for performing basic operations in operating the system, the BIOS is frequently called when the CPU executes an application. For this reason, the BIOS is changed to RO
The speed of reading from M greatly affects the operation speed of the entire system.

Therefore, a program or the like frequently read from the CPU, such as the BIOS, can be read from a memory such as a ROM in which the program is read more quickly by an R which can be accessed at a higher speed.
In some cases, the data is transferred to another memory such as an AM at the time of startup. As a result, the CPU only needs to access a RAM or the like that is faster than a ROM or the like, so that the operation speed of the entire system is improved.

[0005] For example, JP-A-59-71558 and JP-A-61-14735 disclose start-up control devices for transferring programs and the like when the computer system is started.
8, JP-A-1-154226, JP-A-1-154226
261758, JP-A-5-151369,
JP-A-8-305680 and JP-A-9-160
No. 824 and the like.

Hereinafter, a typical start-up control device will be described with reference to FIG. This activation control device has the same basic configuration as the device described in Japanese Patent Application Laid-Open No. 1-261758.

In FIG. 8, a DMA controller 801 is used.
Are connected to the CPU 101, the ROM 802, the SRAM 803, and the address decoder 804.

A start switch 103 is connected to a reset terminal of the CPU 101. In addition, the CPU 10
1 is connected to a DMA controller 801, a ROM 802, and an SRAM 803 via a data bus 810, and is connected to an address decoder 8 via an address bus 807.
04.

The ROM 802 has an address decoder 804
And the data bus 810. Also, SRA
M803 includes an address decoder 804 and a data bus 8
10 is connected.

Next, the operation of the apparatus shown in FIG. 8 will be described with reference to the timing chart shown in FIG.

When the start switch 103 is depressed, the start signal 116 becomes active (T22). As a result, the CPU 101 is reset and activated (T
23).

When the CPU 101 is started, the ROM
The boot program in the BIOS stored in the 802 is read. Then, the CPU 101 starts the DMA controller 801 according to the read start program (T24-T25). DMA controller 801
Converts the data (BIOS) of a predetermined area stored in the ROM 802 into an SRAM according to an instruction from the CPU 101.
803 (T27-T28, T28-T2
9). The data transfer here is for one piece of data.
One cycle to read from ROM 802, SRAM 8
It takes one cycle to write 03. That is, two cycles are required to transfer one data. Then, reading and writing are repeated until data in all the areas specified by the CPU 101 is transferred.

After the data transfer by the DMA controller 801 is completed, the CPU 10
1 accesses the SRAM 803 and reads the BIOS. SRAM rather than access time to ROM 802
Since the access time to 803 is shorter, the operation speed of the entire system is improved.

[0014]

However, in a start-up control device using a conventional DMA controller,
There are the following problems.

That is, the first problem is that the data transfer operation by the DMA controller transfers one data in two cycles of reading and writing, so that the transfer takes time.

The second problem is that the DMA controller
Since the transfer operation is performed according to the instruction from the CPU, the CPU
Is a ROM that takes a long time to access to transfer
In this case, it is necessary to read a predetermined instruction code from the device, and it takes time to start the transfer, and as a result, the operation speed of the entire system is reduced.

An object of the present invention is to provide an inexpensive start-up control device that improves the operation speed of the entire system by improving the transfer operation of the BIOS when the CPU is started.

The control circuit described in Japanese Patent Application Laid-Open No. 61-147358 has an s-RAM with a CPU separated.
The initial program stored in the EPROM is transferred to
After that, the s-RAM and the CPU are connected. Therefore, this control circuit does not have the second problem. However, since this control circuit performs bus switching control, there is another problem that the bus connection configuration is complicated and the connection control is complicated.

Japanese Patent Laid-Open Publication No. Hei 1-261758 discloses that the DMA controller may transfer the BIOS from the ROM to the RAM by hardware processing when the system is started. However,
This publication does not disclose anything about starting transfer without activating the CPU and performing data transfer in one cycle, and does not suggest the present invention.

Further, Japanese Patent Application Laid-Open No. 9-160824 discloses a technique in which transfer from ROM to RAM is performed in one cycle. However, this technique relates to a technique specializing in a read-only storage device, and does not describe a relationship with a CPU at all. That is,
The read-only storage device described in this publication is a BIO
It cannot be used as a device for storing programs and data essential for the operation of the CPU such as S.

[0021]

According to the present invention, in a system using a microcomputer, a BIOS instruction code is transferred from a PAGE ROM to an SDR immediately after power-on.
Means for performing transfer processing to the AM in one cycle, means for starting the CPU after the transfer of the BIOS is completed, means for reading data from the SDRAM in response to a request from the CPU after the CPU is started, and means for writing data to the SDRAM An activation control device characterized by the following is obtained.

According to the present invention, the CPU and the CP
Start-up for starting a computer system including: a first nonvolatile memory in which a BIOS referred to by U is written; and a second memory accessible from the CPU at a higher speed than the first memory. In the control device, the CP
Before starting U, the boot control device is characterized in that the BIOS is transferred from the first memory to the second memory.

Here, the transfer of the BIOS from the first memory to the second memory is performed in one cycle.

Specifically, the activation control device includes a CPU activation control unit connected to an activation switch and the CPU;
And a transfer control unit connected to the second memory, wherein the CPU start control unit outputs a transfer start signal to the transfer control unit in response to a start signal output from the start switch. And the transfer control unit includes the CPU
In response to the transfer start signal from the activation control unit, the transfer of the BIOS from the first memory to the second memory is executed, and when the transfer is completed, the transfer end signal indicating the transfer completion is output. Output to a CPU activation control section, wherein the CPU activation control section outputs a reset signal instructing the CPU to activate in response to the transfer end signal.

Further, the transfer control unit controls a read operation for the first memory, a first memory control unit,
A second memory control unit that controls a read / write operation to the second memory, wherein the second memory control unit operates according to a request from the CPU after startup.
A read / write operation for the second memory is performed.

Further, the first memory is PAGERO.
M, wherein the second memory is an SDRAM.

The activation control device is constituted by hardware.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a computer system provided with a start-up control device according to a first embodiment of the present invention.

The activation control device of FIG. 1 is constituted by hardware, and includes a CPU activation control unit 107, an SDRA
It has an M control unit 108 and a PAGERAM control unit 109, and is connected to the start switch 103. The activation control device is connected to the CPU 101 via a plurality of signal lines including a first data bus 113, and is connected to the PAGERAM1 via a plurality of signal lines including a second data bus 120.
04 and an SDRAM (synchronous DRAM) 105.

The start switch 103 receives an operation such as pressing down, generates a start signal 116, and outputs the signal to the start control device.

The start control device 102 receives the PAGEROM address signal 117 and the PAGEROMCS_B signal 11
8 and the PAGEROM RD_B signal 119 are output to control the READ operation for the PAGEROM 104. In addition, the activation control device 102 controls the SDRAM CK
E signal 121, SDRAM SCLK signal 122, SD
RAM address signal 123, SDRAM CS_B signal 124, SDRAM RAS_B signal 125, SDRAM
CAS_B signal 126, SDRAM WR_B signal 1
27 and the SDRAM DMQ signal 128,
READ operation on SDRAM 105 and WRIT
Control E operation.

The CPU 101 has an address decoder 106
It is connected to the. The first address signal 112 output from the CPU 101 is supplied to the activation control device 102 and the address decoder 106.

The address decoder 106 includes a CPU 101
Decodes the first address signal 112 supplied from
The result is output to the activation control device 102 as SDRAMCS_B110.

Referring to FIG. 2, there is shown a detailed configuration of the activation control device 102 shown in FIG.

The CPU activation control unit 107 has a first RS flip-flop 201, an OR gate 203, a second RS flip-flop 204, and a counter 205. The CPU activation control unit 107 outputs an external clock signal 129 from the activation switch 103 to the activation signal 116.
However, when the transfer end status signal 214 is supplied from the SDRAM control unit 108, the transfer start signal 21
3 and the CPU RESET signal 111 are output to the SDRAM control unit 108 and the CPU 101, respectively.

The PAGEROM control section 109 has a counter 211 and a signal generation section 212. And P
The AGEROM control unit 109 receives an external clock signal 129 and a transfer start signal 2 from the CPU activation control unit 107.
13 and PAGERO from the SDRAM control unit 108
PAGEROM 104 in response to the M access signal 218
PAGEROM address signal 117, PAGEROM
CS_B signal 118 and PAGEROM RD_B
119 is output.

The SDRAM control unit 108 controls the counter 20
6, a comparator 207, a termination address register 208, an address selection unit 209, and a signal generation unit 210. The signal generator 210 includes the first data bus 1
13 and the second data bus 120 are connected. The SDRAM control unit 108 receives an external clock signal 129 and a transfer start signal 2 from the CPU activation control unit 107.
13, the first address signal 112 from the CPU 101, C
PU RD_B signal 114, CPU WR_B signal 115, and SDRAM from address decoder 106
In response to the CS_B signal 110, the SDRAM 105 sends the SDRAM CKE signal 121 and the SDRAM SCL
K signal 122, SDRAM address signal 123, SD
RAM CS_B signal 124, SDRAM RAS_B
Signal 125, SDRAM CAS_B signal 126, SD
The RAM WR_B signal 127 and the SDRAM DQM signal 128 are output.

Note that the counter 205, the counter 206, and the counter 2 used in the activation control device 102
Any of 11 may be a count-up counter or a count-down counter.

In the end address register 208 of the SDRAM control unit 108, the last address among the addresses symmetrical to the data transfer is set.
It may be fixed or may be changed by the CPU 101 later.

Furthermore, the activation control device 102 determines whether the transfer operation has been completed. The determination may be performed by the SDRAM control unit 108 or the PAGERAM control unit 1 may be used.
09 may be performed.

Next, the start control device 1 shown in FIGS.
Operation 02 will be described with reference to the time chart of FIG.

As shown in FIG.
Is activated when an operation such as pressing down is performed.
Is activated (T1). The activation signal 116 is
First RS flip-flop 201 of U activation control section 107
, And as a result, the first RS flip-flop 201 is set. That is, the first RS flip-flop 201 activates the transfer start signal 213 when the activation signal 116 is activated.

In the CPU activation control unit 107, when the transfer start signal 213 becomes active, the second RS flip-flop 204 is reset via the OR gate 203. That is, the second RS flip-flop 204 is
The RESET signal 111 is stabilized at Low.

On the other hand, when the transfer start signal 213 changes from inactive to active, the SDRAM control unit 108 initializes the SDRAM 105 if the transfer completion status 214 is inactive (T2-T).
3). After that, the SDRAM 105
After outputting a ROW address as the RAM address signal 123 and setting the ROW address in the SDRAM 105,
The PAGEROM access signal 218 is activated (T4).

The PAGE ROM control unit 109 controls the PAGE
When the ROM access signal 218 becomes active, PA
A PAGEROM CS_B signal 118, a PAGEROM RD_B signal 119, and a PAGEROM address signal 117 are output to the GEROM 104. PAG
EROM 104 responds to these signals by PAGE.
The BIOS stored at the address specified by the ROM address signal 117 is output to the second data bus 120.

Further, the SDRAM control unit 108
After the EEPROM 104 outputs valid data to the second data bus 120, the SDRAM SCLK signal 122 and SDR
The CAS address as the AM address signal 123 is represented by S
Output to the DRAM 105. As a result, PAGEROM
BIOS output from 104 to the second data bus 120
Is written directly to the SDRAM 105. Furthermore, SD
The RAM control unit 108 generates the count pulse signal 215 and updates the counter 206. The counter 206
The value updated by the count pulse signal 215
It is output to the address selection unit 209 as the AM update address 219 (T5).

When the transfer start signal 213 is active, the address selection section 209 of the SDRAM control section 108 transmits the SDRAM update address 219 to the transfer start signal 213.
Is inactive, the value of the first address signal 112 is selectively output to the signal generator 210 as the SDRAM address 217.

Comparator 207 of SDRAM control unit 108
Is the value of the counter 206 and the end address register 208
The transfer completion status signal 214 is activated when these values match (T7).

The signal generation section 212 of the PAGEROM control section 109 outputs the CAS address as the SDRAM address signal 123 and outputs the SDRAM SCLK signal 122 while the SDRAM control section 108 outputs the first data to the SDRAM 105. The count pulse 216 is output to the counter 211. Counter 2
Reference numeral 11 denotes a PAGE ROM address signal 117 which is updated by the count pulse 216 and indicates the updated value.
Output to AGEROM104. PAGEROM104
Transmits the data stored at the address corresponding to the updated PAGEROM address signal 117 to the second data bus 1.
Output to 20.

The SDRAM control unit 108 has a PAGERO
When new data is output from M104, SDR
An AM SCLK signal 122 is output to the SDRAM 105, and data on the second data bus 120 is directly transferred to the SDRAM 105.
Write to 105 (T5-T6).

The SDRAM control unit 108 operates until the transfer completion status signal 214 becomes active (accurately,
As a result, until the transfer start signal 213 becomes inactive), the updating of the counter 206 and the SDRAM S
The output of the CLK signal 122 to the SDRAM 105 is repeated. The PAGEROM control unit 109 is an SDRAM
The generation of the count pulse 216 is repeated according to the operation of the control unit 108.

Further, the SDRAM control unit 108
When the number of write data after setting the ROW for the AM 105 exceeds the burst length of the SDRAM 105,
The write operation to the DRAM 105 is temporarily terminated, and R
Start over from the OW setting again.

In the CPU activation control unit 107, the SDRAM
When the transfer end status signal 214 from the control unit 108 becomes active, the first RS flip-flop 201 is reset, and the transfer start signal 213 becomes inactive. At the same time, the second RS flip-flop 204 is set by the activation of the transfer end status signal 214, and activates the CPU RESET signal 111 (T8).

The CPU RESET signal 111 is output from the CPU 1
01 and is supplied to the counter 205 in the CPU activation control unit 107. Counter 205
Starts counting pulses of the clock signal 129 when the CPU RESET signal 111 becomes active.
When the counter 205 counts a predetermined number of clock pulses, the counter 205 outputs the CARRY signal 202 to the OR gate 2.
03 is output. When the CARRY signal 202 is input, the OR gate 203 outputs the signal to the reset terminal of the second RS flip-flop 204. As a result, the second R
The S flip-flop 204 is reset and the CPUR
The ESET signal 111 becomes inactive.

The CPU 101 starts up when the CPU RESET signal 111 becomes active once and then becomes inactive.

Referring to FIG. 4, an operation for accessing the SDRAM 105 to read the BIOS or write data after the CPU 101 is started will be described.

When CPU 101 outputs first address signal 112 to access SDRAM 105, address decoder 106 activates SDRAMCS_B signal 110 (T9).

In the activation control device 102, the address selecting unit 209 of the SDRAM control unit 108
In response to the activation of the B signal 110, the SRA
The first address signal 110 is output to the signal generator 210 as the M address signal 217. Then, the signal generator 21
0 indicates that the CPU 10 output to the first data bus 113 is active when the CPU WR_B signal 115 is active.
1 is output to the second data bus 120 and the SDRAM 105 is supplied with the second data bus 12.
The data on 0 is written (T9-T10). When the CPURD_B signal 114 is active, the signal generation unit 210 performs a READ operation for reading data from the SDRAM 105, and outputs data output from the SDRAM 105 to the second data bus 120 to the first data bus 113, Read by CPU 101 (T11-T1
2).

As described above, the activation control device according to the present embodiment is configured to activate the activation signal 1 from the activation switch 103.
When 16 becomes active, the BIOS stored in the PAGE ROM 104 is transferred to the SDRAM 105 in one cycle, and when the transfer is completed, the CPU RESET signal 111 is activated to activate the CPU 101.

The activation control device 1 according to the present embodiment
02, after the transfer operation of the BIOS is completed, the CPU 1
01 and the SDRAM 105. That is, when the CPU 101 attempts to access an address located in the SDRAM 105, the address decoder 106
Activate the AMCS_B signal 110. When the SDRAMCS_B signal 110 becomes active, the activation control device 102 reads data stored in the address of the SDRAM 105 corresponding to the address output by the CPU 101 to the first address 113, or
An operation of writing data to the corresponding address 105 is performed.

As described above, in the activation control device according to the present embodiment, the PAGE ROM 104 is activated when the system is activated.
The BIOS stored in the SDRAM in one cycle
After the transfer to the CPU 105, the CPU 101 is activated, and the activation control device 102
The CPU 101 can access the SDRAM 105 via the activation control device 102 immediately after activation by having the function of performing data transfer between the SDRAM 105 and the SDRAM 105.

Normally, the SDRAM requires a dedicated controller different from the SRAM and the ROM. In the present embodiment, however, the activation control device also serves as the controller.
The system configuration is simplified, and both design and maintenance can be simplified.

Since writing and reading to and from the SDRAM are performed by burst transfer, the writing and reading to and from the normal RAM can be performed at higher speed, and as a result, the operation of the entire system can be sped up.

Next, a second embodiment of the present invention will be described in detail with reference to FIGS.

The start control device 501 according to the present embodiment
Is basically the same as the activation control device 102 according to the first embodiment, except that the address bus connected to the PAGE ROM 104 and the address bus connected to the SDRAM 105 are integrated. That is, in the activation control device 102 of FIG.
Although the GEROM address signal 117 and the SDRAM address signal 123 are supplied to the SDRAM 105, as shown in FIG. 5, in the activation control device 501 of the present embodiment, these are used as the memory address signal 505. , PAGEROM104 and SDRAM
105. In order to realize such a configuration, the activation control device 501 includes a PAGEROM / SDRAM address selection unit 504.
Is provided. Also, PAGEROM / SDRAM
With the provision of the address selection unit 504, the SDR
The AM control unit 108 and the PAGEROM control unit 109 are also slightly changed, and the SDRAM control unit 50
2 and a PAGEROM control unit 503.

Next, referring to FIG.
1 will be described in detail.

CPU activation control section 107 outputs transfer start signal 213 not only to SDRAM control section 502 and PAGEROM control section 503, but also to PAGEROM / SDRAM address selection section 504.

The address selection unit 601 of the SDRAM control unit 502 sets the SDRAM address 217
/ SDRAM address selection section 504. Also,
The signal generation unit 602 outputs the PAGEROM access signal 60
4 to PAGEROM / SDRAM address selector 504
Output to

Counter 6 of PAGEROM control section 503
03 is a PAGE / SDRAM address selection unit 5 which outputs a PAGE ROM address signal 117 representing the count value.
04.

The PAGEROM / SDRAM address selection section 504 receives the PAG from the PAGEROM control section 503.
EROM address signal 117 and SDRAM control unit 50
SDRAM address signal 215 from page 2 and PAGER
In response to the OM access signal 604, the memory address signal 505 is transmitted to the PAGE ROM 104 and the SDRAM 10
Output to 5

The operation of the activation control device 501 will be described below with reference to the timing chart shown in FIG.

When the activation signal 116 is supplied from the activation switch 103, the CPU activation control unit of the activation control device 501 activates the transfer start signal 213 (T13-
T14).

When the transfer start signal 213 becomes active, the SDRAM control unit 502 sets ROW and COL addresses for the SDRAM 105 (T16-
T17). During this time, the SDRAM control unit 502
The EROM access signal 604 is kept inactive.

When the PAGEROM access signal 604 is inactive, the PAGEROM / SDRAM address selection section 504
RAM address signal 217 is changed to memory address signal 505
(T13-T17).

Further, the SDRAM control unit 502
When the address setting for AM 105 is completed, RAG
The EROM access signal 604 is activated.

When the PAGEROM access signal 604 becomes active, the PAGEROM / SDRAM address selection section 504 outputs a P signal from the PAGEROM control section 503.
The AGEROM address signal 117 is output as the memory address signal 505 (T17-T20).

As described above, in this embodiment, the PAGEROM 104 and the SDRAM 105 can be accessed using the common address bus (memory address signal 505). In the present embodiment,
Data transfer from PAGEROM 104 to SDRAM 105 is performed in one cycle by burst transfer, as in the first embodiment.

As described above, in the present embodiment, the SDRAM
Since the address bus for supplying an address signal to the PAGE ROM 105 and the PAGE ROM 104 is shared, the effect of reducing the amount of wiring can be obtained.

[0080]

The present invention has the following effects.

The first effect is that the PAGE ROM
Since data transfer to AM is performed in one cycle, B
The transfer time of the IOS can be reduced.

The second effect is that after the BIOS stored in the PAGE ROM has been transferred to the SDRAM, the CPU 1
01, so that the CPU 101 starts BI
The ability to refer to the OS at high speed.

The third effect is that since the operation of transferring the BIOS is realized only by hardware, it is possible to omit the routine related to the operation of the DMA controller from the programming related to the conventional startup control of the system. It is easy to create a program.

The fourth effect is that when transferring the BIOS, C
Since the operation of the PU is stopped, the operation time of the CPU can be minimized, and the power consumption of the entire system can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a computer system including an activation control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing details of an activation control device of FIG. 1;

FIG. 3 is a timing chart for explaining an operation of the activation control device of FIG. 2;

FIG. 4 is a timing chart for explaining an operation of the activation control device of FIG. 2;

FIG. 5 is a block diagram of a computer system including an activation control device according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing details of the activation control device of FIG. 5;

FIG. 7 is a timing chart for explaining the operation of the activation control device of FIG. 6;

FIG. 8 is a block diagram of a conventional computer system.

FIG. 9 is a timing chart for explaining a starting operation of the system of FIG. 8;

[Explanation of symbols]

101 CPU 102 Start-up control device 103 Start-up switch 104 PAGEROM 105 SDRAM 106 Address decoder 107 CPU start-up control unit 108 SDRAM control unit 109 PAGEROM control unit 110 SDRAMCS_B signal 111 CPURESET signal 112 First address signal 113 First data bus 114 CPU RD_B signal 115 CPU WR_B signal 116 Activation signal 117 PAGEROM address signal 118 PAGEROM CS_B signal 119 PAGEROM RD_B signal 120 Second data bus 121 SDRAM CKE signal 122 SDRAM SCLK signal 123 SDRAM address 124 SDRAM CS_B signal 125 SDRAM RAS_BRAM signal RAM WR_B signal 128 SDRAM DQM signal 129 Clock signal 201 First RS flip-flop 202 CARRY signal 203 OR gate 204 Second RS flip-flop 205 Counter 206 Counter 207 Comparator 208 Terminal address register 209 Address selector 210 Signal generator 211 Counter 212 Signal generation Unit 213 Transfer start signal 214 Transfer end status signal 215 Count pulse signal 216 Count pulse signal 217 SDRAM address signal 218 PAGEROM access signal 219 SDRAM update address signal 501 Start-up control device 502 SDRAM control unit 503 PAGEROM control unit 504 PAGEROM / SDRAM address selection unit 505 Memory address signal 601 Address selection Part 602 signal generator 603 counter 604 PAGEROM access signal 801 DMA controller 802 ROM 803 SRAM 804 address decoder 805 HOLDRQ signal 806 HOLDACK signal 807 address bus 808 RD_B signal 809 WR_B signal 810 data bus 811 ROM CS_B signal 812 SRAM CS_B signal

Claims (7)

[Claims] In a system using a microcomputer, an instruction code of a BIOS is transmitted to a PA immediately after power-on.
Means for transferring data from the GEROM to the SDRAM in one cycle, means for starting the CPU after the transfer of the BIOS is completed, and
An activation control device comprising means for reading AM data and writing data to SDRAM. 2. A CPU and a BIOS referred to by the CPU
And a second memory accessible from the CPU at a higher speed than the first memory. The boot control device is characterized in that the BIOS is transferred from the first memory to the second memory before booting. 3. The boot control device according to claim 1, wherein the transfer of the BIOS from the first memory to the second memory is performed in one cycle. 4. A CPU start control unit connected to the start switch and the CPU, and a transfer control unit connected to the CPU start control unit and connected to the first memory and the second memory. The CPU start control unit outputs a transfer start signal to the transfer control unit in response to a start signal output from the start switch, and the transfer control unit starts the transfer from the CPU start control unit. In response to the signal, the transfer of the BIOS from the first memory to the second memory is executed, and when the transfer is completed, a transfer end signal indicating the transfer completion is output to the CPU activation control unit. 4. The activation control system according to claim 2, wherein the CPU activation control unit outputs a reset signal instructing the CPU to activate in response to the transfer end signal. Control device. 5. A transfer control unit comprising: a first memory control unit that controls a read operation on a first memory; and a second memory control unit that controls a read / write operation on the second memory. 5. The activation control device according to claim 4, wherein the second memory control unit performs a read / write operation on the second memory in accordance with a request from the CPU after activation. . 6. The activation control device according to claim 2, wherein said first memory is a PAGEROM, and said second memory is an SDRAM. 7. The activation control device according to claim 1, wherein the activation control device is configured by hardware.