TWI487323B - Test circuit for internet interface - Google Patents

Description

Network interface test circuit

The present invention relates to a test circuit, and more particularly to a test circuit for testing a network interface.

With the development of communication technology, Ethernet has been widely used in various fields, and RJ45 has been widely used as the most common network interface on computers. Currently, the Ethernet standard for RJ45 network interface transmission is 10Base- T, 100Base-TX, 1000Base-T. In order to ensure the quality of the Ethernet signal sent by the RJ45 interface, the signal integrity measurement must be performed on the transmitted signal. However, the conventional test device needs to manually insert the oscilloscope and the test device during the test. It takes a lot of test time and may cause inaccuracies in measurement results due to human factors.

In view of the above, it is necessary to provide an automatic network interface test circuit to improve the test accuracy and test efficiency of the network interface.

A network interface test circuit for testing a network interface of an electronic device, the network interface test circuit comprising a connector, two probes, a microcontroller, a high speed switch chip, first to third switch chips, a bus switch chip and a first load board, the connector is configured to connect to a network interface on the electronic device, the probe is used for connecting to a measuring instrument, and the first output pin of the microcontroller is connected to the a control pin of the high-speed switch chip, wherein the first to seventh input pins of the high-speed switch chip are respectively connected to the pins on the connector, and the first and second output pins of the high-speed switch chip are respectively connected to the first a two-input pin of a switch chip, two control pins of the first and second switch chips are connected to a second output pin of the microcontroller, and the first to fourth switches of the first and second switch chips The pins are connected to the first load board, and the two output pins of the second switch chip are respectively connected to the first and second input pins of the third switch chip, and the two control pins of the third switch chip are connected. Micro control a third output pin, the two output pins of the third switch chip are respectively connected to the probe, and the first to third input pins of the bus switch chip are respectively connected to the fourth to sixth output leads of the microcontroller The first to sixth output pins of the bus bar switch chip are connected to the first load board, the ground pin of the bus bar switch is grounded, and the microcontroller and the high-speed switch chip respectively output control signal control The first and second switches and the bus bar switch chip are selectively turned on to connect different loads on the first load board to the network interface test circuit, and the microcontroller controls output through the second switch chip The signal controls the third switch wafer to be turned on to display the test result through a measuring instrument.

Compared with the prior art, the network interface test circuit can automatically test the signal of the transmission standard of the network interface on the electronic device, without manually inserting the oscilloscope and the test circuit, which is convenient for the tester and saves. Test time increases test efficiency.

Referring to FIG. 1 and FIG. 2, the network interface test circuit 100 of the present invention is used to test the network interface of an electronic device (such as a computer motherboard). The preferred embodiment of the network interface test circuit 100 includes a connector 10, two probes 40, a microcontroller U1, a high speed switch chip U2, a switch chip U3-U8, a bus switch chip U9, and two loads. Plates 20 and 30, a switch K1, resistors R1-R13, capacitors C1 and C2, and a plurality of light-emitting diodes, such as ten light-emitting diodes D1-D10. The connector 10 is used to connect to a network interface on the computer motherboard, and the probe 40 is used to connect to a measuring instrument such as an oscilloscope. In this embodiment, the switch K1 is a push button switch, the model of the microcontroller U1 is MK7A20P, the model of the high speed switch chip U2 is MAX4892E, and the model of the switch chip U3-U8 is FSA2267, the bus bar switch chip The model number of the U9 is SN74CBTLV3125. The load board 20 is provided with first to sixth loads L1-L6, and the sizes of the first to sixth loads L1-L6 can be selected according to the needs of the test. A seventh load L7 is disposed on the load board 30, and the seventh load L7 is a resistor.

The output pin PC0 of the microcontroller U1 is connected to the control pin SEL of the high-speed switch chip U2, and the input pins A1-A7 of the high-speed switch chip U2 are respectively connected to the pins on the connector 10, the high-speed switch chip The voltage pin VCC of U2 is connected to a voltage source VCC1. The output pins 0B1 and 1B1 of the high-speed switch chip U2 are respectively connected to the input pins 2A and 1A of the switch chip U3, and the control pins 1S and 2S of the switch chip U3 are connected to the output pin PC1 of the microcontroller. The switch pins 1B0, 2B0 of the switch wafer U3 are respectively connected to both ends of the first to third loads L1 - L3, and the switch pins 1B1, 2B1 are respectively connected to both ends of the fourth to sixth loads L4 - L6. The control pins 1S and 2S of the switch chip U4 are connected to the output pin PC1 of the microcontroller U1, and the switch pins 1B0 and 2B0 are respectively connected to the two ends of the first to third loads L1-L3, and the switch pins thereof 1B1 and 2B1 are respectively connected to the two ends of the fourth to sixth loads L4-L6, and the output pins 1A and 2A are respectively connected to the input pins 1B0 and 2B0 of the switch chip U8, and the control pin 1S of the switch chip U8, 2S is connected to the output pin PC4 of the microcontroller U1, and its output pins 1A, 2A are connected to the probe 40, respectively. The output pins 0B2, 1B2, 2B2, and 3B2 of the high-speed switch chip U2 are respectively connected to the input pins 1B0, 2B0, 1B1, and 2B1 of the switch chip U5, and the control pins 1S and 2S of the switch chip U5 are connected to the micro control. The output pin PC2 of the U1, the output pins 1A, 2A are respectively connected to the input pins 1B0, 2B0 of the switch chip U7, and the control pin of the switch chip U7 is connected to the output pin PC3 of the microcontroller U1. The output pins 1A, 2A are connected to both ends of the load L7 and to the output pins 1B1, 2B1 of the switch wafer U8. The output pins 4B2, 5B2, 6B2, and 7B2 of the high-speed switch chip U2 are respectively connected to the input pins 1B0, 2B0, 1B1, and 2B1 of the switch chip U6, and the control pins 1S and 2S of the switch chip U6 are connected to the micro-control. The output pin PC2 of the U1 is connected to the input pins 1B1 and 2B1 of the switch chip U7. The voltage pins of the switch chip U3-U8 are connected to the voltage source VCC1, and the ground pins are grounded. The voltage pin of the bus bar switch chip U9 is connected to the voltage source VCC1, and the input pins 1OE-3OE are respectively connected to the output pins PC5, PC6, PC7 of the microcontroller U1, and the output pins 1A, 1B are respectively connected thereto. Both ends of the first to sixth loads L1 - L6 , the output pins 2A , 2B are respectively connected to the two ends of the first to sixth loads L1 - L6 , and the output pins 3A , 3B are respectively connected to the first to the At both ends of the six loads L1-L6, the ground pin GND of the bus bar switch chip U9 is grounded. The output pin PB6 of the microcontroller U1 is grounded via the switch K1 and connected to the voltage source VCC1 via the resistor R1. The voltage pin RESETB of the microcontroller U1 is connected to the voltage source VCC1 via the resistor R3, and its clock pin OSC1 is connected to the voltage source VCC1 via the resistor R2. The capacitor C1 is connected in series between the clock pin OSC1 of the microcontroller U1 and the ground. The voltage pin VDD of the microcontroller U1 is connected to the voltage source VCC1. C2 is connected in series between the voltage pin VDD of the microcontroller U1 and the ground, and the ground pin VSS of the microcontroller U1 is grounded. The output pins PA0-PA3 and PB0-PB5 of the microcontroller U1 are respectively connected to the anodes of the corresponding light-emitting diodes D1-D10 via the resistors R4-R13, and the cathodes of the light-emitting diodes D1-D10 are Ground.

In the embodiment, the RJ45 network interface is taken as an example for description. Because the RJ45 network interface can transmit Ethernet standards of 10Base-T, 100Base-TX, and 1000Base-T, the output signals of the Ethernet standards of 100Base-TX and 1000Base-T are the same. Therefore, it is necessary to separately perform signal integrity testing on the signals transmitted by the two groups of Ethernet standards.

First, the test principle is described by taking the Ethernet standard of the transmission as 10Base-T as an example.

During testing, the network interface test circuit 100 is connected to the network interface of the computer motherboard through the connector 10, and the network interface test circuit 100 is connected to the oscilloscope through the probe 40. The network interface test circuit 100 is first activated by pressing the push button switch K1. When the output pin PC0 of the microcontroller U1 outputs a low level signal to the control pin SEL of the high speed switch chip U2, the output pins 0B1 and 1B1 of the high speed switch chip U2 and the input of the switch chip U3 are cited. The pins 1A and 2A are connected to be turned on, and the output pin PC1 of the microcontroller U1 outputs a low level signal to the control pins 1S and 2S of the two switch chips U3 and U4, and the outputs of the two switch chips U3 and U4 The pins 1B0 and 2B0 are connected to be connected and connected to the load board 20. When the output pin PC5 of the microcontroller U1 outputs a low level signal to the input pin 1OE of the bus bar switch chip U9, the output pin is output. When PC6 and PC7 respectively output a high level signal to the input pins 2OE, 3OE of the bus bar switch chip U9, the output pins 1A and 1B of the bus bar switch chip U9 are connected to be turned on, and at this time, the load board 20 is A load L1 is connected for the first test. At this time, the input pins 1B0 and 2B0 of the switch chip U8 are connected to the output pins 1A and 2A of the switch chip U4, and the output pin PC4 of the microcontroller U1 is connected. Output a low level signal to the control pins 1S, 2S of the switch chip U8, U8 off output pin wafer 1A, 2A 40 will show through the probe through the first load signal on the oscilloscope, so that the test results determination tester. After the first test is completed, the output pin PC6 of the microcontroller U1 outputs a low level signal to the input pin 2OE of the bus bar switch chip U9, and the output pins PC5 and PC7 respectively output a high level signal. The input pins 1OE, 3OE of the bus bar switch chip U9 are connected to the output pins 2A and 2B of the bus bar switch chip U9, and the second load L2 on the load board 20 is connected for testing. When the output pin PC7 of the microcontroller U1 outputs a low level signal to the input pin 3OE of the bus bar switch chip U9, the output pins PC5 and PC6 respectively output a high level signal to the bus bar switch chip U9. The input pins 1OE, 2OE are connected to the output pins 3A and 3B of the bus bar switch chip U9, and the third load L3 on the load board 20 is connected for testing.

After the previous test is completed, the output pin PC1 of the microcontroller U1 outputs a high level signal to the control pins 1S, 2S of the two switch chips U3, U4, and the output pins of the two switch chips U3 and U4. 1B1 and 2B1 are connected and connected to the load board 20. The output pin PC5 of the microcontroller U1 outputs a low level signal to the input pin 1OE of the bus switch chip U9, and the output pins PC6 and PC7. The high-level signals are respectively output to the input pins 2OE, 3OE of the bus bar switch chip U9. At this time, the output pins 1A and 1B of the bus bar switch chip U9 are connected to be turned on, and the fourth load L4 on the load board 20 is Access for testing. When the output pin PC6 of the microcontroller U1 outputs a low level signal to the input pin 2OE of the bus bar switch chip U9, the output pins PC5 and PC7 respectively output a high level signal to the bus bar switch chip U9. The input pins 1OE, 3OE, the output pins 2A and 2B of the bus bar switch chip U9 are connected to be turned on, and the fifth load L5 on the load board 20 is connected for testing. When the output pin PC7 of the microcontroller U1 outputs a low level signal to the input pin 3OE of the bus bar switch chip U9, the output pins PC5 and PC6 respectively output a high level signal to the bus bar switch chip U9. The input pins 1OE, 2OE, at this time, the output pins 3A and 3B of the bus bar switch chip U9 are connected to be turned on, and the sixth load on the load board 20 is connected for testing. After the six loads L6 on the load board 20 are all tested for access, the network interface test circuit completes the signal integrity test with a transmission rate of 10Base-T through the network interface.

When the network interface test circuit 100 needs to test the Ethernet standard of 100Base-T and 1000Base-T through the network interface, it is only necessary to output the output pin PC0 of the microcontroller U1. The level signal is sent to the control pin SEL of the high-speed switch chip U2, so that the network interface test circuit 100 can be automatically switched to test the transmitted Ethernet standard 100Base-T and 1000Base-T signals. When the output pin PC2 of the microcontroller U1 outputs a low level signal to the control pins 1S and 2S of the two switch chips U5 and U6, the output pins 0B2 and 1B2 of the high speed switch chip U2 and the switch respectively 1B0 and 2B0 of the chip U5 are connected to be turned on, and the output pins 4B2 and 5B2 of the high-speed switch chip U2 are respectively connected to the input pins 1B0 and 2B0 of the switch chip U6, and the output pin PC3 of the microcontroller U1 outputs a When the low level is given to the control pins 1S, 2S of the switch chip U7, the input pins 1B0 and 2B0 of the switch chip U7 are connected to be turned on, and the output pins 1A, 2A are connected to the seventh load L7 and connected with the switch. The input pins 1B1 and 2B1 of the chip U8 are connected to be turned on. The output pin PC4 of the microcontroller U1 outputs a low level signal to the control pins 1S and 2S of the switch chip U8, and the output pin 1A of the switch chip U8. 2A transmits the signal transmitted through the seventh load L7 to the oscilloscope through the probe 40, so that the tester judges the test result.

When the output pin PC2 of the microcontroller U1 outputs a high level signal to the control pins 1S, 2S of the two switch chips U5, U6, the output pins 2B2, 3B2 of the high speed switch chip U2 and the switch respectively 1B1 and 2B1 of the chip U5 are connected to be turned on. The output pins 6B2 and 7B2 of the high-speed switch chip U2 are respectively connected to the input pins 1B1 and 2B1 of the switch chip U6, and the output pin PC3 of the microcontroller U1 outputs a When the low level is given to the control pins 1S, 2S of the switch chip U7, the input pins 1B0 and 2B0 of the switch chip U7 are connected to be turned on, and the output pins 1A, 2A are connected to the seventh load L7 and coupled to the switch chip. The input pins 1B1 and 2B1 of U8 are connected to be turned on. The output pin PC4 of the microcontroller U1 outputs a low level signal to the control pins 1S and 2S of the switch chip U8, and the output pin 1A of the switch chip U8, 2A displays the signal transmitted through the seventh load L7 on the oscilloscope through the probe 40, so that the tester judges the test result.

When the output pin PC2 of the microcontroller U1 outputs a low level signal to the control pins 1S and 2S of the two switch chips U5 and U6, the output pins 0B2 and 1B2 of the high speed switch chip U2 and the switch respectively 1B0 and 2B0 of the chip U5 are connected to be turned on, and the output pins 4B2 and 5B2 of the high-speed switch chip U2 are respectively connected to the input pins 1B0 and 2B0 of the switch chip U6, and the output pin PC3 of the microcontroller U1 outputs a When the high level is given to the control pins 1S, 2S of the switch chip U7, the input pins 1B1 and 2B1 of the switch chip U7 are connected to be turned on, and the output pins 1A, 2A are connected to the seventh load L7 and coupled to the switch chip. The input pins 1B1 and 2B1 of U8 are connected to be turned on. The output pin PC4 of the microcontroller U1 outputs a low level signal to the control pins 1S and 2S of the switch chip U8, and the output pin 1A of the switch chip U8, 2A displays the signal transmitted through the seventh load L7 on the oscilloscope through the probe 40, so that the tester judges the test result.

When the output pin PC2 of the microcontroller U1 outputs a high level signal to the control pins 1S, 2S of the two switch chips U5, U6, the output pins 2B2, 3B2 of the high speed switch chip U2 are respectively 1B1 and 2B1 of the switch chip U5 are connected to be turned on, and the output pins 6B2 and 4B2 of the high-speed switch chip U2 are respectively connected to the input pins 1B1 and 2B1 of the switch chip U6, and are outputted by the output pin PC3 of the microcontroller U1. When a high level is applied to the control pins 1S, 2S of the switch chip U7, the input pins 1B1 and 2B1 of the switch chip U7 are connected to be turned on, and the output pins 1A, 2A are connected to the seventh load L7 and connected to the switch. The input pins 1B1 and 2B1 of the chip U8 are connected to be turned on. The output pin PC4 of the microcontroller U1 outputs a low level signal to the control pins 1S and 2S of the switch chip U8, and the output pin 1A of the switch chip U8. 2A transmits the signal transmitted through the seventh load L7 to the oscilloscope through the probe 40, so that the tester judges the test result.

In this embodiment, because the tested Ethernet standard of 10Base-T requires six load state tests on the load L1-L6 on the load board 20, the Ethernet standard of the transmission is 100Base-TX and 1000Base. The -T test requires four load state tests on the load L7 on the load board 30. Therefore, each of the load state tests is displayed using ten light-emitting diodes D1-D10, and one light-emitting two is used when the test passes. The polar body is bright, otherwise it is not bright. At the completion of each test, the microcontroller U1 controls the illumination of a light-emitting diode.

The network interface test circuit 100 can automatically test the Ethernet standard signals of different transmissions of the network interface on the computer motherboard, without manually inserting the oscilloscope and the test circuit, which is convenient for the tester. , saving test time and improving test efficiency. At the same time, the test state can be easily observed by the light or the LED being turned on or off.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

100. . . Network interface test circuit

10. . . Connector

40. . . Probe

U1. . . Microcontroller

U2. . . High speed switch chip

U3-U8. . . Switch chip

U9. . . Bus switch chip

20, 30. . . Load board

K1. . . switch

R1-R13. . . resistance

C1, C2. . . capacitance

D1-D10. . . Light-emitting diode

L1-L7. . . load

VCC1. . . power source

1 and 2 are schematic diagrams of a preferred embodiment of a network interface test circuit of the present invention.

100. . . Network interface test circuit

10. . . Connector

40. . . Probe

U2. . . High speed switch chip

U3-U8. . . Switch chip

U9. . . Bus switch chip

20, 30. . . Load board

L1-L7. . . load

VCC1. . . power source

Claims (7)

A network interface test circuit for testing a network interface of an electronic device, the network interface test circuit comprising a connector, two probes, a microcontroller, a high speed switch chip, and first to third switch chips a bus bar switch chip and a first load board for connecting to a network interface on the electronic device, the probe being used for connecting to a measuring instrument, the first output pin of the microcontroller is connected a control pin of the high-speed switch chip, the first to seventh input pins of the high-speed switch chip are respectively connected to the pins on the connector, and the first and second output pins of the high-speed switch chip are respectively connected to the pin Two input pins of the first switch chip, two control pins of the first and second switch chips are connected to the second output pin of the microcontroller, first to fourth of the first and second switch chips The switch pins are respectively connected to the first load board, and the two output pins of the second switch chip are respectively connected to the first and second input pins of the third switch chip, and the two control pins of the third switch chip Connect the micro control a third output pin of the third switch chip, wherein the two output pins are respectively connected to the probe, and the first to third input pins of the bus switch chip are respectively connected to the fourth to sixth outputs of the microcontroller a pin, the first to sixth output pins of the bus bar switch chip are connected to the first load board, the ground pin of the bus bar switch is grounded, and the microcontroller and the high-speed switch chip respectively output control signals Controlling selective switching of the first and second switches and the bus bar switch chip to connect different loads on the first load board to the network interface test circuit, and the microcontroller outputs the second switch chip The control signal controls the third switch wafer to conduct to display the test result through a measuring instrument. The network interface test circuit of claim 1, further comprising fourth to sixth switch chips and a second load board, wherein the third to sixth output pins of the high speed switch chip are respectively connected to the fourth The first to fourth switch pins of the switch chip, the two control pins of the fourth switch chip are connected to the seventh output pin of the microcontroller, and the two output pins of the fourth switch chip are respectively connected to the fifth a first and a second input pin of the switch chip, two control pins of the fifth switch chip are connected to an eighth output pin of the microcontroller, and two output pins of the fifth switch chip are connected to the second load On the board, the third and fourth switch pins of the third switch chip are connected to the second load, and the seventh to tenth output pins of the high speed switch chip are respectively connected to the first to the first of the sixth switch chip a four-input pin, the two control pins of the sixth switch chip are connected to the seventh output pin of the microcontroller, and the two output pins of the sixth switch chip are respectively connected to the third and the third of the fifth switch chip Four input pins, the microcontroller and the The high-speed switch chip outputs a control signal to control selective conduction of the fourth and fifth switch chips, and connects the load on the second load board to the network interface test circuit through the conduction of the sixth switch chip, and transmits The conduction of the third switch wafer displays the test result through a measuring instrument. The network interface test circuit of claim 2, wherein the first load board includes first to sixth loads, and the first and second switch pins of the first switch chip are respectively connected to the first to The third and fourth switch pins are respectively connected to the two ends of the fourth to sixth loads, and the first and second switch pins of the second switch chip are respectively connected to the first to the The third and fourth switch pins are respectively connected to the two ends of the fourth to sixth loads, and the first and second output pins of the bus bar switch chip are respectively connected to the first to sixth loads The two ends, the third and fourth output pins are respectively connected to the two ends of the first to sixth loads, and the fifth and sixth output pins are respectively connected to the two ends of the first to sixth loads, the second load The board includes a seventh load, and an output pin of the sixth switch chip is connected to both ends of the seventh load. The network interface test circuit of claim 2, further comprising a switch, first to third resistors, and first and second capacitors, wherein the ninth output pin of the microcontroller is grounded via the switch Connecting the voltage source via the first resistor, the first voltage pin of the microcontroller is connected to the voltage source via the second resistor, and the clock pin of the microcontroller is connected to the voltage source via the third resistor, the first A capacitor is connected in series between the clock pin of the microcontroller and the ground, and the second capacitor is connected in series between the second voltage pin of the microcontroller and the ground. The network interface test circuit of claim 4, further comprising first to tenth light emitting diodes and fourth to thirteenth resistors, the ninth to seventeenth output pins of the microcontroller The anodes of the first to tenth light-emitting diodes are respectively connected via the fourth to thirteenth resistors, and the cathodes of the first to tenth light-emitting diodes are grounded. The network interface test circuit of claim 1, wherein the electronic device is a computer motherboard. The network interface test circuit of claim 1, wherein the switch is a push button switch.