CN102213743A - Signal test device - Google Patents
Signal test device Download PDFInfo
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- CN102213743A CN102213743A CN2010101565167A CN201010156516A CN102213743A CN 102213743 A CN102213743 A CN 102213743A CN 2010101565167 A CN2010101565167 A CN 2010101565167A CN 201010156516 A CN201010156516 A CN 201010156516A CN 102213743 A CN102213743 A CN 102213743A
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Abstract
The invention provides a signal test device, which comprises a connector, a complex programmable logic device chip and a logic unit. The connector is provided with a plurality of connection pins; the complex programmable logic device chip is provided with multiple groups of test signal connection pins, a first control connection pin and a second control pin; the first control connection pin receives a first logic signal; the second control pin receives a second logic signal; the complex programmable logic device chip is used for connecting one of the multiple groups of test signal connection pins with the plurality of connection pins of the connector according to the logic states of the first logic signal and the second logic signal so as to output a test signal to the connector and perform test; and the logic unit connects the first control connection pin and the second control connection pin and is used for generating the first logic signal and the second logic signal.
Description
Technical field
The present invention relates to a kind of signal-testing apparatus, and be particularly related to a kind of signal-testing apparatus that is used for computer system.
Background technology
In general, in the computer system design, owing to need debug and signal testing to the element on the mainboard, each main chip all has (the joint test action group of joint test working group basically, hereinafter to be referred as JTAG) signal, when wrong (bug) occurring, debug or signal testing in system.In intel foxhollow platform, central processing unit (central processing unit, CPU), platform controller hub (Platform Controller Hub, PCH), network interface controller (NetworkInterface Controller, NIC), physical layer (physical layer, PHY), quick peripheral hardware interconnect standard (peripheral component interconnect express, PCI-E) switch, complex programmable logic device (complex programmable logic device, CPLD) etc. the JTAG signal is all arranged, and the JTAG signal of complex programmable logic device is usually as burning program.
Yet if the JTAG of each main chip external connector (connector) all, the connector quantity on the mainboard just increases much so, has also caused the rising of circuit component use cost simultaneously.And being the JTAG signal of complex programmable logic device mostly, present way is connected to controller, the JTAG signal of other chips is all reserved connector, if mistake really appears in system, go up related resistors and connector at heavy industry (rework), and such mode obviously can make testing efficiency reduce, and more is not suitable for wrong debugging occurring after the volume production.
Summary of the invention
The invention provides a kind of signal-testing apparatus, in order to reducing the use cost of circuit component effectively, and reduce the risk that test result confidence level that heavy industry (rework) causes descends.
The present invention proposes a kind of signal-testing apparatus, comprises connector, complex programmable logic device chip, logical block.Connector has a plurality of pins.The programmable logic device chip connects described connector, described complex programmable logic device chip has many group test signal pins, the first control pin and the second control pin, the described first control pin receives first logical signal, the described second control pin receives second logical signal, described complex programmable logic device chip is according to the logic state of described first logical signal and described second logical signal, and with described many group test signal pins one group of a plurality of pin that connect described connector wherein, to export test signal to described connector, to test.Logical block connects described first control pin and the described second control pin, in order to produce described first logical signal and described second logical signal.
In one embodiment of this invention, described logical block comprises first resistance, first switch, second resistance and second switch.First end of first resistance connects the described first control pin, and second end of first resistance is connected to voltage source.First end of first switch connects first end of described first resistance, and second end of first switch is held with being connected to.First end of second resistance connects the described second control pin, and second end of second resistance is connected to voltage source.First end of second switch connects first end of described second resistance, and second end of second switch is held with being connected to.
In one embodiment of this invention, described many group test signal pins comprise the test signal pin of described complex programmable logic device chip, test signal pin, platform controller hub test signal pin and the network interface controller test signal pin of central processing unit.
In one embodiment of this invention, described test signal is a joint test working group signal.
First logical signal and the logic state of second logical signal that complex programmable logic device chip of the present invention produces according to logical block, and corresponding will be not on the same group test signal pin be connected to connector, test to export test signal.Thus, signal-testing apparatus can be under the situation of not doing any hardware heavy industry (rework), on the same group the test signal of test signal pin not is connected to connector arbitrarily tests, to reduce the risk that the test result confidence level descends.In addition, signal-testing apparatus of the present invention can reduce number of connectors, so can reduce the use cost of circuit component.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the circuit diagram of the signal-testing apparatus of one embodiment of the invention;
Fig. 2 is the circuit diagram of the logical block of one embodiment of the invention.
Main element symbol description in the accompanying drawing:
The 100-signal-testing apparatus; The 110-connector;
120-complex programmable logic device chip; The 130-logical block;
The 121-first control pin; The 122-second control pin;
R1, R2-resistance; SW1, SW2-switch;
The V1-voltage source.
Embodiment
Fig. 1 is the circuit diagram of the signal-testing apparatus of one embodiment of the invention.Please refer to Fig. 1, signal-testing apparatus 100 comprises connector 110, complex programmable logic device (complexprogrammable logic device) chip 120 and logical block 130.
Connector 110 has a plurality of pins.Complex programmable logic device chip 120 has many group test signal pins, the first control pin 121 and the second control pin 122, the first control pin 121 receives first logical signal, the second control pin 122 receives second logical signal, complex programmable logic device chip 120 can be according to first logical signal and described second logical signal, and, carry out signal testing with test signal to the connector 110 of exporting a correspondence with described many group test signal pins one group of a plurality of pin that are connected to connector 110 wherein.Logical block 130 connects the first control pin 121 and the second control pin 122, in order to produce first logical signal and second logical signal.
In the present embodiment, many group test signal pins can comprise the test signal pin of complex programmable logic device chip 120, central processing unit (central processing unit, CPU) test signal pin, platform controller hub (Platform Controller Hub, PCH) test signal pin, network interface controller (Network Interface Controller, NIC) test signal pin, and complex programmable logic device chip 120 just can be according to the logic state of first logical signal and second logical signal, and the corresponding test signal pin with above-mentioned is connected to connector 110, so that the output test signal is tested.In addition, above-mentioned test signal for example can be joint working group (joint test action group, JTAG) signal.
In addition, complex programmable logic device chip 120 can according to the corresponding relation of the logic state of first logical signal shown in the table 1 and second logical signal and test signal pin with organize more wherein one group of test signal pin corresponding be connected to connector 110.
The logic state of table 1 first logical signal and second logical signal and the corresponding relation of test signal pin
| First logical signal | Second logical signal | The test signal pin |
| 0 | 0 | Central processing unit |
| 0 | 1 | The platform controller hub |
| 1 | 0 | Network interface controller |
| 1 | 1 | The complex programmable logic device chip |
As shown in table 1, when the logic state of first logical signal and second logical signal all was low level " 0 ", complex programmable logic device chip 120 can be connected to connector 110 with the test signal pin of central processing unit; When the logic state of first logical signal is the logic state of the low level " 0 " and second logical signal when being high level " 1 ", complex programmable logic device chip 120 can be connected to connector 110 with the test signal pin of platform controller hub; When the logic state of first logical signal is the logic state of the high level " 1 " and second logical signal when being low level " 0 ", complex programmable logic device chip 120 can be connected to connector 110 with the test signal pin of network interface controller; When the logic state of first logical signal and second logical signal all was high level " 1 ", complex programmable logic device chip 120 can be connected to connector 110 with the test signal pin of complex programmable logic device chip 120.Above-mentioned table 1 only is one embodiment of the present invention, and also visual its demand of user is adjusted the logic state of first logical signal and second logical signal and the corresponding relation of test signal pin voluntarily, is not giving unnecessary details at this.
By above-mentioned table 1 as can be known, the signal-testing apparatus 100 of present embodiment can utilize the logic state of first logical signal and second logical signal, connecting different test signal pins is connected on the connector 110, test with signal different elements, thus, the use cost of circuit component (connector) can be reduced, and the risk that test result confidence level that heavy industry causes descends can be reduced.
Fig. 2 is the circuit diagram of the logical block of one embodiment of the invention.Please refer to Fig. 2, logical block 130 comprises resistance R 1, R2 and switch SW 1, SW2.Second end that first end of resistance R 1 connects the first control pin 121, resistance R 1 is connected to voltage source V 1 (for example being P3V3STBY).First end of switch SW 1 is connected to first end of resistance R 1, and second end of switch SW 1 is held with being connected to.
First end of resistance R 2 is connected to the second control pin 122, and second end of resistance R 2 is connected to voltage source V 1.First end of switch SW 2 is connected to first end of resistance R 2, and second end of switch SW 2 is held with being connected to.
In the present embodiment, logical block 130 is switched on or switched off by switch SW 1, SW2's, to produce logic level as first logical signal and second logical signal of table 1, and complex programmable logic device chip 120 can be according to the logic level of first logical signal and second logical signal, and the test signal pin of correspondence is connected to connector 110, to carry out the test of signal.
In sum, complex programmable logic device chip of the present invention is according to first logical signal of logical block generation and the logic state of second logical signal, and the corresponding test signal pin with different is connected to a plurality of pins of connector, tests with the output test signal.Thus, signal-testing apparatus can be under the situation of not doing any hardware heavy industry (rework), the test signal of different test signal pins is connected to connector arbitrarily tests, to reduce the risk that the test result confidence level descends.In addition, signal-testing apparatus of the present invention can reduce number of connectors, so can reduce the use cost of circuit component.
Though the present invention discloses as above with embodiment; yet it is not in order to limit the present invention; those of ordinary skill under any in the technical field; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (4)
1. a signal-testing apparatus is characterized in that, comprising:
A connector has a plurality of pins;
One complex programmable logic device chip, have many group test signal pins, one first control pin and one second control pin, the described first control pin receives one first logical signal, the described second control pin receives one second logical signal, described complex programmable logic device chip is according to the logic state of described first logical signal and described second logical signal, and with described many group test signal pins one group of a plurality of pin that connect described connector wherein, to export a test signal to described connector, to test; And
One logical block connects described first control pin and the described second control pin, in order to produce described first logical signal and described second logical signal.
2. signal-testing apparatus according to claim 1 is characterized in that, described logical block comprises:
One first resistance, its first end connect the described first control pin, and its second end is connected to a voltage source;
One first switch, its first end connects first end of described first resistance, and its second end is held with being connected to;
One second resistance, its first end connect the described second control pin, and its second end is connected to this voltage source; And
One second switch, its first end connects first end of described second resistance, and its second end is held with being connected to.
3. signal-testing apparatus according to claim 1, it is characterized in that described many group test signal pins comprise the test signal pin of described complex programmable logic device chip, test signal pin, platform controller hub test signal pin and the network interface controller test signal pin of central processing unit.
4. signal-testing apparatus according to claim 1 is characterized in that, described test signal is a joint test working group signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101565167A CN102213743A (en) | 2010-04-01 | 2010-04-01 | Signal test device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101565167A CN102213743A (en) | 2010-04-01 | 2010-04-01 | Signal test device |
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|---|---|
| CN102213743A true CN102213743A (en) | 2011-10-12 |
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| CN2010101565167A Pending CN102213743A (en) | 2010-04-01 | 2010-04-01 | Signal test device |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103197225A (en) * | 2012-01-06 | 2013-07-10 | 珠海天威技术开发有限公司 | Testing method of single bus chip |
| CN104298575A (en) * | 2013-07-16 | 2015-01-21 | 鸿富锦精密电子(天津)有限公司 | Mainboard debugging circuit |
| CN105426337A (en) * | 2015-10-29 | 2016-03-23 | 上海飞斯信息科技有限公司 | Universal processing module |
| CN105842615A (en) * | 2015-01-14 | 2016-08-10 | 扬智科技股份有限公司 | System chip capable of being debugged in abnormal state, and debugging method thereof |
| CN106940424A (en) * | 2016-01-05 | 2017-07-11 | 德律科技股份有限公司 | Multiple cases test device and its test signal conveyer |
| CN108804261A (en) * | 2017-05-05 | 2018-11-13 | 中兴通讯股份有限公司 | The test method and device of connector |
| CN108984354A (en) * | 2018-06-27 | 2018-12-11 | 郑州云海信息技术有限公司 | A kind of server chips debug circuit, adjustment method and server |
| CN112463467A (en) * | 2019-09-09 | 2021-03-09 | 英业达科技有限公司 | Automated integrated test system and method thereof |
| CN114325320A (en) * | 2021-12-27 | 2022-04-12 | 展讯通信（上海）有限公司 | Signal generating device and chip reliability testing system |
-
2010
- 2010-04-01 CN CN2010101565167A patent/CN102213743A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103197225A (en) * | 2012-01-06 | 2013-07-10 | 珠海天威技术开发有限公司 | Testing method of single bus chip |
| CN104298575A (en) * | 2013-07-16 | 2015-01-21 | 鸿富锦精密电子(天津)有限公司 | Mainboard debugging circuit |
| CN104298575B (en) * | 2013-07-16 | 2018-08-03 | 鸿富锦精密电子(天津)有限公司 | Mainboard debug circuit |
| CN105842615B (en) * | 2015-01-14 | 2019-03-05 | 扬智科技股份有限公司 | The System on Chip/SoC and its adjustment method that can be debugged under abnormality |
| CN105842615A (en) * | 2015-01-14 | 2016-08-10 | 扬智科技股份有限公司 | System chip capable of being debugged in abnormal state, and debugging method thereof |
| CN105426337A (en) * | 2015-10-29 | 2016-03-23 | 上海飞斯信息科技有限公司 | Universal processing module |
| CN106940424B (en) * | 2016-01-05 | 2020-02-07 | 德律科技股份有限公司 | Multi-chassis testing device and testing signal transmission device thereof |
| CN106940424A (en) * | 2016-01-05 | 2017-07-11 | 德律科技股份有限公司 | Multiple cases test device and its test signal conveyer |
| CN108804261A (en) * | 2017-05-05 | 2018-11-13 | 中兴通讯股份有限公司 | The test method and device of connector |
| CN108804261B (en) * | 2017-05-05 | 2023-05-19 | 中兴通讯股份有限公司 | Connector testing method and device |
| CN108984354A (en) * | 2018-06-27 | 2018-12-11 | 郑州云海信息技术有限公司 | A kind of server chips debug circuit, adjustment method and server |
| CN112463467A (en) * | 2019-09-09 | 2021-03-09 | 英业达科技有限公司 | Automated integrated test system and method thereof |
| CN114325320A (en) * | 2021-12-27 | 2022-04-12 | 展讯通信（上海）有限公司 | Signal generating device and chip reliability testing system |
| CN114325320B (en) * | 2021-12-27 | 2024-06-07 | 展讯通信（上海）有限公司 | Signal generating device and chip reliability test system |
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Application publication date: 20111012 |