201206112 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係關於一種測試電路，尤指一種用於測試網路介 面的測試電路。 【先前技術】 - [0002] 隨著通訊技術的發展，乙太網已普遍應用在各個領域， 而RJ45作為最常見的網路介面在電腦上得到了廣泛的應 用，目前應用RJ45網路介面傳輸的乙太網標準為 10Base-T、100Base-TX、1000Base-T。為保證RJ45 f 介面發送的乙太網訊號的品質，必須對其傳輸的訊號進 行訊號完整性測量，然而習知的測試裝置在測試過程中 需要手動的插換示波器和測試裝置，該種測試方式不但 佔用大量測試時間而且可能由於人為原因會造成測量結 果的不準確。 【發明内容】 [0003] 鑒於以上内容，有必要提供一種自動的網路介面測試電 路，以提高網路介面的測試準確度及測試效率。 [0004] 一種網路介面測試電路用於測試一電子設備的網路介面 ，該網路介面測試電路包括一連接器、兩探棒、一微控 制器、一高速開關晶片、第一至第三開關晶片、一匯流 排開關晶片及一第一負載板，該連接器用於連接該電子 設備上的網路介面，該探棒用於連接至一測量儀器上， 該微控制器的第一輸出引腳連接該高速開關晶片的一控 制引腳，該高速開關晶片的第一至第七輸入引腳分別對 應連接該連接器上的引腳，該高速開關晶片的第一及第 099125415 表單編號A0101 第4頁/共19頁 0992044645-0 201206112 二輸出引腳分別連接該第一開關晶片的兩輸入引腳，該 〇 第一及第二開關晶片的兩控制引腳均連接該微控制器的 第二輸出引腳，該第一及第二開關晶片的第一至第四開 關引腳均連接至該第一負載板上，該第二開關晶片的兩 輸出引腳分別連接該第三開關晶片的第一及第二輸入引 腳，該第三開關晶片的兩控制引腳連接該微控制器的第 三輸出引腳，該第三開關晶片的兩輸出引腳分別連接探 棒，該匯流排開關晶片的第一至第三輸入引腳分別連接 該微控制器的第四至第六輸出引腳，該匯流排開關晶片 的第一至第六輸出引腳均連接至該第一負載板上，該匯 流排開關的接地引腳接地，該微控制器及該高速開關晶 片分別輸出控制訊號控制該第一及第二開關及該匯流排 開關晶片選擇性的導通，以將該第一負載板上的不同負 載接入該網路介面測試電路，該微控制器透過該第二開 關晶片輸出控制訊號控制該第三開關晶片導通以將測試 結果透過一測量儀器顯示。 〇 [_5] 相較習知技術，該網路介面測試電路可以方便的對電子 設備上的網路介面的傳輸標準的訊號進行自動測試，而 不需要手動插換示波器和測試電路，方便了測試人員， 節省了測試時間，提高了測試效率。 [0006] 【實施方式】 請參考圖1及圖2，本發明網路介面測試電路100用於測試 一電子設備（如一電腦主機板）的網路介面。該網路介 面測試電路100的較佳實施方式包括一連接器10、兩探棒 40、一微控制器U1、一高速開關晶片U2、開關晶片 099125415 表單編號A0101 第5頁/共19頁 0992044645-0 201206112 113-118、一匯流排開關晶片1]9、兩負載板20及30、一開 關ΚΙ、電阻IU-IU3、電容Cl及C2及複數發光二極體，如 十個發光二極體D1-D10。該連接器10用於連接該電腦主 機板上的網路介面，該探棒40用於連接至一測量儀器（ 如示波器）上。在本實施方式中，該開關K1為一按鈕開 關，該微控制器U1的型號為MK7A20P，該高速開關晶片 U2的型號為MAX4892E，該開關晶片U3-U8的型號為 FSA22 67，該匯流排開關晶片U9的型號為 SN74CBTLV3125。該負載板20上設置第一至第六負載 U-L6，該第一至第六負載L1-L6的大小可以根據測試的 需要進行選擇。該負載板30上設置一第七負載L7，該第 七負載L7為一電阻。 [0007] 該微控制器U1的輸出引腳PC0連接該高速開關晶片U2的控 制引腳SEL，該高速開關晶片U2的輸入引腳A1-A7分別對 應連接該連接器10上的引腳，該高速開關晶片U2的電壓 引腳VCC連接一電壓源VCC1。該高速開關晶片U2的輸出 引腳0B1、1B1分別連接該開關晶片U3的輸入引腳2A、1A ，該開關晶片U3的控制引腳IS、2S均連接該微控制器的 輸出引腳PC1，該開關晶片U3的開關引腳1B0、2B0分別 連接該第一至第三負載L1-L3的兩端，該開關引腳1B1、 2B1分別連接該第四至第六負載L4-L6的兩端。該開關晶 片U4的控制引腳IS、2S連接該微控制器U1的輸出引腳 PC1，其開關引腳1B0、2B0分別連接該第一至第三負載 U-L3的兩端，其開關引腳1B1、2B1分別連接該第四至 第六負載L4-L6的兩端，其輸出引腳ΙΑ、2A分別連接該 099125415 表單編號A0101 第6頁/共19頁 0992044645-0 201206112 開關晶片U8的輸入引腳iB〇、2B〇，該開關晶片U8的控制 引腳IS、2S連接該微控制器耵的輸出引腳PC4，其輸出 引腳1A、2A分別連接探棒40。該高速開關晶片U2的輸出 引腳0B2、1B2、2B2、3B2分別連接該開關晶>| U5的輸入 引腳1B0、2B0、1B1、2B1，該開關晶片U5的控制引腳 - IS、2S均連接該微控制器U1的輸出引腳PC2，其輸出引 - 腳ΙΑ、2A分別連接該開關晶片U7的輸入引腳1B0 ' 2B0， 該開關晶片U7的控制引腳連接該微控制器U1的輸出引腳 PC3，其輸出引腳ΙΑ、2A連接該負載L7的兩端及連接該 開關晶片U8的輸出引腳iBl、2B1。該高速開關晶片U2的 輸出引腳4B2、5B2、6B2、7B2分別連接該開關晶片U6的 輸入引腳1B0、2B0、1B1、2B1，該開關晶片U6的控制引 腳IS、2S均連接該微控制器U1的輸出引腳PC2，其輸出 弓1腳ΙΑ、2A分別連接該開關晶片U7的輪入引腳1B1、2B1 ◊該開關晶片\J3-U8的電壓引腳均連接該電壓源VCC1，201206112 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a test circuit, and more particularly to a test circuit for testing a network interface. [Prior Art] - [0002] With the development of communication technology, Ethernet has been widely used in various fields, and RJ45 has been widely used as the most common network interface on computers. Currently, RJ45 network interface is used for transmission. The Ethernet standard is 10Base-T, 100Base-TX, and 1000Base-T. In order to ensure the quality of the Ethernet signal sent by the RJ45 f interface, the signal integrity measurement must be performed on the transmitted signal. However, the conventional test device needs to manually insert the oscilloscope and the test device during the test. Not only does it take up a lot of testing time, but it can cause inaccuracies in measurement results due to human factors. SUMMARY OF THE INVENTION [0003] In view of the above, it is necessary to provide an automatic network interface test circuit to improve the test accuracy and test efficiency of the network interface. [0004] A network interface test circuit is used to test a network interface of an electronic device, the network interface test circuit includes a connector, two probes, a microcontroller, a high speed switch chip, first to third a switch chip, a bus switch chip and a first load board, wherein the connector is used to connect to a network interface on the electronic device, the probe is used for connecting to a measuring instrument, and the first output of the microcontroller is The pin is connected to a control pin of the high-speed switch chip, and the first to seventh input pins of the high-speed switch chip are respectively connected to the pin on the connector, and the first and the 099125415 form number A0101 of the high-speed switch chip 4 pages/total 19 pages 0992044645-0 201206112 Two output pins are respectively connected to the two input pins of the first switch chip, and the two control pins of the first and second switch chips are connected to the second of the microcontroller An output pin, the first to fourth switch pins of the first and second switch chips are connected to the first load board, and the two output pins of the second switch chip are respectively connected to the third switch chip The first and second input pins, the two control pins of the third switch chip are connected to the third output pin of the microcontroller, and the two output pins of the third switch chip are respectively connected to the probe, the bus bar The first to third input pins of the switch chip are respectively connected to the fourth to sixth output pins of the microcontroller, and the first to sixth output pins of the bus bar switch chip are connected to the first load board The grounding pin of the bus bar switch is grounded, and the microcontroller and the high-speed switch chip respectively output control signals to control selective conduction of the first and second switches and the bus bar switch chip to the first load board The different loads are connected to the network interface test circuit, and the microcontroller controls the third switch chip to be turned on by the second switch chip output control signal to display the test result through a measuring instrument. 〇[_5] Compared with the prior art, the network interface test circuit can automatically test the signal of the transmission standard of the network interface on the electronic device without manual insertion of the oscilloscope and the test circuit, which facilitates the test. Staff, saving test time and improving test efficiency. [0006] Referring to FIG. 1 and FIG. 2, the network interface test circuit 100 of the present invention is used to test a network interface of an electronic device such as a computer motherboard. A preferred embodiment of the network interface test circuit 100 includes a connector 10, two probes 40, a microcontroller U1, a high speed switch chip U2, a switch chip 099125415, a form number A0101, page 5, a total of 19 pages 0992044645- 0 201206112 113-118, a bus switch chip 1]9, two load boards 20 and 30, a switch ΚΙ, a resistor IU-IU3, capacitors C1 and C2, and a plurality of light-emitting diodes, such as ten light-emitting diodes D1 -D10. The connector 10 is for connecting to a network interface on the computer main board, and the probe 40 is for connecting to a measuring instrument such as an oscilloscope. In this embodiment, the switch K1 is a push button switch, the model of the microcontroller U1 is MK7A20P, the model of the high speed switch chip U2 is MAX4892E, and the model of the switch chip U3-U8 is FSA22 67, the bus bar switch The model number of the chip U9 is SN74CBTLV3125. The load board 20 is provided with first to sixth loads U-L6, and the sizes of the first to sixth loads L1-L6 can be selected according to the needs of the test. A seventh load L7 is disposed on the load board 30, and the seventh load L7 is a resistor. The output pin PC0 of the microcontroller U1 is connected to the control pin SEL of the high-speed switch chip U2, and the input pins A1-A7 of the high-speed switch chip U2 are respectively connected to the pins on the connector 10. The voltage pin VCC of the high speed switch chip U2 is connected to a voltage source VCC1. The output pins 0B1 and 1B1 of the high-speed switch chip U2 are respectively connected to the input pins 2A and 1A of the switch chip U3, and the control pins IS and 2S of the switch chip U3 are connected to the output pin PC1 of the microcontroller. The switch pins 1B0, 2B0 of the switch wafer U3 are respectively connected to both ends of the first to third loads L1 - L3, and the switch pins 1B1, 2B1 are respectively connected to both ends of the fourth to sixth loads L4 - L6. The control pins IS, 2S of the switch chip U4 are connected to the output pin PC1 of the microcontroller U1, and the switch pins 1B0, 2B0 are respectively connected to the two ends of the first to third loads U-L3, and the switch pins thereof 1B1 and 2B1 are respectively connected to the two ends of the fourth to sixth loads L4-L6, and the output pins ΙΑ and 2A are respectively connected to the 099125415. Form No. A0101 Page 6/19 pages 0992044645-0 201206112 Input of the switch chip U8 The pins iB〇 and 2B〇, the control pins IS and 2S of the switch chip U8 are connected to the output pin PC4 of the microcontroller, and the output pins 1A and 2A are connected to the probe 40, respectively. The output pins 0B2, 1B2, 2B2, and 3B2 of the high-speed switch chip U2 are respectively connected to the input pins 1B0, 2B0, 1B1, and 2B1 of the switch crystal U1, and the control pins of the switch chip U5 are - IS and 2S. The output pin PC2 of the microcontroller U1 is connected, and the output pin-pin 2A is connected to the input pin 1B0 ' 2B0 of the switch chip U7, and the control pin of the switch chip U7 is connected to the output of the microcontroller U1. The pin PC3 has its output pins ΙΑ and 2A connected to both ends of the load L7 and output pins iB1 and 2B1 connected to the switch chip U8. The output pins 4B2, 5B2, 6B2, and 7B2 of the high-speed switch chip U2 are respectively connected to the input pins 1B0, 2B0, 1B1, and 2B1 of the switch chip U6, and the control pins IS and 2S of the switch chip U6 are connected to the micro control. The output pin PC2 of the U1 is connected to the wheel pins 1B1 and 2B1 of the switch chip U7, and the voltage pins of the switch chip \J3-U8 are connected to the voltage source VCC1.
其接地引腳均接地。該匯流排開關晶片D9的電壓引腳連 接該電壓源VCC1，其輸入引腳10E-30E分別連接該微控 〇 制器ΙΠ的輸出引腳PC5、PC6、PC7，其輸出引腳ΙΑ、1B 分別連接該第一至第六負載L1-L6的兩端，其輸出引腳2A 、2B分別連接該第一至第六負載L卜L6的兩端，其輸出引 腳3A ' 3B分別連接該第一至第六負載L卜L6的兩端，該 匯流排開關晶片U9的接地引腳GND接地。該微控制器U1的 輸出引腳PB6經該開關K〗接地及經該電阻ri連接該電壓源 VCC1，該微控制器U1的電壓引腳reSETB經該電阻R3連接 該電壓源VCC1，其時鐘引腳0SC1經該電阻R2連接該電壓 源代(：1，該電容C1串接在該微控制器ui的時鐘引腳0SC1 099125415 表單編號A0101 第7頁/共19頁 0992044645-0 201206112 與地之間，該微控制器μ的電壓引腳VDD連接該電壓源 VCC1，該電容C2串接在該微控制器Η的電壓引腳與 地之間，該微控制器U1的接地引腳VSS接地。該微控制器 U1的輸出引腳ρΑ0-ρΑ3、ΡΒ0_ΡΒ5*別經該等電阻 R4-R13連接對應該等發光二極體D1_D1〇的陽極，該等發 光二極體D1-D10的陰極均接地。 [0008] 本實施方式中以RJ45網路介面為例進行說明。因為RJ45 網路介面可以傳輸的乙太網標準為l〇Base-T， 100Base TX，l〇〇〇Base_T三種，雨'其中傳輸的乙太網 標準為100Base-TX友l〇〇〇Base-T的輸出訊號相同。因 此’需要對該兩組傳輸的乙太網標準的訊號分別進行訊 號完整性測試。 [0009] 首先以傳輸的乙太網標準為1 OBase-Τ為例進行測試原理 說明。 [0010] 測試時，將該網路介面測誠電路1〇 〇:透過該連接器1 〇連接 到該電腦主機板的網路介面上，將該網路介面測試電路 . ： · 100透過該探棒40連接到該示波器上。首先按下按鈕開關 K1使該網路介面測試電路1〇〇啟動，當該微控制器耵的輸 出引腳PC0輸出一低電平訊號給該高速開關晶片μ的控制 引腳SEL時，該高速開關晶片U2的輸出引腳0B1及1B1與 該開關晶片U3的輸入引腳ία及2A連接導通，同時該微控 制器U1的輸出引腳PC1輸出一低電平訊號給該兩開關晶片 U3及U4的控制引腳is與2S，則該兩開關晶片U3及U4的輸 出引腳1B0與2B0連接導通並連接至該負載板20上，當該 微控制器U1的輸出引腳PC5輸出一低電平訊號給該匯流排 099125415 表單編號A0101 第8頁/共19頁 0992044645-0 201206112 開關晶片U9的輸入引腳10E，而輸出引腳PC6、PC7分別 輸出高電平訊號給該匯流排開關晶片U 9的輸入引腳2 0 E、Its ground pin is grounded. The voltage pin of the bus bar switch chip D9 is connected to the voltage source VCC1, and the input pins 10E-30E are respectively connected to the output pins PC5, PC6, PC7 of the micro control controller, and the output pins ΙΑ, 1B respectively Connecting the two ends of the first to sixth loads L1 - L6 , the output pins 2A , 2B are respectively connected to the two ends of the first to sixth loads L b L6 , and the output pins 3A ' 3B are respectively connected to the first To the both ends of the sixth load Lb L6, the ground pin GND of the bus bar switch wafer U9 is grounded. The output pin PB6 of the microcontroller U1 is grounded via the switch K and connected to the voltage source VCC1 via the resistor ri. The voltage pin reSETB of the microcontroller U1 is connected to the voltage source VCC1 via the resistor R3. The pin 0SC1 is connected to the voltage source generation via the resistor R2 (:1, the capacitor C1 is serially connected to the clock pin of the microcontroller ui, 0SC1 099125415, form number A0101, page 7 / 19 pages 0992044645-0 201206112, and ground The voltage pin VDD of the microcontroller μ is connected to the voltage source VCC1, and the capacitor C2 is connected in series between the voltage pin of the microcontroller and the ground, and the ground pin VSS of the microcontroller U1 is grounded. The output pins ρΑ0-ρΑ3 and ΡΒ0_ΡΒ5* of the microcontroller U1 are connected to the anodes corresponding to the light-emitting diodes D1_D1〇 via the resistors R4-R13, and the cathodes of the light-emitting diodes D1-D10 are grounded. In this embodiment, the RJ45 network interface is taken as an example for description. Because the RJ45 network interface can transmit Ethernet standards of l〇Base-T, 100Base TX, and l〇〇〇Base_T, the rain transmits Ethernet standard is 100Base-TX friend l〇〇〇Base-T output signal phase Therefore, it is necessary to perform signal integrity testing on the signals transmitted by the two groups of Ethernet standards. [0009] Firstly, the test principle is described by taking the Ethernet standard of transmission as 1 OBase-Τ as an example. [0010] During the test, the network interface test circuit is connected to the network interface of the computer motherboard through the connector 1 ,, and the network interface test circuit is: 100 connected through the probe 40 To the oscilloscope, first press the button switch K1 to enable the network interface test circuit 1 ,, when the output pin PC0 of the microcontroller 输出 outputs a low level signal to the control pin of the high speed switch chip μ In the case of SEL, the output pins 0B1 and 1B1 of the high-speed switch chip U2 are connected to the input pins ία and 2A of the switch chip U3, and the output pin PC1 of the microcontroller U1 outputs a low-level signal to the two. The control pins is and 2S of the switch wafers U3 and U4, the output pins 1B0 and 2B0 of the two switch chips U3 and U4 are connected to be connected and connected to the load board 20, when the output pin PC5 of the microcontroller U1 is Output a low level signal to the bus 099125415 Form No. A0101 Page 8 of 19 0992044645-0 201206112 Switching chip U9 input pin 10E, while output pins PC6, PC7 output high level signals to the input pin 2 of the bus bar switch chip U 9 0 E,
[0011] 099125415 30E時，該匯流排開關晶片U9的輸出引腳1A與1B連接導 通，此時該負載板20上的第一負載L1被接入進行第一次 測試，此時該開關晶片U8的輸入引腳1B0、2B0與該開關 晶片U4的輸出引腳ΙΑ、2A連接導通，該微控制器U1的輸 出引腳PC4輸出一低電平訊號給該開關晶片U8的控制引腳 IS、2S，該開關晶片U8的輸出引腳ΙΑ、2A透過該探棒40 將透過該第一負載的訊號顯示在該示波器上，以便測試 人員判斷測試結果。當第一次測試完成後，該微控制器 U1的輸出引腳PC6輸出一低電平訊號給該匯流排開關晶片 U9的輸入引腳20E，而輸出引腳PC5、PC7分別輸出高電 平訊號給該匯流排開關晶片U9的輸入引腳10E、30E，此 時該匯流排開關晶片U9的輸出引腳2A與2B連接導通，該 負載板20上的第二負載L2被接入進行測試。當該微控制 器U1的輸出引腳PC7輸出一低電平訊號給該匯流排開關晶 片U9的輸入引腳30E，而輸出引腳PC5、PC6分別輸出高 電平訊號給該匯流排開關晶片U9的輸入引腳10E、20E， 此時該匯流排開關晶片U 9的輪出引腳3 A與3 B連接導通， 該負載板20上的第三負載L3被接入進行測試。[0011] At 099125415 30E, the output pins 1A and 1B of the bus bar switch chip U9 are connected to be turned on. At this time, the first load L1 on the load board 20 is connected for the first test. At this time, the switch chip U8 The input pins 1B0 and 2B0 are connected to the output pins ΙΑ and 2A of the switch chip U4, and the output pin PC4 of the microcontroller U1 outputs a low-level signal to the control pins IS and 2S of the switch chip U8. The output pins ΙΑ, 2A of the switch chip U8 are displayed on the oscilloscope through the probe 40 to transmit the signal through the first load, so that the tester can judge the test result. After the first test is completed, the output pin PC6 of the microcontroller U1 outputs a low level signal to the input pin 20E of the bus bar switch chip U9, and the output pins PC5 and PC7 respectively output a high level signal. The input pins 10E, 30E of the bus bar switch chip U9 are connected to the output pins 2A and 2B of the bus bar switch chip U9, and the second load L2 on the load board 20 is connected for testing. When the output pin PC7 of the microcontroller U1 outputs a low level signal to the input pin 30E of the bus bar switch chip U9, the output pins PC5 and PC6 respectively output a high level signal to the bus bar switch chip U9. The input pins 10E, 20E, at this time, the turn-out pins 3 A and 3 B of the bus bar switch chip U 9 are connected to be turned on, and the third load L3 on the load board 20 is connected for testing.
當前面的測試完成後，該微控制器U1的輸出引腳PC1輸出 一高電平訊號給該兩開關晶片U3、U4的控制引腳IS、2S ，該兩開關晶片U3及U4的輸出引腳1B1與2B1連接導通並 連接到該負載板20上，該微控制器U1的輸出引腳PC5輸出 一低電平訊號給該匯流排開關晶片U9的輸入引腳10E，而 表單編號A0101 第9頁/共19頁 0992044645-0 201206112 輸出引腳PC6、PC7分別輸出高電平訊號給該匯流排開關 晶片U9的輸入引腳20E、30E，此時該匯流排開關晶片U9 的輸出引腳1A與1B連接導通，該負載板20上的第四負載 L4被接入進行測試。當該微控制器U1的輸出引腳PC6輸出 一低電平訊號給該匯流排開關晶片U9的輸入引腳20E，而 輸出引腳PC5、PC7分別輸出南電平訊號給該匯流排開關 晶片U9的輸入引腳10E、30E，該匯流排開關晶片U9的輸 出引腳2A與2B連接導通，該負載板20上的第五負載L5被 接入進行測試。當該微控制器U1的輸出引腳PC7輸出一低 電平訊號給該匯流排開關晶片U9的輸入引腳30E，而輸出 引腳P C 5、P C 6分別輸出雨電平訊號給該匯流排開關晶片 U9的輸入引腳10E、20E，此時該匯流排開關晶片U9的輸 出引腳3A與3B連接導通，該負載板20上的第六負載被接 入進行測試。當該負載板2 0上的六種負載L6均被接入測 試完成後，則該網路介面測試電路對透過該網路介面的 傳輸速率為1 OBase-Τ的訊號完整性測試完成。 [0012] 當該網路介面測試電路100需要對透過該網路介面的傳輸 的乙太網標準為1 OOBase-Τ及100OBase-T進行測試時， 只需使該微控制器U1的輸出引腳PC0輸出一高電平訊號給 該高速開關晶片U2的控制引腳SEL，即可實現自動將該網 路介面測試電路1 0 0切換到對傳輸的乙太網標準為 100Base-T及1 000Base-T的訊號進行測試。當該微控制 器U1的輸出引腳PC2輸出一低電平訊號給該兩開關晶片U5 、U6的控制引腳IS、2S時，該高速開關晶片U2的輸出引 腳0B2、1B2分別與該開關晶片U5的1B0、2B0連接導通， 099125415 表單編號A0101 第10頁/共19頁 0992044645-0 201206112 該高速開關晶片U2的輸出引腳4Β2、5Β2分別與該開關晶 片U6的輸入引腳1B0、2B0連接導通，當該微控制器U1的 輸出弓丨腳P C 3輸出一低電平給該開關晶片U 7的控制引腳1 S 、2S時，該開關晶片U7的輸入引腳1B0與2B0連接導通’ 其輸出引腳1A、2A連接至該第七負載L7上並與該開關晶 片U8的輸入引腳1B1、2B1連接導通，該微控制器U1的输 出引腳PC4輸出一低電平訊號給該開關晶片U8的控制引腳 IS、2S，該開關晶片U8的輸出引腳ΙΑ、2A透過該探棒 將透過該第七負載L7的訊號顯示在該示波器上，以便測 Ο [0013] 試人員判斷測試結果》 - ........ .... 當該微控制器U1的輸出引腳PC2輸出一高電平訊號給該兩 開關晶片U5、U6的控制引腳3S、2S時:，該高速開關晶片 U2的輸出引腳2B2、3B2分別與該開關晶片ϋ5的1B1、 ❹ 2Β1連接導通，該高速開關晶片μ的輸出引腳6Β2、7Β2 分別與該開關晶片U6的輸入引娜1Β1、2Β1連接導通，當 該微控制器U1的輸出引腳PC3輸出一低電平給該開關晶片 U7的控制引腳1S、含S時，該開闕晶片U7的輸入引腳1Β0 與2Β0連接導通，其輸出引腳1Α、2Α連接至該第七負載 L7並與該開關晶片U8的輸入引腳1Β1、2Β1連接導通，該 微控制器U1的輸出引腳PC4輸出一低電平訊號給該開關晶 片U8的控制引腳iS、2S，該開關晶片U8的輸出引腳1Α、 2Α透過该探棒4〇將透過該第七負載L7的訊號顯示在該示 波器上，以便測試人員判斷測試結果。 當該微控制器U1的輸出引腳pc2輸出一低電平訊號給該兩 開關晶片U5、ϋ6的控制引腳IS、2S時，該高速開關晶片 099125415 表單編號Α0101 第11頁/共19頁 0992044645-0 [0014] 201206112 U2的輸出引腳0B2、1B2分別與該開關晶片U5的1B0、 2B0連接導通，該高速開關晶片U2的輸出引腳4B2、5B2 分別與該開關晶片U6的輸入引腳1B0、2B0連接導通，當 該微控制器U1的輸出引腳PC3輸出一高電平給該開關晶片 U7的控制引腳IS、2S時，該開關晶片U7的輸入引腳1B1 與2B1連接導通，其輸出引腳ΙΑ、2A連接至該第七負載 L7並與該開關晶片U8的輸入引腳1B1、2B1連接導通，該 微控制器U1的輸出引腳PC4輸出一低電平訊號給該開關晶 片U8的控制引腳IS、2S，該開關晶片U8的輸出引腳1A、 2A透過該探棒40將透過該第七負載L7的訊號顯示在該示 波器上，以便測試人員判斷測軾緯果Λ [0015] [0016] 當該微控制器U1的輸出引聊—高電平訊號給該兩 開關晶片U5、U6的控制引腳IS、2S時，該高速開關晶片 U2的輸出引腳2B2、3B2分別與該兩開關晶片U5的1B1、 2B1連接導通，該高速開關晶片U2的輸出引腳6B2、4B2 分別與該開關晶片U6的輸入引腳1B1、2Βί連接導通，當 該微控制器U1的輸出引腳PC3輸出一高電平給該開關晶片 U7的控制引腳is、2S時，該開關晶片U7的輸入引腳1Β1 與2Β1連接導通，其輸出引腳ια、2Α連接至該第七負載 L7並與該開關晶片U8的輸入引腳1Β1、2Β1連接導通，該 微控制器U1的輸出引腳PC4輸出一低電平訊號給該開關晶 片U8的控制引腳is、2S，該開關晶片U8的輸出引腳1Α、 2Α透過該探棒4〇將透過該第七負載L7的訊號顯示在該示 波器上’以便測試人員判斷測試結果。 本實施方式中’因為傳輸的乙太網標準為l〇Base_T的測 099125415 表單編號A0101 第12頁/共19頁 0992044645-0 201206112 試需要對該負載板20上的負載L1-L6進行六次負載狀態測 試’而傳輸的乙太網標準為100Base-TX及1 000Base-T 的測試需要對負載板30上的負載L7進行四次負載狀態測 試’因此’採用十個發光二極體D1_D1〇對每一負載狀態 測試進行顯示’當測試透過時，則一發光二極體亮，否 則不亮。在每一測試完成時，該微控制器耵控制一發光 二極體的亮或滅。 〇 [0017] [0018] 該網路介面賴電物0相方便的對料縣機板上的 網路介面的不同傳輪的乙太網標準的的訊號進行自動測 β ’而不需要手動插換示波器和測試電路，方便了測試 人員，節省了測試時問，植Λ 1美两了測試效率。同時亦可透 過該發光二極體的亮或、、ώ Α >' 次减很容易嘴觀察到測:試狀態。 综上所述，本發明符合發 申請。惟，以上所述者僅广要件’*依法提出專利 熟悉本案技藝之人士，在:本發明之較佳實施例，舉凡 飾或變化，皆應涵蓋心==神㈣之等效修 ❹ 【主要元件符號說明】 [0020] 網路介面測試電路：1 〇 ^ [0021] 連接器：10 【圖式簡單說明】 [0019] 圖1及圖2為本發明網 原理圖。 範圍内 路介面測試電路的 較佳實施方式的 [0022] 探棒：40 [0023] 微控制器：U1 099125415 表單編號Α0101 第13百 貝/共19頁 0992044645-0 201206112 [0024] 高速開關晶片：U2 [0025] 開關晶片：U3-U8 [0026] 匯流排開關晶片：U9 [0027] 負載板：20、30 [0028] 開關：K1 [0029] 電阻：R1-R13 [0030] 電容：Cl、C2 [0031] 發光二極體：D卜D10 [0032] 負载：U-L7 [0033] 電壓源：VCC1 0992044645-0 099125415 表單編號A0101 第14頁/共19頁After the previous test is completed, the output pin PC1 of the microcontroller U1 outputs a high level signal to the control pins IS, 2S of the two switch chips U3, U4, and the output pins of the two switch chips U3 and U4. 1B1 and 2B1 are connected and connected to the load board 20. The output pin PC5 of the microcontroller U1 outputs a low level signal to the input pin 10E of the bus switch chip U9, and the form number A0101 is page 9. / 19 pages 0992044645-0 201206112 Output pins PC6, PC7 respectively output a high level signal to the input pins 20E, 30E of the bus switch chip U9, at this time the output pins 1A and 1B of the bus switch chip U9 The connection is turned on, and the fourth load L4 on the load board 20 is connected for testing. When the output pin PC6 of the microcontroller U1 outputs a low level signal to the input pin 20E of the bus bar switch chip U9, the output pins PC5 and PC7 respectively output a south level signal to the bus bar switch chip U9. The input pins 10E, 30E of the bus bar switch chip U9 are connected to the output pins 2A and 2B, and the fifth load L5 on the load board 20 is connected for testing. When the output pin PC7 of the microcontroller U1 outputs a low level signal to the input pin 30E of the bus bar switch chip U9, the output pins PC 5 and PC 6 respectively output a rain level signal to the bus bar switch. The input pins 10E and 20E of the chip U9 are connected to the output pins 3A and 3B of the bus bar switch chip U9, and the sixth load on the load board 20 is connected for testing. After the six loads L6 on the load board 20 are all tested by the access test, the network interface test circuit completes the signal integrity test with a transmission rate of 1 OBase-Τ through the network interface. [0012] When the network interface test circuit 100 needs to test the Ethernet standard of 100 Mbps-100 and 100-OBase-T through the network interface, only the output pin of the microcontroller U1 is required. PC0 outputs a high level signal to the control pin SEL of the high speed switch chip U2, which can automatically switch the network interface test circuit 100 to the Ethernet standard of 100Base-T and 1 000Base for transmission. The signal of T is tested. When the output pin PC2 of the microcontroller U1 outputs a low level signal to the control pins IS and 2S of the two switch chips U5 and U6, the output pins 0B2 and 1B2 of the high speed switch chip U2 and the switch respectively 1B0, 2B0 of the wafer U5 are connected to be turned on, 099125415 Form No. A0101 Page 10/19 pages 0992044645-0 201206112 The output pins 4Β2, 5Β2 of the high-speed switch chip U2 are respectively connected to the input pins 1B0, 2B0 of the switch wafer U6. Turning on, when the output pin PC 3 of the microcontroller U1 outputs a low level to the control pins 1 S and 2S of the switch chip U 7 , the input pins 1B0 and 2B0 of the switch chip U7 are connected to conduct ' The output pins 1A and 2A are connected to the seventh load L7 and connected to the input pins 1B1 and 2B1 of the switch chip U8. The output pin PC4 of the microcontroller U1 outputs a low level signal to the switch. The control pins IS, 2S of the chip U8, the output pins ΙΑ, 2A of the switch chip U8 are displayed on the oscilloscope through the probe through the probe to detect the test [0013] Result" - ........ .... when the microcontroller When the output pin PC2 of U1 outputs a high level signal to the control pins 3S and 2S of the two switch chips U5 and U6: the output pins 2B2 and 3B2 of the high speed switch chip U2 and the 1B1 of the switch chip ϋ5, respectively ❹ 2Β1 connection is turned on, and the output pins 6Β2 and 7Β2 of the high-speed switch wafer μ are respectively connected to the input terminals 1Β1 and 2Β1 of the switch chip U6, and when the output pin PC3 of the microcontroller U1 outputs a low level, When the control pin 1S of the switch chip U7 is included, the input pins 1Β0 and 2Β0 of the open chip U7 are connected to be turned on, and the output pins 1Α, 2Α are connected to the seventh load L7 and the switch chip U8. The input pins 1Β1 and 2Β1 are connected to be turned on. The output pin PC4 of the microcontroller U1 outputs a low level signal to the control pins iS and 2S of the switch chip U8. The output pins of the switch chip U8 are 1Α, 2Α. The signal transmitted through the seventh load L7 is displayed on the oscilloscope through the probe 4 to allow the tester to judge the test result. When the output pin pc2 of the microcontroller U1 outputs a low level signal to the control pins IS, 2S of the two switch chips U5, ϋ6, the high speed switch chip 099125415 form number Α 0101 page 11 / 19 pages 0992044645 -0 [0014] 201206112 U2 output pins 0B2, 1B2 are respectively connected to 1B0, 2B0 of the switch chip U5, the output pins 4B2, 5B2 of the high-speed switch chip U2 and the input pin 1B0 of the switch chip U6 The 2B0 connection is turned on. When the output pin PC3 of the microcontroller U1 outputs a high level to the control pins IS and 2S of the switch chip U7, the input pins 1B1 and 2B1 of the switch chip U7 are connected to be turned on. The output pin ΙΑ, 2A is connected to the seventh load L7 and is connected to the input pins 1B1 and 2B1 of the switch chip U8. The output pin PC4 of the microcontroller U1 outputs a low level signal to the switch chip U8. Control pins IS, 2S, the output pins 1A, 2A of the switch chip U8 are displayed on the oscilloscope through the probe 40 through the probe 40, so that the tester can determine the measured 轼 Λ [0015 [0016] When the output of the microcontroller U1 is cited - When the high level signal is applied to the control pins IS, 2S of the two switch chips U5, U6, the output pins 2B2, 3B2 of the high speed switch chip U2 are respectively connected to the 1B1, 2B1 of the two switch wafers U5, and the high speed is connected. The output pins 6B2 and 4B2 of the switch chip U2 are respectively connected to the input pins 1B1 and 2B of the switch chip U6, and when the output pin PC3 of the microcontroller U1 outputs a high level to the control of the switch chip U7. When the feet are 2S, the input pins 1Β1 and 2Β1 of the switch chip U7 are connected to be turned on, and the output pins ια, 2Α are connected to the seventh load L7 and connected to the input pins 1Β1 and 2Β1 of the switch chip U8. The output pin PC4 of the microcontroller U1 outputs a low level signal to the control pins is, 2S of the switch chip U8, and the output pins 1Α, 2Α of the switch chip U8 pass through the probe 4 The signal of the seven-load L7 is displayed on the oscilloscope' so that the tester can judge the test result. In the present embodiment, 'the Ethernet standard of the transmission is l〇Base_T. 099125415 Form No. A0101 Page 12/19 pages 0992044645-0 201206112 It is necessary to perform six loads on the load L1-L6 on the load board 20. The state test's transmission of the Ethernet standard 100Base-TX and 1 000Base-T requires four load state tests on the load L7 on the load board 30. Therefore, ten LEDs D1_D1 are used. A load status test is performed to display 'When the test passes, one of the LEDs is lit, otherwise it is not lit. At the completion of each test, the microcontroller controls the illumination of a light-emitting diode. 〇[0017] [0018] The network interface is easy to automatically measure the signal of the Ethernet interface of different transmissions on the network interface of the county board without the need for manual insertion. Changing the oscilloscope and test circuit facilitates the tester, saves the test time, and the planting efficiency is better. At the same time, it is also easy to observe the test state by the light or the ώ Α > In summary, the present invention is in compliance with the application. However, the above-mentioned ones only have a wide range of '* legally patented persons who are familiar with the art of the present invention. In the preferred embodiment of the present invention, the equivalent of the heart==God (4) should be covered. [0020] Network interface test circuit: 1 〇 ^ [0021] Connector: 10 [Simple diagram of the drawing] [0019] FIG. 1 and FIG. 2 are schematic diagrams of the network of the present invention. [0022] Detector: 40 [0023] Microcontroller: U1 099125415 Form No. 101 0101 13th Beck / Total 19 Page 0992044645-0 201206112 [0024] High Speed Switching Wafer: U2 [0025] Switching wafer: U3-U8 [0026] Busbar switch wafer: U9 [0027] Load board: 20, 30 [0028] Switch: K1 [0029] Resistance: R1-R13 [0030] Capacitance: Cl, C2 [0031] Light Emitting Diode: D Bu D10 [0032] Load: U-L7 [0033] Voltage Source: VCC1 0992044645-0 099125415 Form No. A0101 Page 14 of 19