TWI483234B - Pixel of a display panel and driving method thereof - Google Patents

Pixel of a display panel and driving method thereof Download PDF

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Publication number
TWI483234B
TWI483234B TW102109309A TW102109309A TWI483234B TW I483234 B TWI483234 B TW I483234B TW 102109309 A TW102109309 A TW 102109309A TW 102109309 A TW102109309 A TW 102109309A TW I483234 B TWI483234 B TW I483234B
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transistor
voltage
coupled
capacitor
signal
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TW102109309A
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Chinese (zh)
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TW201435837A (en
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Chun Chieh Lin
Ya Ling Chen
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Au Optronics Corp
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Priority to TW102109309A priority Critical patent/TWI483234B/en
Priority to CN201310174969.6A priority patent/CN103400544B/en
Priority to US13/928,394 priority patent/US9177505B2/en
Publication of TW201435837A publication Critical patent/TW201435837A/en
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Publication of TWI483234B publication Critical patent/TWI483234B/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Description

顯示面板之畫素及其驅動方法Display panel pixel and driving method thereof

本發明係相關於一種顯示面板之畫素及其驅動方法，尤指一種可補償電性特性差異之顯示面板之畫素及其驅動方法。The present invention relates to a pixel of a display panel and a driving method thereof, and more particularly to a pixel of a display panel capable of compensating for differences in electrical characteristics and a driving method thereof.

有機發光二極體顯示面板係一種利用有機發光二極體畫素發光以顯示畫面的顯示裝置。有機發光二極體的亮度係正比於流經有機發光二極體的電流大小。一般而言，為了控制流經有機發光二極體的電流大小，有機發光二極體畫素會包含電流控制開關，用以根據其閘極端之顯示電壓控制流經有機發光二極體的電流大小，進而控制有機發光二極體的亮度。The organic light emitting diode display panel is a display device that emits light using an organic light emitting diode to display a picture. The brightness of the organic light emitting diode is proportional to the amount of current flowing through the organic light emitting diode. In general, in order to control the current flowing through the organic light-emitting diode, the organic light-emitting diode includes a current control switch for controlling the current flowing through the organic light-emitting diode according to the display voltage of the gate terminal thereof. In turn, the brightness of the organic light-emitting diode is controlled.

然而，每一有機發光二極體畫素之電流控制開關的臨界電壓會有差異，再者，有機發光二極體的老化也會造成有機發光二極體的跨電壓發生變化，上述電流控制開關及有機發光二極體的電性特性差異會影響有機發光二極體的顯示亮度。習知有機發光二極體顯示裝置容易受到電流控制開關及有機發光二極體的電性特性差異之影響，造成顯示畫面之品質變差。However, the threshold voltage of the current-controlled switch of each organic light-emitting diode pixel may be different. Furthermore, the aging of the organic light-emitting diode may also cause a change in the voltage across the organic light-emitting diode. The current control switch The difference in electrical characteristics of the organic light-emitting diode affects the display brightness of the organic light-emitting diode. The conventional organic light-emitting diode display device is susceptible to the difference in electrical characteristics of the current control switch and the organic light-emitting diode, resulting in deterioration of the quality of the display screen.

本發明之目的在於提供一種可補償電性特性差異之顯示面板之畫素及其驅動方法，以解決先前技術的問題。SUMMARY OF THE INVENTION An object of the present invention is to provide a pixel of a display panel capable of compensating for differences in electrical characteristics and a driving method thereof to solve the problems of the prior art.

本發明顯示面板之畫素包含第一電晶體，其第一端耦接於資料線，控制端耦接於掃描線用以接收掃描訊號；第二電晶體，其第一端耦接於第一電壓源，控制端耦接於該第一電晶體之第二端；第三電晶體，其第一端耦接於該第二電晶體之第二端，控制端用以接收控制訊號；發光單元，其第一端耦接於該第二電晶體之第二端，第二端耦接於第二電壓源；第一電容，其第一端耦接於該第一電晶體之第二端，第二端耦接於該第三電晶體之第二端；及第二電容，其第一端耦接於該第一電容之第二端，第二端耦接於該第二電壓源。The pixel of the display panel of the present invention comprises a first transistor, the first end of which is coupled to the data line, the control end is coupled to the scan line for receiving the scan signal, and the second transistor is coupled to the first end of the second transistor. a voltage source, the control end is coupled to the second end of the first transistor; the third transistor has a first end coupled to the second end of the second transistor, the control end is configured to receive the control signal; The first end is coupled to the second end of the second transistor, the second end is coupled to the second voltage source, and the first end is coupled to the second end of the first transistor. The second end is coupled to the second end of the third transistor; and the second end is coupled to the second end of the first capacitor, and the second end is coupled to the second voltage source.

本發明顯示面板之畫素驅動方法包含提供一顯示面板，該顯示面板包含複數條掃描線，複數條資料線及複數個畫素，每一畫素包含第一電晶體，第二電晶體，第三電晶體，發光單元，第一電容，及一第二電容，該第一電晶體之第一端耦接於該些資料線之一資料線，該第一電晶體之控制端耦接於該些掃描線之一掃描線用以接收掃描訊號，該第二電晶體之第一端耦接於第一電壓源，該第二電晶體之控制端耦接於該第一電晶體之第二端，該第三電晶體之第一端耦接於該第二電晶體之第二端，該第三電晶體之控制端用以接收控制訊號，該發光單元之第一端耦接於該第二電晶體之第二端，該發光單元之第二端耦接於一第二電壓源，該第一電容之第一端耦接於該第一電晶體之第二端，該第一電容之第二端耦接於該第三電晶體之第二端，該第二電容之第一端耦接於該第一電容之第二端，該第二電容之第二端耦接於該第二電壓源；於一掃描時段內開啟該第一電晶體；於該掃描時段之第一子時段中，該第一電晶體之第一端接收第一電壓訊號，以重置該第一電容及該第二電容之電壓；於該掃描時段之第二子時段中，該第一電晶體之第一端接收相異於該第一電壓訊號之第二電壓訊號，以寫入補償電壓於該第一電容之第二 端；於該掃描時段之第三子時段中，該第一電晶體之第一端接收一顯示電壓訊號，以根據該補償電壓對該顯示電壓訊號進行補償；及於該掃描時段後關閉該第一電晶體。The pixel driving method of the display panel of the present invention comprises providing a display panel, the display panel comprising a plurality of scanning lines, a plurality of data lines and a plurality of pixels, each pixel comprising a first transistor, a second transistor, a third transistor, a light emitting unit, a first capacitor, and a second capacitor, wherein the first end of the first transistor is coupled to one of the data lines, and the control end of the first transistor is coupled to the One of the scan lines is configured to receive the scan signal, the first end of the second transistor is coupled to the first voltage source, and the control end of the second transistor is coupled to the second end of the first transistor The first end of the third transistor is coupled to the second end of the second transistor, and the control end of the third transistor is configured to receive a control signal, and the first end of the light emitting unit is coupled to the second end The second end of the first unit is coupled to a second voltage source, the first end of the first capacitor is coupled to the second end of the first transistor, and the first capacitor is The second end is coupled to the second end of the third transistor, and the first end of the second capacitor is coupled a second end of the second capacitor, the second end of the second capacitor is coupled to the second voltage source; the first transistor is turned on during a scan period; and in the first sub-period of the scan period, the The first end of the first transistor receives the first voltage signal to reset the voltage of the first capacitor and the second capacitor; in the second sub-period of the scanning period, the first end of the first transistor receives Different from the second voltage signal of the first voltage signal to write the compensation voltage to the second of the first capacitor The first end of the first transistor receives a display voltage signal to compensate the display voltage signal according to the compensation voltage; and closes the first time after the scanning period A transistor.

相較於先前技術，本發明顯示面板之畫素及其驅動方法可有效地補償電流控制開關及有機發光二極體的電性特性差異。因此，本發明顯示面板之畫面品質不會受到電流控制開關及有機發光二極體的電性特性差異之影響，進而改善顯示畫面之品質。Compared with the prior art, the pixel of the display panel of the present invention and the driving method thereof can effectively compensate for the difference in electrical characteristics between the current control switch and the organic light emitting diode. Therefore, the picture quality of the display panel of the present invention is not affected by the difference in electrical characteristics of the current control switch and the organic light emitting diode, thereby improving the quality of the display screen.

100‧‧‧顯示面板100‧‧‧ display panel

110‧‧‧畫素110‧‧‧ pixels

120‧‧‧發光單元120‧‧‧Lighting unit

C1‧‧‧第一電容C1‧‧‧first capacitor

C2‧‧‧第二電容C2‧‧‧second capacitor

N1‧‧‧第一N型電晶體N1‧‧‧First N-type transistor

N2‧‧‧第二N型電晶體N2‧‧‧Second N-type transistor

N3‧‧‧第三N型電晶體N3‧‧‧ Third N-type transistor

P1‧‧‧第一P型電晶體P1‧‧‧First P-type transistor

P2‧‧‧第二P型電晶體P2‧‧‧Second P-type transistor

P3‧‧‧第三P型電晶體P3‧‧‧ Third P-type transistor

D‧‧‧資料線D‧‧‧ data line

G‧‧‧掃描線G‧‧‧ scan line

VDD‧‧‧高位準電壓源VDD‧‧‧ high level voltage source

VSS‧‧‧低位準電壓源VSS‧‧‧low level voltage source

Sc‧‧‧控制訊號Sc‧‧‧ control signal

Sg‧‧‧掃描訊號Sg‧‧‧ scan signal

VD‧‧‧資料線之電壓位準Voltage level of VD‧‧‧ data line

Vh‧‧‧第一電壓訊號Vh‧‧‧First voltage signal

Va‧‧‧第二電壓訊號Va‧‧‧second voltage signal

Vd‧‧‧顯示電壓訊號Vd‧‧‧ shows voltage signal

I‧‧‧電流I‧‧‧current

第1圖為本發明顯示裝置的示意圖。Figure 1 is a schematic view of a display device of the present invention.

第2圖為第1圖顯示裝置的畫素的第一實施例的示意圖。Fig. 2 is a schematic view showing a first embodiment of a pixel of the display device of Fig. 1.

第3圖為本發明畫素之第一實施例的相關訊號的波形示意圖。Fig. 3 is a waveform diagram showing the correlation signal of the first embodiment of the pixel of the present invention.

第4圖為本發明畫素之第一實施例的驅動方法的示意圖。Fig. 4 is a schematic view showing a driving method of the first embodiment of the pixel of the present invention.

第5圖為本發明畫素之第一實施例的驅動方法的示意圖。Fig. 5 is a schematic view showing a driving method of the first embodiment of the pixel of the present invention.

第6圖為本發明畫素之第一實施例的驅動方法的示意圖。Fig. 6 is a schematic view showing a driving method of the first embodiment of the pixel of the present invention.

第7圖為本發明畫素之第一實施例的驅動方法的示意圖。Fig. 7 is a schematic view showing a driving method of the first embodiment of the pixel of the present invention.

第8圖為第1圖顯示裝置的畫素的第二實施例的示意圖。Fig. 8 is a view showing a second embodiment of the pixel of the display device of Fig. 1.

第9圖為本發明畫素之第二實施例的相關訊號的波形示意圖。Figure 9 is a waveform diagram of the correlation signal of the second embodiment of the pixel of the present invention.

第10圖為本發明畫素之第二實施例的驅動方法的示意圖。Figure 10 is a schematic view showing a driving method of a second embodiment of the pixel of the present invention.

第11圖為本發明畫素之第二實施例的驅動方法的示意圖。Figure 11 is a schematic view showing a driving method of a second embodiment of the pixel of the present invention.

第12圖為本發明畫素之第二實施例的驅動方法的示意圖。Figure 12 is a schematic view showing a driving method of a second embodiment of the pixel of the present invention.

第13圖為本發明畫素之第二實施例的驅動方法的示意圖。Figure 13 is a schematic view showing a driving method of the second embodiment of the pixel of the present invention.

請同時參考第1圖及第2圖。第1圖為本發明顯示面板的示 意圖。第2圖為第1圖顯示面板的畫素的第一實施例的示意圖。如圖所示，本發明顯示面板100包含複數條掃描線G，複數條資料線D及複數個畫素110。每一畫素110包含第一電晶體N1，第二電晶體N2，第三電晶體N3，發光單元120，第一電容C1，及第二電容C2。第一電晶體N1之第一端係耦接於資料線D，而第一電晶體N1之控制端係耦接於掃描線G，用以接收掃描訊號Sg。第二電晶體N2之第一端係耦接於高位準電壓源VDD，而第二電晶體N2之控制端係耦接於第一電晶體N1之第二端。第三電晶體N3之第一端係耦接於第二電晶體N2之第二端，而第三電晶體N3之控制端係用以接收一控制訊號Sc。發光單元120之第一端係耦接於第二電晶體N2之第二端，而發光單元120之第二端係耦接於低位準電壓源VSS。第一電容C1之第一端係耦接於第一電晶體N1之第二端，而第一電容C2之第二端係耦接於第三電晶體N3之第二端。第二電容C2之第一端係耦接於第一電容C1之第二端，而第二電容C2之第二端係耦接於第二電壓源VSS。第一電晶體N1、第二電晶體N2及第三電晶體N3係N型電晶體，且第二電晶體N2係電流控制開關。發光單元120可為有機發光二極體，或其他電流驅動型式之發光單元。高位準電壓源VDD之電壓位準係高於低位準電壓源VSS之電壓位準。Please refer to both Figure 1 and Figure 2. Figure 1 is a view of the display panel of the present invention intention. Fig. 2 is a schematic view showing the first embodiment of the panel of the panel of Fig. 1. As shown, the display panel 100 of the present invention includes a plurality of scan lines G, a plurality of data lines D, and a plurality of pixels 110. Each pixel 110 includes a first transistor N1, a second transistor N2, a third transistor N3, a light emitting unit 120, a first capacitor C1, and a second capacitor C2. The first end of the first transistor N1 is coupled to the data line D, and the control end of the first transistor N1 is coupled to the scan line G for receiving the scan signal Sg. The first end of the second transistor N2 is coupled to the high-level voltage source VDD, and the control end of the second transistor N2 is coupled to the second end of the first transistor N1. The first end of the third transistor N3 is coupled to the second end of the second transistor N2, and the control end of the third transistor N3 is configured to receive a control signal Sc. The first end of the light emitting unit 120 is coupled to the second end of the second transistor N2, and the second end of the light emitting unit 120 is coupled to the low level voltage source VSS. The first end of the first capacitor C1 is coupled to the second end of the first transistor N1, and the second end of the first capacitor C2 is coupled to the second end of the third transistor N3. The second end of the second capacitor C2 is coupled to the second end of the first capacitor C1, and the second end of the second capacitor C2 is coupled to the second voltage source VSS. The first transistor N1, the second transistor N2, and the third transistor N3 are N-type transistors, and the second transistor N2 is a current control switch. The light emitting unit 120 can be an organic light emitting diode, or other current driven type of light emitting unit. The voltage level of the high level voltage source VDD is higher than the voltage level of the low level voltage source VSS.

請同時參考第3圖至第7圖。第3圖為本發明畫素之第一實施例的相關訊號的波形示意圖，第4圖至第7圖為本發明畫素之第一實施例的驅動方法的示意圖。如圖所示，當畫素110之第一電晶體N1於掃描時段Ts內被掃描訊號Sg開啟時，於掃描時段Ts之第一子時段T1中，第一電晶體N1之第一端經由資料線D接收第一電壓訊號Vh，且第三電晶體N3被控制訊號Sc開啟，以重置第一電容C1及第二電容C2之電壓位準。第一電容C1之第一端之電壓位準會等於第一電壓訊號Vh之電壓位準，而第二電容C2之第一端之電壓位準會等於低位準電壓源VSS之 電壓位準加上發光單元之跨電壓Voled。Please also refer to Figures 3 through 7. Fig. 3 is a waveform diagram showing the correlation signal of the first embodiment of the pixel of the present invention, and Figs. 4 to 7 are schematic views showing the driving method of the first embodiment of the pixel of the present invention. As shown in the figure, when the first transistor N1 of the pixel 110 is turned on by the scanning signal Sg during the scanning period Ts, in the first sub-period T1 of the scanning period Ts, the first end of the first transistor N1 is via the data. The line D receives the first voltage signal Vh, and the third transistor N3 is turned on by the control signal Sc to reset the voltage levels of the first capacitor C1 and the second capacitor C2. The voltage level of the first terminal of the first capacitor C1 is equal to the voltage level of the first voltage signal Vh, and the voltage level of the first terminal of the second capacitor C2 is equal to the low level voltage source VSS. The voltage level is added to the voltage across the voltage unit Voled.

於掃描時段Ts之第二子時段T2中，第一電晶體N1之第一端經由資料線D接收第二電壓訊號Va(第一電壓訊號Vh之電壓位準係高於第二電壓訊號Va之電壓位準)，且第三電晶體N3被控制訊號Sc開啟，以寫入補償電壓於第一電容C1之第二端。舉例來說，由於第二電壓訊號Va之電壓位準係低於第一電壓訊號Vh之電壓位準，當第一電晶體N1之第一端經由資料線D接收第二電壓訊號Va時，第一電容C1之第一端之電壓位準會從第一電壓訊號Vh之電壓位準下降至第二電壓訊號Va之電壓位準，而第一電容C1之第二端之電壓位準會因電容耦合效應而被下拉，進而造成第二電晶體N2之閘極端和源極端的電壓差Vgs大於第二電晶體N2的臨界電壓Vth。因此第二電容C2會被充電，直到第二電晶體N2之閘極端和源極端的電壓差等於第二電晶體N2的臨界電壓Vth為止，此時第一電容C1之第二端之電壓位準會等於第二電壓訊號Va之電壓位準減去第二電晶體的臨界電壓Vth。In the second sub-period T2 of the scan period Ts, the first end of the first transistor N1 receives the second voltage signal Va via the data line D (the voltage level of the first voltage signal Vh is higher than the second voltage signal Va) The voltage level is turned on, and the third transistor N3 is turned on by the control signal Sc to write the compensation voltage to the second end of the first capacitor C1. For example, when the voltage level of the second voltage signal Va is lower than the voltage level of the first voltage signal Vh, when the first end of the first transistor N1 receives the second voltage signal Va via the data line D, The voltage level of the first terminal of the capacitor C1 drops from the voltage level of the first voltage signal Vh to the voltage level of the second voltage signal Va, and the voltage level of the second terminal of the first capacitor C1 is due to the capacitance. The coupling effect is pulled down, thereby causing the voltage difference Vgs of the gate terminal and the source terminal of the second transistor N2 to be greater than the threshold voltage Vth of the second transistor N2. Therefore, the second capacitor C2 is charged until the voltage difference between the gate terminal and the source terminal of the second transistor N2 is equal to the threshold voltage Vth of the second transistor N2, and the voltage level of the second terminal of the first capacitor C1 is at this time. It will be equal to the voltage level of the second voltage signal Va minus the threshold voltage Vth of the second transistor.

於掃描時段Ts之第三子時段T3中，第一電晶體N1之第一端經由資料線D接收顯示電壓訊號Vd(顯示電壓訊號Vd之電壓位準係介於第一電壓訊號Vh之電壓位準及第二電壓訊號Va之電壓位準之間)，且第三電晶體N3被控制訊號Sc關閉，以根據補償電壓對顯示電壓訊號Vd進行補償。舉例來說，由於顯示電壓訊號Vd之電壓位準係高於第二電壓訊號Va之電壓位準，當第一電晶體N1之第一端經由資料線D接收顯示電壓訊號Vd時，第一電容C1之第一端之電壓位準會從第二電壓訊號Va之電壓位準上升至顯示電壓訊號Vd之電壓位準，而第一電容C1之第二端之電壓位準會因電容耦合效應而被上拉，此時第一電容C1之第二端之電壓位準可如以下算式表示：In the third sub-period T3 of the scan period Ts, the first end of the first transistor N1 receives the display voltage signal Vd via the data line D (the voltage level of the display voltage signal Vd is the voltage level of the first voltage signal Vh) The voltage is between the voltage level of the second voltage signal Va, and the third transistor N3 is turned off by the control signal Sc to compensate the display voltage signal Vd according to the compensation voltage. For example, since the voltage level of the display voltage signal Vd is higher than the voltage level of the second voltage signal Va, when the first end of the first transistor N1 receives the display voltage signal Vd via the data line D, the first capacitor The voltage level at the first end of C1 rises from the voltage level of the second voltage signal Va to the voltage level of the display voltage signal Vd, and the voltage level of the second end of the first capacitor C1 is due to the capacitive coupling effect. When it is pulled up, the voltage level of the second end of the first capacitor C1 can be expressed as follows:

V2=Va-Vth+c1(Vd-Va)/(c1+c2) 算式(1)V2=Va-Vth+c1(Vd-Va)/(c1+c2) Equation (1)

其中c1為第一電容C1之電容值，c2為第二電容C2之電容值。Where c1 is the capacitance value of the first capacitor C1, and c2 is the capacitance value of the second capacitor C2.

於掃描時段Ts之後，第一電晶體N1被關閉，且第三電晶體N3被控制訊號Sc開啟，以使第二電晶體N2根據補償後之顯示電壓訊號提供電流I至發光單元120，以使發光單元120發光。舉例來說，當第三電晶體N3被控制訊號Sc開啟時，第一電容C1之第二端之電壓位準會被上拉以等於低位準電壓源VSS之電壓位準加上發光單元之跨電壓VoLed，而第一電容C1之第一端之電壓位準會因電容耦合效應而被上拉，此時第一電容C1之第一端之電壓位準可如以下算式表示：V1=Vd+(VSS+Voled)-[Va-Vth+c1(Vd-Va)/(c1+c2)] 算式(2)After the scanning period Ts, the first transistor N1 is turned off, and the third transistor N3 is turned on by the control signal Sc, so that the second transistor N2 supplies the current I to the light emitting unit 120 according to the compensated display voltage signal, so that The light emitting unit 120 emits light. For example, when the third transistor N3 is turned on by the control signal Sc, the voltage level of the second terminal of the first capacitor C1 is pulled up to be equal to the voltage level of the low level voltage source VSS plus the cross section of the light emitting unit. The voltage VoLed, and the voltage level of the first end of the first capacitor C1 is pulled up due to the capacitive coupling effect. At this time, the voltage level of the first end of the first capacitor C1 can be expressed by the following formula: V1=Vd+( VSS+Voled)-[Va-Vth+c1(Vd-Va)/(c1+c2)] Equation (2)

而流經第二電晶體之電流值可如以下算式表示：I=K(Vgs-Vth)2 =K[V1-(VSS+Voled)-Vth]2 算式(3)The current value flowing through the second transistor can be expressed by the following formula: I=K(Vgs-Vth) 2 =K[V1-(VSS+Voled)-Vth] 2 Equation (3)

其中K為常數。另外，根據算式(2)及算式(3)，流經第二電晶體之電流值可另用以下算式表示：I=K[(1-c1/(c1+c2))(Vd-Va)]2 算式(4)Where K is a constant. In addition, according to the formula (2) and the formula (3), the current value flowing through the second transistor can be expressed by the following formula: I=K[(1-c1/(c1+c2))(Vd-Va)] 2 formula (4)

依據上述配置，流經第二電晶體N2之電流值不再和第二電晶體N2的臨界電壓及發光單元120的跨電壓相關。本發明顯示面板100只需控制第二電壓訊號Va及顯示電壓訊號Vd之電壓位準，即可準確地控制發光單元120的亮度。因此，本發明顯示面板100的畫素亮度不會受到電流控制開關及有機發光二極體的電性特性差異之影響。According to the above configuration, the current value flowing through the second transistor N2 is no longer related to the threshold voltage of the second transistor N2 and the voltage across the light-emitting unit 120. The display panel 100 can accurately control the brightness of the light emitting unit 120 by simply controlling the voltage levels of the second voltage signal Va and the display voltage signal Vd. Therefore, the pixel brightness of the display panel 100 of the present invention is not affected by the difference in electrical characteristics of the current control switch and the organic light emitting diode.

請參考第8圖。第8圖為第1圖顯示面板的畫素的第二實施例的示意圖。如第8圖所示，每一畫素110包含第一電晶體P1，第二電晶體P2，第三電晶體P3，發光單元120，第一電容C1，及第二電容C2。第一電晶體P1之第一端係耦接於資料線D，而第一電晶體P1之控制端係耦接於掃描線G，用以接收掃描訊號Sg。第二電晶體P2之第一端係耦接於低位準電壓源Vss，而第二電晶體P2之控制端係耦接於第一電晶體P1之第二端。第三電晶體P3之第一端係耦接於第二電晶體P2之第二端，而第三電晶體P3之控制端係用以接收控制訊號Sc。發光單元120之第一端係耦接於第二電晶體P2之第二端，而發光單元120之第二端係耦接於高位準電壓源VDD。第一電容C1之第一端係耦接於第一電晶體P1之第二端，而第一電容C2之第二端係耦接於第三電晶體P3之第二端。第二電容C2之第一端係耦接於第一電容C1之第二端，而第二電容C2之第二端係耦接於高位準電壓源VDD。第一電晶體P1、第二電晶體P2及第三電晶體P3係P型電晶體，且第二電晶體P2係電流控制開關。發光單元120可為有機發光二極體，或其他電流驅動型式之發光單元。高位準電壓源VDD之電壓位準係高於低位準電壓源VSS之電壓位準。Please refer to Figure 8. Figure 8 is a schematic view showing a second embodiment of the pixel of the panel of Figure 1. As shown in FIG. 8, each pixel 110 includes a first transistor P1, a second transistor P2, a third transistor P3, a light emitting unit 120, a first capacitor C1, and a second capacitor C2. The first end of the first transistor P1 is coupled to the data line D, and the control end of the first transistor P1 is coupled to the scan line G for receiving the scan signal Sg. The first end of the second transistor P2 is coupled to the low-level voltage source Vss, and the control end of the second transistor P2 is coupled to the second end of the first transistor P1. The first end of the third transistor P3 is coupled to the second end of the second transistor P2, and the control end of the third transistor P3 is configured to receive the control signal Sc. The first end of the light emitting unit 120 is coupled to the second end of the second transistor P2, and the second end of the light emitting unit 120 is coupled to the high level voltage source VDD. The first end of the first capacitor C1 is coupled to the second end of the first transistor P1, and the second end of the first capacitor C2 is coupled to the second end of the third transistor P3. The first end of the second capacitor C2 is coupled to the second end of the first capacitor C1, and the second end of the second capacitor C2 is coupled to the high level voltage source VDD. The first transistor P1, the second transistor P2, and the third transistor P3 are P-type transistors, and the second transistor P2 is a current control switch. The light emitting unit 120 can be an organic light emitting diode, or other current driven type of light emitting unit. The voltage level of the high level voltage source VDD is higher than the voltage level of the low level voltage source VSS.

請同時參考第9圖至第13圖。第9圖為本發明畫素之第二實施例的相關訊號的波形示意圖，第10圖至第13圖為本發明畫素之第二實施例的驅動方法的示意圖。如圖所示，當畫素110之第一電晶體 P1於掃描時段Ts內被掃描訊號Sg開啟時，於掃描時段Ts之第一子時段T1中，第一電晶體P1之第一端經由資料線D接收第一電壓訊號Vh，且第三電晶體P3被控制訊號Sc開啟，以重置第一電容C1及第二電容C2之電壓位準。第一電容C1之第一端之電壓位準會等於第一電壓訊號Vh之電壓位準，而第二電容C2之第一端之電壓位準會等於高位準電壓源VDD之電壓位準減去發光單元之跨電壓Voled。Please also refer to Figures 9 to 13. Fig. 9 is a waveform diagram showing the correlation signal of the second embodiment of the pixel of the present invention, and Figs. 10 to 13 are diagrams showing the driving method of the second embodiment of the pixel of the present invention. As shown, when the first transistor of pixel 110 When P1 is turned on by the scanning signal Sg in the scanning period Ts, in the first sub-period T1 of the scanning period Ts, the first end of the first transistor P1 receives the first voltage signal Vh via the data line D, and the third transistor P3 is turned on by the control signal Sc to reset the voltage levels of the first capacitor C1 and the second capacitor C2. The voltage level of the first terminal of the first capacitor C1 is equal to the voltage level of the first voltage signal Vh, and the voltage level of the first terminal of the second capacitor C2 is equal to the voltage level of the high level voltage source VDD minus The voltage across the voltage unit is Voled.

於掃描時段Ts之第二子時段T2中，第一電晶體P1之第一端經由資料線D接收第二電壓訊號Va(第一電壓訊號Vh之電壓位準係低於第二電壓訊號Va之電壓位準)，且第三電晶體P3被控制訊號Sc開啟，以寫入補償電壓於第一電容C1之第二端。舉例來說，由於第二電壓訊號Va之電壓位準係高於第一電壓訊號Vh之電壓位準，當第一電晶體P1之第一端經由資料線D接收第二電壓訊號Va時，第一電容C1之第一端之電壓位準會從第一電壓訊號Vh之電壓位準上升至第二電壓訊號Va之電壓位準，而第一電容C1之第二端之電壓位準會因電容耦合效應而被上拉，進而造成第二電晶體P2之源極端和閘極端的電壓差Vsg大於第二電晶體P2的臨界電壓。因此第一電容C1會被放電，直到第二電晶體P2之源極端和閘極端的電壓差Vsg等於第二電晶體P2的臨界電壓Vth為止，此時第一電容C1之第二端之電壓位準會等於第二電壓訊號Va之電壓位準加上第二電晶體的臨界電壓Vth。In the second sub-period T2 of the scan period Ts, the first end of the first transistor P1 receives the second voltage signal Va via the data line D (the voltage level of the first voltage signal Vh is lower than the second voltage signal Va) The voltage level is turned on, and the third transistor P3 is turned on by the control signal Sc to write the compensation voltage to the second end of the first capacitor C1. For example, when the voltage level of the second voltage signal Va is higher than the voltage level of the first voltage signal Vh, when the first end of the first transistor P1 receives the second voltage signal Va via the data line D, The voltage level of the first terminal of the capacitor C1 rises from the voltage level of the first voltage signal Vh to the voltage level of the second voltage signal Va, and the voltage level of the second terminal of the first capacitor C1 is due to the capacitance. The coupling effect is pulled up, thereby causing the voltage difference Vsg of the source terminal and the gate terminal of the second transistor P2 to be greater than the threshold voltage of the second transistor P2. Therefore, the first capacitor C1 is discharged until the voltage difference Vsg between the source terminal and the gate terminal of the second transistor P2 is equal to the threshold voltage Vth of the second transistor P2, and the voltage level of the second terminal of the first capacitor C1 is at this time. The criterion is equal to the voltage level of the second voltage signal Va plus the threshold voltage Vth of the second transistor.

於掃描時段Ts之第三子時段T3中，第一電晶體P1之第一端經由資料線D接收顯示電壓訊號Vd(顯示電壓訊號Vd之電壓位準係介於第一電壓訊號Vh之電壓位準及第二電壓訊號Va之電壓位準之間)，且第三電晶體P3被控制訊號Sc關閉，以根據補償電壓對顯示電壓訊號Vd進行補償。舉例來說，由於顯示電壓訊號Vd之電壓位準係低於第二電壓 訊號Va之電壓位準，當第一電晶體P1之第一端經由資料線D接收顯示電壓訊號Vd時，第一電容C1之第一端之電壓位準會從第二電壓訊號Va之電壓位準下降至顯示電壓訊號Vd之電壓位準，而第一電容C1之第二端之電壓位準會因電容耦合效應而被下拉，此時第一電容C1之第二端之電壓位準可如以下算式表示：V2=Va+Vth-c1(Va-Vd)/(c1+c2) 算式(5)In the third sub-period T3 of the scanning period Ts, the first end of the first transistor P1 receives the display voltage signal Vd via the data line D (the voltage level of the display voltage signal Vd is the voltage level of the first voltage signal Vh) The voltage is between the voltage level of the second voltage signal Va, and the third transistor P3 is turned off by the control signal Sc to compensate the display voltage signal Vd according to the compensation voltage. For example, since the voltage level of the display voltage signal Vd is lower than the second voltage The voltage level of the signal Va, when the first end of the first transistor P1 receives the display voltage signal Vd via the data line D, the voltage level of the first end of the first capacitor C1 is from the voltage level of the second voltage signal Va The voltage level of the second terminal of the first capacitor C1 is pulled down due to the capacitive coupling effect, and the voltage level of the second terminal of the first capacitor C1 can be as follows. The following formula is expressed as: V2=Va+Vth-c1(Va-Vd)/(c1+c2) Equation (5)

於掃描時段Sc之後，第一電晶體P1被關閉，且第三電晶體P3被控制訊號Sc開啟，以使第二電晶體P2根據補償後之顯示電壓訊號Vd提供電流至發光單元120，以使發光單元120發光。舉例來說，當第三電晶體P3被控制訊號Sc開啟時，第一電容C1之第二端之電壓位準會被上拉以等於高位準電壓源VDD之電壓位準減去發光單元之跨電壓Voled，而第一電容C1之第一端之電壓位準會因電容耦合效應而被上拉，此時第一電容C1之第一端之電壓位準可如以下算式表示：V1=Vd+(VDD-Voled)-[Va+Vth-c1(Va-Vd)/(c1+c2)] 算式(6)After the scanning period Sc, the first transistor P1 is turned off, and the third transistor P3 is turned on by the control signal Sc, so that the second transistor P2 supplies current to the light emitting unit 120 according to the compensated display voltage signal Vd, so that The light emitting unit 120 emits light. For example, when the third transistor P3 is turned on by the control signal Sc, the voltage level of the second terminal of the first capacitor C1 is pulled up to be equal to the voltage level of the high level voltage source VDD minus the cross section of the light emitting unit. The voltage is Voled, and the voltage level of the first end of the first capacitor C1 is pulled up due to the capacitive coupling effect. At this time, the voltage level of the first end of the first capacitor C1 can be expressed by the following formula: V1=Vd+( VDD-Voled)-[Va+Vth-c1(Va-Vd)/(c1+c2)] Equation (6)

而流經第二電晶體之電流值可如以下算式表示：I=K(Vsg-Vth)2 =K[(VDD-Voled)-V1-Vth]2 算式(7)The current value flowing through the second transistor can be expressed by the following formula: I=K(Vsg-Vth) 2 =K[(VDD-Voled)-V1-Vth] 2 Equation (7)

其中K為常數。另外，根據算式(6)及算式(7)，流經第二電晶體之電流值可另以以下算式表示： I=K[(1-c1/(c1+c2))(Va-Vd)]2 算式(8)Where K is a constant. In addition, according to the formula (6) and the formula (7), the current value flowing through the second transistor can be expressed by the following formula: I=K[(1-c1/(c1+c2))(Va-Vd)] 2 formula (8)

依據上述配置，流經第二電晶體P2之電流值I不再和第二電晶體P2的臨界電壓Vth及發光單元的跨電壓Voled相關。本發明顯示面板100只需控制第二電壓訊號Va及顯示電壓訊號Vd之電壓位準，即可準確地控制發光單元120的亮度。因此，本發明顯示面板100的畫素亮度不會受到電流控制開關及有機發光二極體的電性特性差異之影響。According to the above configuration, the current value I flowing through the second transistor P2 is no longer related to the threshold voltage Vth of the second transistor P2 and the voltage across the voltage of the light-emitting unit. The display panel 100 can accurately control the brightness of the light emitting unit 120 by simply controlling the voltage levels of the second voltage signal Va and the display voltage signal Vd. Therefore, the pixel brightness of the display panel 100 of the present invention is not affected by the difference in electrical characteristics of the current control switch and the organic light emitting diode.

相較於先前技術，本發明顯示面板之畫素及其驅動方法可有效地補償電流控制開關及有機發光二極體的電性特性差異。因此，本發明顯示面板之畫面品質不會受到電流控制開關及有機發光二極體的電性特性差異之影響，進而改善顯示畫面之品質。Compared with the prior art, the pixel of the display panel of the present invention and the driving method thereof can effectively compensate for the difference in electrical characteristics between the current control switch and the organic light emitting diode. Therefore, the picture quality of the display panel of the present invention is not affected by the difference in electrical characteristics of the current control switch and the organic light emitting diode, thereby improving the quality of the display screen.

110‧‧‧畫素110‧‧‧ pixels

120‧‧‧發光單元120‧‧‧Lighting unit

C1‧‧‧第一電容C1‧‧‧first capacitor

C2‧‧‧第二電容C2‧‧‧second capacitor

N1‧‧‧第一N型電晶體N1‧‧‧First N-type transistor

N2‧‧‧第二N型電晶體N2‧‧‧Second N-type transistor

N3‧‧‧第三N型電晶體N3‧‧‧ Third N-type transistor

D‧‧‧資料線D‧‧‧ data line

G‧‧‧掃描線G‧‧‧ scan line

VDD‧‧‧高位準電壓源VDD‧‧‧ high level voltage source

VSS‧‧‧低位準電壓源VSS‧‧‧low level voltage source

Sc‧‧‧控制訊號Sc‧‧‧ control signal

Claims (11)

一種顯示面板之畫素，包含：一第一電晶體，其第一端耦接於一資料線，控制端耦接於一掃描線用以接收一掃描訊號；一第二電晶體，其第一端耦接於一第一電壓源，控制端耦接於該第一電晶體之第二端；一第三電晶體，其第一端耦接於該第二電晶體之第二端，控制端用以接收一控制訊號；一發光單元，其第一端耦接於該第二電晶體之第二端，第二端耦接於一第二電壓源；一第一電容，其第一端耦接於該第一電晶體之第二端，第二端耦接於該第三電晶體之第二端；及一第二電容，其第一端耦接於該第一電容之第二端，第二端耦接於該第二電壓源。A display panel pixel includes: a first transistor having a first end coupled to a data line, a control end coupled to a scan line for receiving a scan signal, and a second transistor first The end is coupled to a first voltage source, the control end is coupled to the second end of the first transistor; a third transistor is coupled to the second end of the second transistor, the control end The first end is coupled to the second end of the second transistor, the second end is coupled to a second voltage source, and the first end is coupled to the first end. Connected to the second end of the first transistor, the second end is coupled to the second end of the third transistor; and a second capacitor is coupled to the second end of the first capacitor. The second end is coupled to the second voltage source. 如請求項1所述之畫素，其中該第一電晶體係於一掃描時段內被開啟，及於該掃描時段後被關閉，該第一電晶體之第一端係於該掃描時段之一第一子時段接收一第一電壓訊號，於該掃描時段之一第二子時段接收相異於該第一電壓訊號之一第二電壓訊號，及於該掃描時段之一第三子時段接收一顯示電壓訊號。The pixel according to claim 1, wherein the first electro-optic system is turned on during a scanning period and is turned off after the scanning period, and the first end of the first transistor is tied to one of the scanning periods. Receiving a first voltage signal in the first sub-period, receiving a second voltage signal different from the first voltage signal in the second sub-period of the scanning period, and receiving one in the third sub-period of the scanning period Display voltage signal. 如請求項2所述之畫素，其中該第三電晶體係於該第一子時段、該第二子時段及該掃描時段後被該控制訊號開啟，及於該第三子時段被該控制訊號關閉。The pixel of claim 2, wherein the third electro-optic system is turned on by the control signal after the first sub-period, the second sub-period, and the scanning period, and is controlled by the third sub-period The signal is off. 如請求項1所述之畫素，其中該第一電晶體、該第二電晶體及該第三電晶 體係N型電晶體。The pixel according to claim 1, wherein the first transistor, the second transistor, and the third transistor System N-type transistor. 如請求項4所述之畫素，其中該第一電壓源之電壓位準係高於該第二電壓源之電壓位準，且該第一電壓訊號之電壓位準係高於該第二電壓訊號之電壓位準。The pixel of claim 4, wherein the voltage level of the first voltage source is higher than the voltage level of the second voltage source, and the voltage level of the first voltage signal is higher than the second voltage. The voltage level of the signal. 如請求項1所述之畫素，其中該第一電晶體、該第二電晶體及該第三電晶體係P型電晶體。The pixel of claim 1, wherein the first transistor, the second transistor, and the third transistor system P-type transistor. 如請求項6所述之畫素，其中該第一電壓源之電壓位準係低於該第二電壓源之電壓位準，且該第一電壓訊號之電壓位準係低於該第二電壓訊號之電壓位準。The pixel of claim 6, wherein the voltage level of the first voltage source is lower than the voltage level of the second voltage source, and the voltage level of the first voltage signal is lower than the second voltage. The voltage level of the signal. 如請求項1所述之畫素，其中該發光單元係一有機發光二極體。The pixel according to claim 1, wherein the light emitting unit is an organic light emitting diode. 一種顯示面板之畫素驅動方法，包含：提供一顯示面板，該顯示面板包含複數條掃描線，複數條資料線及複數個畫素，每一畫素包含一第一電晶體，一第二電晶體，一第三電晶體，一發光單元，一第一電容，及一第二電容，該第一電晶體之第一端耦接於該些資料線之一資料線，該第一電晶體之控制端耦接於該些掃描線之一掃描線用以接收一掃描訊號，該第二電晶體之第一端耦接於一第一電壓源，該第二電晶體之控制端耦接於該第一電晶體之第二端，該第三電晶體之第一端耦接於該第二電晶體之第二端，該第三電晶體之控制端用以接收一控制訊號，該發光單元之第一端耦接於該第二電晶體之第二端，該發光單元之第二端耦接於一第二電壓源，該第一電容之第一端耦接於該第一電晶體之第二端，該第一電容之第二端耦接 於該第三電晶體之第二端，該第二電容之第一端耦接於該第一電容之第二端，該第二電容之第二端耦接於該第二電壓源；於一掃描時段內開啟該第一電晶體；於該掃描時段之一第一子時段中，該第一電晶體之第一端接收一第一電壓訊號，以重置該第一電容及該第二電容之電壓位準；於該掃描時段之一第二子時段中，該第一電晶體之第一端接收相異於該第一電壓訊號之一第二電壓訊號，以寫入補償電壓於該第一電容之第二端；於該掃描時段之一第三子時段中，該第一電晶體之第一端接收一顯示電壓訊號，以根據該補償電壓對該顯示電壓訊號進行補償；及於該掃描時段後關閉該第一電晶體。A pixel driving method for a display panel, comprising: providing a display panel, the display panel comprising a plurality of scan lines, a plurality of data lines and a plurality of pixels, each pixel comprising a first transistor and a second battery a first transistor, a first transistor, and a second capacitor, the first end of the first transistor being coupled to one of the data lines, the first transistor The control end is coupled to the scan line of the scan lines for receiving a scan signal, the first end of the second transistor is coupled to a first voltage source, and the control end of the second transistor is coupled to the a second end of the first transistor, the first end of the third transistor is coupled to the second end of the second transistor, and the control end of the third transistor is configured to receive a control signal, and the light emitting unit The first end is coupled to the second end of the second transistor, the second end of the light emitting unit is coupled to a second voltage source, and the first end of the first capacitor is coupled to the first transistor At the second end, the second end of the first capacitor is coupled The second end of the second capacitor is coupled to the second end of the first capacitor, and the second end of the second capacitor is coupled to the second voltage source. Turning on the first transistor during a scanning period; in a first sub-period of the scanning period, the first end of the first transistor receives a first voltage signal to reset the first capacitor and the second capacitor a voltage level; in a second sub-period of the scanning period, the first end of the first transistor receives a second voltage signal different from the first voltage signal to write a compensation voltage to the first a second end of the capacitor; in a third sub-period of the scanning period, the first end of the first transistor receives a display voltage signal to compensate the display voltage signal according to the compensation voltage; The first transistor is turned off after the scanning period. 如請求項9所述之畫素驅動方法，另包含：於該掃描時段之該第一子時段中，開啟該第三電晶體；於該掃描時段之該第二子時段中，開啟該第三電晶體；於該掃描時段之該第三子時段中，關閉該第三電晶體；及於該掃描時段後開啟該第三電晶體。The pixel driving method of claim 9, further comprising: turning on the third transistor in the first sub-period of the scanning period; and opening the third in the second sub-period of the scanning period a transistor; in the third sub-period of the scanning period, turning off the third transistor; and turning on the third transistor after the scanning period. 如請求項9所述之畫素驅動方法，另包含：於該掃描時段後該第二電晶體根據該補償後之顯示電壓訊號提供電流至該發光單元，以使該發光單元發光。The pixel driving method of claim 9, further comprising: after the scanning period, the second transistor provides a current to the light emitting unit according to the compensated display voltage signal, so that the light emitting unit emits light.
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CN103400544A (en) 2013-11-20

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