TW201638916A

TW201638916A - Pixel circuit

Info

Publication number: TW201638916A
Application number: TW104112937A
Authority: TW
Inventors: 林永銘; 葉佳元
Original assignee: 友達光電股份有限公司
Priority date: 2015-04-22
Filing date: 2015-04-22
Publication date: 2016-11-01
Also published as: CN104916255A; CN104916255B; TWI560665B

Abstract

A pixel circuit includes a first transistor, a second transistor, a third transistor, a forth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a organic light-emitting diode, each of the transistors includes a first terminal, a second terminal and a control terminal, the control terminal of the fourth transistor is electrically coupled to the first capacitor and the second terminal of the third transistor. When the pixel is operating in a display mode, a voltage level of the first terminal of the third transistor is higher than the voltage level of the control terminal of the fourth transistor to reduce the leakage path effectively.

Description

Pixel circuit

本發明是有關於一種畫素電路，尤其是有關於一種可降低漏電流的畫素電路。 The present invention relates to a pixel circuit, and more particularly to a pixel circuit capable of reducing leakage current.

有機發光二極體(Organic Light Emitting Diode,OLED)顯示裝置較液晶顯示裝置具有可自發光、廣視角、高對比、反應速度快等優點，適合應用於對功率消耗敏感的可攜式電子裝置中。在有機發光二極體顯示裝置中，有機發光二極體係根據流經有機發光二極體的驅動電流來顯示對應之顯示資料，而驅動電流是由畫素單元中的驅動電晶體依照所接收到的資料電壓而產生。因此驅動電晶體之各端點的電壓準位變化會直接影響到顯示畫面。然習知的有機發光二極體顯示裝置之畫素單元由於具有較多的漏電路徑，因此容易造成驅動電晶體所耦接之電壓準位變動，導致畫素單元無法正常顯示顯示資料，因而造成畫面的閃爍。此外，在低更新率(low frame rate)的顯示應用上，傳統的畫素電路會使得畫面閃爍的現象更加明顯。 The organic light emitting diode (OLED) display device has the advantages of self-luminous, wide viewing angle, high contrast, fast response, and the like, and is suitable for use in a portable electronic device sensitive to power consumption. . In the organic light emitting diode display device, the organic light emitting diode system displays corresponding display data according to a driving current flowing through the organic light emitting diode, and the driving current is received by the driving transistor in the pixel unit. The data is generated by the voltage. Therefore, the voltage level change of each end of the driving transistor directly affects the display screen. However, since the pixel unit of the conventional organic light-emitting diode display device has a large leakage path, the voltage level of the driving transistor is easily changed, and the pixel unit cannot display the display data normally, thereby causing The picture flickers. In addition, in the low frame rate display application, the traditional pixel circuit makes the phenomenon of flickering of the picture more obvious.

為了解決上述習知畫素單元具有較多的漏電路徑之缺陷，本發明提出一種畫素電路，根據本發明之一實施例，其包括一第一電晶體，第一電晶體具有一第一端、一第二端以及一控制端，第一電晶體之第一端與一參考電壓電性耦接，第一電晶體之控制端接收一第一控制訊號；一第二電晶體，第二電晶體具有一第一端、一第二端以及一控制端，第二電晶體之第一端與一顯示資料電性耦接，第二電晶體之控制端接收一第二控制訊號，第二電晶體之第二端與第一電晶體之第二端電性耦接；一第一電容，第一電容具有一第一端以及一第二端，第一電容之第一端與第一電晶體之第二端以及第二電晶體之第二端電性耦接；一第三電晶體，第三電晶體其具有一第一端、一第二端以及一控制端，第三電晶體之第一端與第二控制訊號電性耦接，第三電晶體之控制端接收一第三控制訊號，第三電晶體之第二端與第一電容的第二端電性耦接；一第四電晶體，第四電晶體其具有一第一端、一第二端以及一控制端，第四電晶體之第一端與一外部高電壓電性耦接，第四電晶體之控制端與第一電容之第二端電性耦接；第五電晶體，第五電晶體其具有一第一端、一第二端以及一控制端，第五電晶體之第一端與第四電晶體之第二端電性耦接，第五電晶體之控制端接收第二控制訊號，第五電晶體之第二端與第一電容之第二端電性耦接；一第六電晶體，第六電晶體其具有一第一端、一第二端以及一控制端，第六電晶體之第一端與第四電晶體之第二端電性耦接，第六電晶體之控制端接收第一控制訊號；一有機發光二極體，有機發光二極體具有一第一端以及一第二端，有機發光二極體之第一端與第六電晶體之第二端電性耦接，有機發光二極體之第二端與一外部低電壓電性耦接。 In order to solve the above-mentioned conventional pixel unit, there are many leak circuits. The present invention provides a pixel circuit. According to an embodiment of the present invention, the present invention includes a first transistor having a first end, a second end, and a control end, the first The first end of the crystal is electrically coupled to a reference voltage, the control end of the first transistor receives a first control signal, and the second transistor has a first end, a second end, and a second transistor a control end, the first end of the second transistor is electrically coupled to a display data, the control end of the second transistor receives a second control signal, and the second end of the second transistor is second with the first transistor The first capacitor has a first end and a second end, the first end of the first capacitor and the second end of the first transistor and the second end of the second transistor Electrically coupled to the third transistor, the third transistor has a first end, a second end, and a control end, and the first end of the third transistor is electrically coupled to the second control signal, The control end of the tri-crystal receives a third control signal, and the second end of the third transistor is first The second end of the capacitor is electrically coupled; a fourth transistor having a first end, a second end, and a control end, the first end of the fourth transistor and an external high voltage The second transistor is electrically coupled to the second end of the first capacitor; the fifth transistor has a first end, a second end, and a control end, The first end of the fifth transistor is electrically coupled to the second end of the fourth transistor, the control end of the fifth transistor receives the second control signal, and the second end of the fifth transistor and the second end of the first capacitor Electrically coupled; a sixth transistor, the sixth transistor having a first end, a second end, and a control end, the first end of the sixth transistor and the second end of the fourth transistor being electrically Coupling, the control end of the sixth transistor receives the first control signal; an organic light emitting diode, the organic light emitting diode has a first end and a second end, and the first end of the organic light emitting diode The second end of the sixth transistor is electrically coupled, and the second end of the organic light emitting diode is electrically coupled to an external low voltage.

在本實施例中，畫素電路操作於一第一初始期間時，第一控制訊號為高電壓準位，第二控制訊號為高電壓準位，第三控制訊號為低電壓準位，第一電晶體、第二電晶體、第五電晶體以及第六電晶體為關閉；畫素電路操作於一第二初始期間時，第一控制訊號為高電壓準位，第二控制訊號由高電壓準位變換為低電壓準位，第三控制訊號為低電壓準位，第一電晶體與第六電晶體為關閉；畫素電路操作於一補償期間時，第一控制訊號為高電壓準位，第二控制訊號為低電壓準位，第三控制訊號為高電壓準位，第一電晶體、第三電晶體、第六電晶體為關閉；畫素電路操作於一顯示期間時，第一控制訊號為低電壓準位，第二控制訊號為高電壓準位，第三控制訊號為高電壓準位，第二電晶體、第三電晶體以及第五電晶體為關閉。 In this embodiment, when the pixel circuit operates in a first initial period, the first control signal is at a high voltage level, the second control signal is at a high voltage level, and the third control signal is at a low voltage level, first The transistor, the second transistor, the fifth transistor, and the sixth transistor are turned off; when the pixel circuit operates in a second initial period, the first control signal is at a high voltage level, and the second control signal is at a high voltage level. The bit is converted to a low voltage level, the third control signal is a low voltage level, and the first transistor and the sixth transistor are turned off; when the pixel circuit is operated during a compensation period, the first control signal is at a high voltage level. The second control signal is a low voltage level, the third control signal is a high voltage level, the first transistor, the third transistor, and the sixth transistor are turned off; and the pixel control is operated during a display period, the first control The signal is a low voltage level, the second control signal is a high voltage level, the third control signal is a high voltage level, and the second transistor, the third transistor, and the fifth transistor are turned off.

在本發明之其他實施例中，畫素電路實施例更可包括一第二電容，其具有一第一端以及一第二端並電性耦接於第二控制訊號與第三電晶體之第一端之間，第二電容之第一端與第二控制訊號電性耦接，第二電容之第二端與第三電晶體之第一端電性耦接。 In another embodiment of the present invention, the pixel circuit embodiment further includes a second capacitor having a first end and a second end electrically coupled to the second control signal and the third transistor The first end of the second capacitor is electrically coupled to the second control signal, and the second end of the second capacitor is electrically coupled to the first end of the third transistor.

綜上所述，由於本發明之畫素電路實施例之第四電晶體控制端與第一電容以及第三電晶體電性耦接，在顯示期間時，基於電容特性以及第三電晶體之第一端為高於第四電晶體控制端電壓準位的高電壓準位，因此第四電晶體控制端之漏電流只會往有機發光二極體流動，故本發明之畫素電路實施例能有效降低漏電流之路徑，使第四電晶體控制端之電壓準位不因漏電流大幅變動，因此第四電晶體之驅動電流可正常驅動有機發光二極體以正常顯示。此外，第四電晶體之驅動電流更與外部高電壓以及第四電晶體之截止電壓無關，驅動電流因此不會受到外部高電壓在傳輸途中的電壓衰退或第四電晶體之電性改變所影響，而導致顯示錯誤的情況發生。 In summary, since the fourth transistor control terminal of the pixel circuit embodiment of the present invention is electrically coupled to the first capacitor and the third transistor, the capacitance characteristic and the third transistor are based on the capacitance period during the display period. One end is a high voltage level higher than the voltage level of the fourth transistor control terminal, so the leakage current of the fourth transistor control terminal only flows to the organic light emitting diode, so the pixel circuit embodiment of the present invention can The path of the leakage current is effectively reduced, so that the voltage level of the fourth transistor control terminal is not greatly changed by the leakage current, so the driving current of the fourth transistor can normally drive the organic light emitting diode to display normally. In addition, the fourth transistor The driving current is more independent of the external high voltage and the cut-off voltage of the fourth transistor, and the driving current is therefore not affected by the voltage drop of the external high voltage during transmission or the electrical change of the fourth transistor, resulting in display error. The situation happened.

為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例並配合所附圖式做詳細說明如下。 The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims.

10、30‧‧‧畫素電路 10, 30‧‧‧ pixel circuit

T1、T2、T3、T4、T5、T6‧‧‧電晶體 T1, T2, T3, T4, T5, T6‧‧‧ transistors

S1、S2、E_m‧‧‧控制訊號 S1, S2, E _m ‧‧‧ control signals

C_st、C_P‧‧‧電容 C _st , C _P ‧‧‧ capacitor

OLED‧‧‧有機發光二極體 OLED‧‧ Organic Light Emitting Diode

OVDD‧‧‧外部高電壓 OVDD‧‧‧External high voltage

OVSS‧‧‧外部低電壓 OVSS‧‧‧External low voltage

V_th‧‧‧截止電壓 V _th ‧‧‧ cutoff voltage

V_H‧‧‧高電壓準位 V _H ‧‧‧high voltage level

V_L‧‧‧低電壓準位 V _L ‧‧‧low voltage level

I_DS‧‧‧驅動電流 I _DS ‧‧‧ drive current

V_data‧‧‧顯示資料 V _data ‧‧‧Display data

V_ref‧‧‧參考電壓 V _ref ‧‧‧reference voltage

V_S‧‧‧電晶體T4第一端之電壓準位 V _S ‧‧‧voltage level of the first end of transistor T4

V_G‧‧‧電晶體T4控制端之電壓準位 V _G ‧‧‧voltage level of T4 control terminal

Frame1、Frame2‧‧‧顯示畫面 Frame1, Frame2‧‧‧ display screen

圖1為本發明之畫素電路實施例一之示意圖。 FIG. 1 is a schematic diagram of Embodiment 1 of a pixel circuit of the present invention.

圖2為本發明之畫素電路實施例一訊號時序示意圖。 FIG. 2 is a timing diagram of a signal sequence of the pixel circuit of the present invention.

圖3為本發明之畫素電路實施例二之示意圖。 FIG. 3 is a schematic diagram of Embodiment 2 of a pixel circuit of the present invention.

圖1為根據本發明一第一實施例之畫素電路示意圖。請參閱圖1，畫素電路10包括一電晶體T1、一電晶體T2、一電晶體T3、一電晶體T4、一電晶體T5一電晶體T6、電容C_st、電容C_p、以及一有機發光二極體OLED，上述之電晶體T1~T6可為P型電晶體，但不以此為限。電晶體T1具有一第一端、一第二端以及一控制端，電晶體T1之第一端與一參考電壓V_ref電性耦接，電晶體T1之控制端接收一控制訊號E_m，電晶體T1之第二端則與電晶體T2電性耦接。電晶體T2具有一第一端、一第二端以及一控制端，電晶體T2之第一端與一顯示資料V_data電性耦接，電晶體T2之控制端接收一控制訊號S2，電晶體T2之第二端則與電晶體T1之第二端電性耦接。電容C_st具有一第一端以及一第二端，電容C_st之第一端與電晶體T1之第二端以及電晶體T2之第二端電性耦接。電晶體T4具有一第一端、一第二端以及一控制端，電晶體T4之第一端與一外部高電壓OVDD電性耦接，電晶體T4之控制端與電容C_st之第二端電性耦接，電晶體T4之第二端與電晶體T5以及電晶體T6電性耦接。電晶體T5具有一第一端、一第二端以及一控制端，電晶體T5之第一端與電晶體T4之第二端電性耦接，電晶體T5之控制端用以接收上述之控制訊號S2，電晶體T5之第二端與電容C_st之第二端電性耦接。電晶體T3具有一第一端、一第二端以及一控制端，電晶體T3之第一端與電容C_p電性耦接，電晶體T3之控制端接收一控制訊號S1，電晶體T3之第二端與電容C_st的第二端電性耦接。電容C_p具有一第一端以及一第二端，電容C_p之第一端與控制訊號S2以及電晶體T5之控制端電性耦接，電容C_p之第二端與電晶體T3之第一端電性耦接。電晶體T6具有一第一端、一第二端以及一控制端，電晶體T6之第一端與電晶體T4之第二端以及電晶體T5之第一端電性耦接，電晶體T6之控制端接收控制訊號E_m，電晶體T6之第二端與有機發光二極體OLED電性耦接。有機發光二極體OLED具有一第一端以及一第二端，有機發光二極體OLED之第一端與電晶體T6之第二端電性耦接，有機發光二極體OLED之第二端與一外部低電壓OVSS電性耦接。 1 is a schematic diagram of a pixel circuit in accordance with a first embodiment of the present invention. Please refer to FIG. 1, the pixel circuit 10 includes a transistor Tl, a transistor T2, a transistor T3, a transistor T4, a transistor T5 a transistor T6, the capacitor C _st, the capacitor C _p, and an organic For the light-emitting diode OLED, the above-mentioned transistors T1 to T6 may be P-type transistors, but are not limited thereto. The transistor T1 has a first end, a second end and a control end. The first end of the transistor T1 is electrically coupled to a reference voltage V _ref , and the control end of the transistor T1 receives a control signal E _m . The second end of the crystal T1 is electrically coupled to the transistor T2. The transistor T2 has a first end, a second end and a control end. The first end of the transistor T2 is electrically coupled to a display data V _data , and the control end of the transistor T2 receives a control signal S2, the transistor The second end of T2 is electrically coupled to the second end of the transistor T1. The capacitor C _st has a first end and a second end. The first end of the capacitor C _st is electrically coupled to the second end of the transistor T1 and the second end of the transistor T2 . The transistor T4 has a first end, a second end and a control end. The first end of the transistor T4 is electrically coupled to an external high voltage OVDD, and the control end of the transistor T4 and the second end of the capacitor C _st The second end of the transistor T4 is electrically coupled to the transistor T5 and the transistor T6. The transistor T5 has a first end, a second end and a control end. The first end of the transistor T5 is electrically coupled to the second end of the transistor T4, and the control end of the transistor T5 is configured to receive the above control. The second end of the transistor T5 is electrically coupled to the second end of the capacitor C _st . Transistor T3 having a first terminal, a second terminal and a control terminal, a first terminal of the transistor T3 and the capacitance C _p is electrically coupled to the control terminal of the transistor T3 receives a control signal Sl, the transistor T3 The second end is electrically coupled to the second end of the capacitor C _st . The capacitor C _p has a first end and a second end. The first end of the capacitor C _p is electrically coupled to the control signal S2 and the control terminal of the transistor T5. The second end of the capacitor C _{p is} the same as the transistor T3. One end is electrically coupled. The transistor T6 has a first end, a second end and a control end. The first end of the transistor T6 is electrically coupled to the second end of the transistor T4 and the first end of the transistor T5, and the transistor T6 The control terminal receives the control signal E _m , and the second end of the transistor T6 is electrically coupled to the organic light emitting diode OLED. The organic light emitting diode OLED has a first end and a second end. The first end of the organic light emitting diode OLED is electrically coupled to the second end of the transistor T6, and the second end of the organic light emitting diode OLED Electrically coupled to an external low voltage OVSS.

圖2為本發明第一實施例之畫素電路的控制訊號時序示意圖。請參考圖2，第一實施例之畫素電路的控制訊號包含控制訊號E_m、控制訊號S1以及控制訊號S2，上述之控制訊號是用以根據訊號時序使畫素電路10顯示不同顯示畫面 frame之顯示資料，圖2中並以顯示畫面Frame1以及Frame2為例，但不以此為限。其中控制訊號S1以及控制訊號S2，舉例而言，可分別為相鄰兩列之畫素電路所使用之掃描訊號，且控制訊號S1為第N列畫素電路之掃描訊號，而控制訊號S2為第N+1列畫素電路之掃描訊號，此外控制訊號S1以及控制訊號S2之掃描頻率，舉例而言，可為1Hz，即前述之低更新率，以下更以顯示畫面Frame1為例說明畫素電路的控制訊號。每一控制訊號皆具有至少一上升緣以及至少一下降緣，控制訊號S1之下降緣早於控制訊號S2之下降緣，控制訊號S1之上升緣早於控制訊號S2之上升緣，控制訊號E_m之上升緣早於控制訊號S1以及控制訊號S2之下降緣，控制訊號E_m之下降緣晚於控制訊號S1以及控制訊號S2之上升緣。此外，每一控制訊號皆具有高電壓準位V_H以及低電壓準位V_L，高電壓準位V_H並高於外部高電壓OVDD之電壓準位，外部高電壓OVDD之電壓準位高於參考電壓V_ref之電壓準位，參考電壓之電壓準位V_ref高於外部低電壓OVSS之電壓準位，外部低電壓OVSS之電壓準位高於低電壓準位V_L。 2 is a timing chart showing the control signals of the pixel circuit of the first embodiment of the present invention. Referring to FIG. 2, the control signal of the pixel circuit of the first embodiment includes a control signal E _m , a control signal S1 and a control signal S2. The control signal is used to cause the pixel circuit 10 to display different display frame frames according to the signal timing. For the display data, the display frames Frame1 and Frame2 are taken as an example in FIG. 2, but are not limited thereto. The control signal S1 and the control signal S2 are, for example, scanning signals used by adjacent two columns of pixel circuits, and the control signal S1 is a scanning signal of the Nth column pixel circuit, and the control signal S2 is The scan signal of the N+1th column pixel circuit, and the scanning frequency of the control signal S1 and the control signal S2, for example, may be 1 Hz, that is, the aforementioned low update rate, and the display picture Frame1 is taken as an example to illustrate the pixel. The control signal of the circuit. Each control signal has at least one rising edge and at least one falling edge. The falling edge of the control signal S1 is earlier than the falling edge of the control signal S2, and the rising edge of the control signal S1 is earlier than the rising edge of the control signal S2, and the control signal E _m The rising edge is earlier than the falling edge of the control signal S1 and the control signal S2, and the falling edge of the control signal E _m is later than the rising edge of the control signal S1 and the control signal S2. In addition, each control signal has a high voltage level V _H and a low voltage level V _L , the high voltage level V _H is higher than the voltage level of the external high voltage OVDD, and the voltage level of the external high voltage OVDD is higher than the voltage level of the reference voltage V _ref, the voltage level of the reference voltage V _ref is higher than the voltage level of OVSS external low-voltage, low-voltage external voltage level higher than the OVSS low voltage level V _L.

接著將配合圖1以及圖2來說明本發明之畫素電路實施例一之運作方法。首先，當畫素電路10操作於一第一初始期間(對應於圖2時段A)時，控制訊號S1為低電壓準位V_L，控制訊號S2為高電壓準位V_H，控制訊號E_m為高電壓準位，因此此時只有電晶體T3開啟，使電晶體T4之控制端之電壓準位分壓至電容C_p與電容C_st。接著，當畫素電路10操作於一第二初始期間(對應於圖2時段B)時，控制訊號S1為低電壓準位V_L，控制訊號S2由高電壓準位V_H轉換為低電壓準位V_L，控制訊號E_m為高電壓準位，此時由於電晶體T3仍開啟，因此與電晶體T4之控制端電性耦接之電晶體T3之第二端，會因為控制訊號S2由高電壓準位V_H轉換為低電壓準位V_L而被下拉至更低之電壓準位，因此電晶體T4會據以開啟。當畫素電路10操作於補償期間(對應於圖2時段C)時，控制訊號S1為高電壓準位V_H，控制訊號S2為低電壓準位V_L，控制訊號E_m為高電壓準位，電晶體T2以及電晶體T5為開啟，電晶體T1、電晶體T3以及電晶體T6為關閉。此時電晶體T2將顯示資料V_data傳送至電晶體T2之第二端以及電容C_st之第一端，而電晶體T4因為其第一端之外部高電壓OVDD而充至截止，因此電晶體T4之第二端之電壓準位充至外部高電壓OVDD減去電晶體T4的截止電壓V_th4的電壓準位，即OVDD-V_th4之電壓準位，又由於電晶體T5為開啟，因此OVDD-V_th4之電壓準位會傳送至電晶體T5的第二端，也就是電晶體T4之控制端。接著在時段D時，控制訊號S1為高電壓準位V_H，控制訊號S2為高電壓準位V_H，控制訊號E_m為高電壓準位V_H，電晶體T1、電晶體T2、電晶體T3、電晶體T5、電晶體T6為關閉，並準備進入顯示期間。當畫素電路10操作於顯示期間(對應於圖2時段E)時，控制訊號S1為高電壓準位V_H，控制訊號S2為高電壓準位V_H，控制訊號E_m為低電壓準位V_L，電晶體T2、電晶體T3、電晶體T5為關閉，電晶體T1以及電晶體T6此時為開啟。由於電晶體T1為開啟，因此電晶體T1將其第二端充至參考電壓V_ref之電壓準位，而在前述之補償期間時，由於電晶體T2已將電晶體T1之第二端之電壓準位充至顯示資料V_data之電壓準位，因此在顯示期間時，此節點上會出現V_ref-V_data之電壓差，並會根據電容之特性而使電容C_st的第二端也出現V_ref-V_data之電壓差，因此導致電晶體T4控制端之電壓準位由補償期間時的OVDD-V_th4之電壓準位下拉至OVDD-V_th4-(V_ref-V_data)之電壓準位，電晶體T4之驅動電流I_DS可藉由公式1/2×β×(V_S-V_G-|V_th|)²推得，I_DS=1/2×β×(OVDD-(OVDD-V_th-(V_ref-V_data))-|V_th|)²=1/2×β×(V_ref-V_data)²其中β為常數，V_S為電晶體T4第一端之電壓準位，V_G為電晶體T4控制端之電壓準位。也就是驅動電流I_DS與外部高電壓OVDD以及電晶體T4的截止電壓V_th無關。此時電晶體T6為開啟，因此有機發光二極體OLED可根據驅動電流I_DS而依照顯示資料V_data正確發光，且不受外部高電壓OVDD的衰落以及電晶體T4的截止電壓V_th變動所影響。此外，本實施例一之電晶體T4之控制端與電容C_st以及電晶體T3電性耦接，電晶體T3又與電容C_P電性耦接，而電容本身的特性並無電流流動，又電容C_P之第一端所耦接之控制訊號S2之高電壓準位高於電晶體T4控制端之電壓準位，因此電晶體T4控制端之漏電流僅往有機發光二極體OLED方向流動，故本發明實施例大幅減少了畫素電路之漏電流路徑，電容C_P更持續補償電晶體T4控制端之電壓準位，使電晶體T4可正常輸出驅動電流I_DS使有機發光二極體OLED正確發光。 Next, the operation method of the first embodiment of the pixel circuit of the present invention will be described with reference to FIG. 1 and FIG. First, when the pixel circuit 10 operates in a first initial period (corresponding to the period A of FIG. 2), the control signal S1 is at a low voltage level V _L , the control signal S2 is at a high voltage level V _H , and the control signal E _m It is a high voltage level, so only the transistor T3 is turned on at this time, and the voltage level of the control terminal of the transistor T4 is divided to the capacitor C _p and the capacitor C _st . Next, when the pixel circuit 10 operates in a second initial period (corresponding to the period B of FIG. 2), the control signal S1 is at a low voltage level V _L , and the control signal S2 is converted from a high voltage level V _H to a low voltage level. Bit V _L , the control signal E _m is at a high voltage level. At this time, since the transistor T3 is still turned on, the second end of the transistor T3 electrically coupled to the control terminal of the transistor T4 is controlled by the control signal S2. The high voltage level V _{H is} converted to a low voltage level V _L and pulled down to a lower voltage level, so that the transistor T4 is turned on. When the pixel circuit 10 operates during the compensation period (corresponding to the period C of FIG. 2), the control signal S1 is at the high voltage level V _H , the control signal S2 is at the low voltage level V _L , and the control signal E _m is at the high voltage level. The transistor T2 and the transistor T5 are turned on, and the transistor T1, the transistor T3, and the transistor T6 are turned off. At this time, the transistor T2 transmits the display data V _data to the second end of the transistor T2 and the first end of the capacitor C _st , and the transistor T4 is turned off due to the external high voltage OVDD of the first end thereof, so the transistor The voltage level of the second terminal of T4 is charged to the external high voltage OVDD minus the voltage level of the cutoff voltage _Vth4 of the transistor T4, that is, the voltage level of OVDD- _Vth4 , and since the transistor T5 is turned on, OVDD The voltage level of -V _th4 is transferred to the second end of transistor T5, which is the control terminal of transistor T4. Then, in the period D, the control signal S1 is at the high voltage level V _H , the control signal S2 is at the high voltage level V _H , the control signal E _m is the high voltage level V _H , the transistor T1, the transistor T2, the transistor T3, transistor T5, and transistor T6 are off and ready to enter the display period. When the pixel circuit 10 is operating during the display period (corresponding to the period E of FIG. 2), the control signal S1 is at the high voltage level V _H , the control signal S2 is at the high voltage level V _H , and the control signal E _m is at the low voltage level. V _L , transistor T2 , transistor T3 , and transistor T5 are off, and transistor T1 and transistor T6 are turned on at this time. Since the transistor T1 is turned on, the transistor T1 charges its second end to the voltage level of the reference voltage V _ref , and during the aforementioned compensation period, since the transistor T2 has applied the voltage of the second terminal of the transistor T1 The level is charged to the voltage level of the display data V _data . Therefore, during the display period, the voltage difference of V _ref -V _data will appear on this node, and the second end of the capacitor C _st will also appear according to the characteristics of the capacitor. The voltage difference of V _ref -V _data , so that the voltage level of the control terminal of the transistor T4 is pulled down from the voltage level of OVDD-V _th4 during the compensation period to the voltage level of OVDD-V _th4 -(V _ref -V _data ) Bit, the driving current I _{DS of the} transistor T4 can be obtained by the formula 1/2 × β × (V _S - V _G - | V _th |) ² , I _DS = 1/2 × β × (OVDD - (OVDD -V _th -(V _ref -V _data ))-|V _th |) ² = 1/2 × β × (V _ref - V _data ) ² where β is a constant and V _S is the voltage at the first end of the transistor T4 The level V _G is the voltage level of the control terminal of the transistor T4. That is, the drive current I _{DS is} independent of the external high voltage OVDD and the turn-off voltage _{Vth of the} transistor T4. At this time, the transistor T6 is turned on, so that the organic light emitting diode OLED can correctly emit light according to the display data V _data according to the driving current I _DS , and is not affected by the fading of the external high voltage OVDD and the cutoff voltage V _{th of the} transistor T4. influences. In addition, the control terminal of the transistor T4 of the first embodiment is electrically coupled to the capacitor C _st and the transistor T3 , and the transistor T3 is electrically coupled to the capacitor C _P , and the characteristic of the capacitor itself has no current flowing, and The high voltage level of the control signal S2 coupled to the first end of the capacitor C _P is higher than the voltage level of the control terminal of the transistor T4, so that the leakage current of the control terminal of the transistor T4 flows only toward the organic light emitting diode OLED. Therefore, the embodiment of the invention substantially reduces the leakage current path of the pixel circuit, and the capacitor C _P continuously compensates the voltage level of the control terminal of the transistor T4, so that the transistor T4 can normally output the driving current I _{DS to} make the organic light emitting diode. The OLED is illuminated correctly.

圖3為本發明之畫素電路實施例二，在本實施例中，畫素電路30與實施例一相同之元件具有相同之技術特徵，此外畫素電路30與實施例一並具有類似的運作方法，故不再贅述。其中畫素電路30與實施例一之差別在於，電晶體T3之第一端直接與控制訊號S2電性耦接，故當畫素電路30運作於顯示期間時，雖電晶體T3之第一端並無與電容C_P電性耦接，但控制訊號S2在顯示期間時為高於電晶體T4控制端電壓準位的高電壓準位V_H，因此不會形成漏電路徑，仍可將畫素電路30之漏電流控制為僅往有機發光二極體OLED方向流動，有效減少了畫素電路30之漏電流路徑，控制訊號S2更持續補償電晶體T4控制端之電壓準位，使電晶體T4可正常輸出驅動電流I_DS並使有機發光二極體OLED正確發光。 FIG. 3 is a second embodiment of the pixel circuit of the present invention. In the embodiment, the components of the pixel circuit 30 having the same components as those of the first embodiment have the same technical features, and the pixel circuit 30 has a similar operation as the embodiment. Method, so I won't go into details. The difference between the pixel circuit 30 and the first embodiment is that the first end of the transistor T3 is directly coupled to the control signal S2, so that when the pixel circuit 30 operates during the display period, the first end of the transistor T3 is It is not electrically coupled to the capacitor C _P , but the control signal S2 is a high voltage level V _H higher than the voltage level of the control terminal of the transistor T4 during the display period, so that a leakage path is not formed, and the pixel can still be used. The leakage current of the circuit 30 is controlled to flow only in the direction of the organic light emitting diode OLED, which effectively reduces the leakage current path of the pixel circuit 30, and the control signal S2 continuously compensates the voltage level of the control terminal of the transistor T4, so that the transistor T4 The driving current I _DS can be normally output and the organic light emitting diode OLED emits light correctly.

根據上述的內容可以得知，由於本發明之畫素電路實施例之電晶體T4之控制端與電容C_st以及電晶體T3電性耦接，在顯示期間時，基於電容特性以及電晶體T3之第一端為高於電晶體T4之控制端電壓準位的高電壓準位，因此電晶體T4控制端之漏電流只會往有機發光二極體OLED的方向流動，故本發明之畫素電路實施例能有效降低漏電流之路徑，使電晶體T4控制端之電壓準位不因漏電流大幅變動，因此電晶體T4之驅動電流可正常驅動有機發光二極體以正常顯示。此外，電晶體T4之驅動電流更與外部高電壓OVDD以及電晶體T4的截止電壓V_th無關，驅動電流因此不會受到外部高電壓OVDD在傳輸途中的電壓衰退或者電晶體T4的電性改變所影響，而導致顯示錯誤的情況發生。 According to the above, it can be seen that, since the control terminal of the transistor T4 of the embodiment of the pixel circuit of the present invention is electrically coupled to the capacitor C _st and the transistor T3, during the display period, based on the capacitance characteristics and the transistor T3 The first end is a high voltage level higher than the voltage level of the control terminal of the transistor T4, so the leakage current of the control terminal of the transistor T4 only flows in the direction of the organic light emitting diode OLED, so the pixel circuit of the present invention The embodiment can effectively reduce the path of the leakage current, so that the voltage level of the control terminal of the transistor T4 is not greatly changed by the leakage current, so the driving current of the transistor T4 can normally drive the organic light emitting diode to display normally. In addition, the driving current of the transistor T4 is more independent of the external high voltage OVDD and the off voltage _{Vth of the} transistor T4, and the driving current is therefore not subjected to the voltage decay of the external high voltage OVDD during transmission or the electrical change of the transistor T4. Affects, causing a display error to occur.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技術者，在不脫離本發明之精神和範圍內，當可做些許之更動與潤飾，因此本發明之保護範圍當視後付之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the patent application scope.

10‧‧‧畫素電路 10‧‧‧ pixel circuit

S1、S2、E_m‧‧‧控制訊號 S1, S2, E _m ‧‧‧ control signals

C_st、C_P‧‧‧電容 C _st , C _P ‧‧‧ capacitor

OLED‧‧‧有機發光二極體 OLED‧‧ Organic Light Emitting Diode

OVDD‧‧‧外部高電壓 OVDD‧‧‧External high voltage

OVSS‧‧‧外部低電壓 OVSS‧‧‧External low voltage

V_th‧‧‧截止電壓 V _th ‧‧‧ cutoff voltage

V_H‧‧‧高電壓準位 V _H ‧‧‧high voltage level

V_L‧‧‧低電壓準位 V _L ‧‧‧ low voltage level

I_DS‧‧‧驅動電流 I _DS ‧‧‧ drive current

V_data‧‧‧顯示資料 V _data ‧‧‧Display data

V_ref‧‧‧參考電壓 V _ref ‧‧‧reference voltage

Claims

A pixel circuit includes: a first transistor having a first end, a second end, and a control end, wherein the first end of the first transistor is electrically coupled to a reference voltage, The control end of the first transistor receives a first control signal; a second transistor has a first end, a second end, and a control end, the first end of the second transistor and a display The data is electrically coupled, the control end of the second transistor receives a second control signal, and the second end of the second transistor is electrically coupled to the second end of the first transistor; a capacitor having a first end and a second end, the first end of the first capacitor being electrically coupled to the second end of the first transistor and the second end of the second transistor a third transistor having a first end, a second end, and a control end, the first end of the third transistor being electrically coupled to the second control signal, the third transistor The control terminal receives a third control signal, and the second end of the third transistor is electrically coupled to the second end of the first capacitor a fourth transistor having a first end, a second end, and a control end, the first end of the fourth transistor being electrically coupled to an external high voltage, the fourth transistor The control terminal is electrically coupled to the second end of the first capacitor; a fifth transistor having a first end, a second end, and a control end, the first end of the fifth transistor being The second end of the fourth transistor is electrically coupled, and the control end of the fifth transistor receives the first a second control signal, the second end of the fifth transistor is electrically coupled to the second end of the first capacitor; a sixth transistor having a first end, a second end, and a control end The first end of the sixth transistor is electrically coupled to the second end of the fourth transistor, the control end of the sixth transistor receives the first control signal; and an organic light emitting diode a first end and a second end, the first end of the organic light emitting diode is electrically coupled to the second end of the sixth transistor, and the second end of the organic light emitting diode The terminal is electrically coupled to an external low voltage.

The pixel circuit of claim 1, further comprising a second capacitor having a first end and a second end electrically coupled to the second control signal and the third transistor The first end of the second capacitor is electrically coupled to the second control signal, and the second end of the second capacitor is electrically coupled to the first end of the third transistor.

The pixel control circuit of claim 1, wherein the first control signal has at least one rising edge and at least one falling edge, the second control signal has at least one rising edge and at least one falling edge, and the third control signal has at least one a rising edge and at least one falling edge, the falling edge of the third control signal is earlier than the falling edge of the second control signal, and the falling edge of the second control signal is earlier than the falling edge of the first control signal The rising edge of the first control signal is earlier than the rising edge of the third control signal, and the rising edge of the third control signal is earlier than the second The rising edge of the control signal is earlier than the falling edge of the third control signal, and the falling edge of the second control signal is earlier than the rising edge of the third control signal.

The pixel control circuit of claim 3, wherein the first control signal has a high voltage level of a plurality of times and a low voltage level of the plurality of times, the second control signal has a high voltage level of the plurality of times and a plurality of low voltage levels, the third control signal having a plurality of high voltage levels and a plurality of low voltage levels, the high voltage level of the first control signal, and the second control signal The high voltage level and the high voltage level of the third control signal are higher than the voltage level of the external high voltage, and the voltage level of the external high voltage is higher than the voltage level of the reference voltage, and the reference voltage is The voltage level is higher than the voltage level of the external low voltage, the voltage level of the external low voltage is higher than the low voltage level of the first control signal, the low voltage level of the second control signal, and the first The low voltage level of the three control signals.

The pixel circuit of claim 4, wherein the pixel control circuit operates in a first initial period, the first control signal is the high voltage level, and the second control signal is the high voltage level, the first The third control signal is the low voltage level, the first transistor, the second transistor, the fifth transistor, and the sixth transistor are turned off, and when the pixel circuit operates in a second initial period, the The first control signal is the high voltage level, the second control signal is converted to the low voltage level by the high voltage level, the third control signal is the low voltage level, the first transistor and the first The six transistors are turned off, and the pixel circuit operates in a compensation period. The first control signal is the high voltage level, the second control signal is the low voltage level, the third control signal is the high voltage level, the first transistor, the third transistor The sixth transistor is turned off. When the pixel circuit is operated during a display period, the first control signal is a low voltage level, the second control signal is a high voltage level, and the third control signal is a high voltage. The second transistor, the third transistor, and the fifth transistor are turned off.