TWI773293B - Driving circuit - Google Patents

Abstract

A driving circuit includes a light-emitting element, a first p-type transistor, a second p-type transistor, a third p-type transistor, a first n-type transistor, a second n-type transistor, a third n-type transistor and a fourth n-type transistor. The first p-type transistor is configured to provide a driving current to the light-emitting element. The light-emitting element, the first p-type transistor, the second p-type transistor, the third p-type transistor are electrically coupled to a current path of the driving current provided to the light-emitting element. The first n-type transistor is configured to reset the driving circuit during a reset period. The second n-type transistor is configured to transmit a data signal to the driving circuit during the compensation and write period. The third n-type transistor is conducted during the compensation and write period, such that a threshold voltage of the first p-type transistor can be compensated. The fourth n-type transistor is configured to reset light-emitting element during the reset period.

Description

Drive circuit

This case is about a driving circuit, especially a driving circuit for a light-emitting element.

Today's displays have widely used driving current to provide driving current to drive light-emitting elements. Generally speaking, the driving current is determined by the potential of the gate node of the driving transistor. If the potential of the gate node is shifted due to leakage current, may cause picture distortion. Therefore, how to reduce the picture distortion caused by the offset of the potential of the gate terminal due to the leakage current is an important issue in the art.

The present disclosure provides a driving circuit. The driving circuit includes a light-emitting element, a first P-type transistor, a second P-type transistor, a third P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, and a fourth P-type transistors. The first P-type transistor is used for providing driving current to the light-emitting element. The first terminal of the second P-type transistor is electrically coupled to the high voltage terminal of the system, and the second terminal of the second P-type transistor is electrically coupled to the first terminal of the first P-type transistor. The first end of the third P-type transistor is electrically coupled to the second end of the first P-type transistor, and the second end of the third P-type transistor is electrically coupled to the first end of the light-emitting element. The second end of the light-emitting element is electrically coupled to the low voltage end of the system. The first end of the first N-type transistor is electrically coupled to the second end of the first P-type transistor, and the second end of the first end is electrically coupled to the low voltage end of the system. The first end of the second N-type transistor is used for receiving the data signal, and the second end thereof is electrically coupled to the first end of the first P-type transistor. The first end of the third N-type transistor is electrically coupled to the second end of the first P-type transistor, and the second end of the third N-type transistor is electrically coupled to the first end of the first N-type transistor.

To sum up, the present disclosure uses N-type transistors for the transistors outside the current path of the driving current, so as to solve the problem of distortion of the display screen due to leakage current.

The following examples are described in detail in conjunction with the accompanying drawings, but the provided examples are not intended to limit the scope of the present disclosure, and the description of the structure and operation is not intended to limit its execution order. The structure and the resulting device with equal efficacy are all within the scope of the present disclosure. In addition, the drawings are for illustrative purposes only, and are not drawn according to the original size. For ease of understanding, the same or similar elements in the following description will be described with the same symbols.

The terms used throughout the specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, in the content disclosed herein and in the specific content.

In addition, the terms "comprising", "including", "having", "containing" and the like used in this document are all open-ended terms, ie, meaning "including but not limited to". In addition, the term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

In this document, when an element is referred to as being "coupled" or "connected", it may be referred to as "electrically coupled" or "electrically connected". "Coupled" or "connected" may also be used to indicate the cooperative operation or interaction between two or more elements. In addition, although terms such as "first", "second", . . . are used herein to describe different elements, the terms are only used to distinguish elements or operations described by the same technical terms.

FIG. 1 is a circuit structure diagram of a driving circuit 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the driving circuit 100 includes a light-emitting element L1, a first P-type transistor TP1, a second P-type transistor TP2, a third P-type transistor TP3, a first N-type transistor TN1, and a second N-type transistor TN1. type transistor TN2, a third N-type transistor TN3, a fourth N-type transistor TN4, and a capacitor Cst.

The first P-type transistor TP1 is used for providing a driving current to the light-emitting element L1 during the light-emitting period, so that the light-emitting element emits light according to the driving current. The second P-type transistor TP2 and the third P-type transistor TP3 are used to prevent large voltage degradation. The first N-type transistor TN1 is used to reset the driving circuit 100 during the reset period. The second N-type transistor TN2 is used for writing the data signal DATA into the driving circuit 100 during compensation and data writing. The third N-type transistor TN3 is turned on during the compensation period to enable the driving circuit 100 to compensate the threshold voltage of the first P-type transistor TP1 . The fourth N-type transistor TN4 is used for resetting the first end of the light emitting element L1 during the resetting period.

The first P-type transistor TP1, the second P-type transistor TP2, the third P-type transistor TP3 and the light emitting element L1 are electrically coupled between the system high voltage terminal VDD and the system low voltage terminal VSS. That is to say, the current path of the driving current flowing through the light-emitting element L1 is implemented by a P-type transistor, thereby increasing the current driving capability of the transistor, reducing the range of the required driving voltage, and achieving low power consumption. consumption effect. Further, the aforementioned P-type transistor may be a low temperature polysilicon thin film transistor.

The aforementioned transistors respectively have a first terminal, a second terminal and a gate terminal (Gate). When the first terminal of one of the transistors is the drain terminal (source terminal), the second terminal of the transistor is the source terminal (drain terminal). In addition, the aforementioned capacitors also have a first end and a second end, respectively.

In detail, the first terminal of the second P-type transistor TP2 is electrically coupled to the system high voltage terminal VDD, and the second terminal of the second P-type transistor TP2 is electrically coupled to the first terminal of the first P-type transistor TP1 The gate terminal of the second P-type transistor TP2 is used for receiving the third control signal EM.

The first end of the first P-type transistor TP1 is electrically coupled to the second end of the second P-type transistor TP2, and the second end of the first P-type transistor TP1 is electrically coupled to the third P-type transistor TP3. At the first end, the gate terminal of the first P-type transistor TP1 is electrically coupled to the node A. Node B is at the connection between the second end of the first P-type transistor TP1 and the second end of the third P-type transistor TP3. Node C is at the connection between the second end of the third P-type transistor TP3 and the first end of the light emitting element L1. The node D is at the connection between the source terminal (first terminal) of the first P-type transistor TP1 and the second terminal of the second P-type transistor TP2. The first terminal of the third P-type transistor TP3 is electrically coupled to the second terminal of the first P-type transistor TP1, and the second terminal of the third P-type transistor TP3 is electrically coupled to the first terminal of the light-emitting element L1. The gate terminal of the third P-type transistor TP3 is used for receiving the third control signal EM.

The first terminal of the light emitting element L1 is electrically coupled to the second terminal of the third P-type transistor TP3, and the second terminal of the light emitting element L1 is electrically coupled to the system low voltage terminal VSS.

The magnitude of the driving current flowing through the light-emitting element L1 is positively related to the potential of the gate terminal of the first P-type transistor TP1. Generally speaking, the data voltage will write (or affect) the potential of the gate terminal to determine the magnitude of the driving current In the display period, if there is a leakage path at the gate terminal of the first P-type transistor TP1, the potential of the gate terminal is shifted due to leakage, which may cause the display screen to flicker. In order to prevent the screen of the display from flickering due to leakage at the gate terminal of the first P-type transistor TP1 (node A), in this disclosure, the driving circuit 100 drives the transistor on a path other than the current path of the driving current. All are implemented with N-type transistors. The aforementioned N-type transistors (eg, the first N-type transistor TN1 , the second N-type transistor TN2 , the third N-type transistor TN3 and the fourth N-type transistor TN4 ) may be indium gallium zinc oxide thin film transistors. Compared with the low temperature polysilicon thin film transistor, the leakage current of the indium gallium zinc oxide thin film transistor is smaller when it is turned off, so the gate terminal potential of the first P-type transistor TP1 is less likely to be affected by the leakage current of other surrounding transistors , which can be maintained at a stable potential. Therefore, in a display with a low picture update frequency, the driving circuit 100 can effectively improve the problem of picture distortion caused by the leakage of node A.

Specifically, the first terminal of the first N-type transistor TN1 is electrically coupled to the gate terminal (node A) of the first P-type transistor TP1 , and the second terminal of the first N-type transistor TN1 is electrically coupled to the system The low voltage terminal VSS, the gate terminal of the first N-type transistor TN1 is used for receiving the first control signal S1.

The first terminal of the second N-type transistor TN2 is used to receive the data signal DATA, the second terminal of the second N-type transistor TN2 is electrically coupled to the first terminal of the first P-type transistor TP1, and the second N-type transistor TN2 is electrically coupled to the first terminal of the first P-type transistor TP1. The gate terminal of the crystal TN2 is used for receiving the second control signal S2.

The first terminal of the third N-type transistor TN3 is electrically coupled to the second terminal of the first P-type transistor TP1, and the second terminal of the third N-type transistor TN3 is electrically coupled to the second terminal of the first P-type transistor TP1. The gate terminal (node A) and the first terminal of the first N-type transistor TN1 and the gate terminal of the third N-type transistor TN3 are used for receiving the third control signal EM.

The first terminal of the capacitor Cst is electrically coupled to the system high voltage terminal VDD, the second terminal of the capacitor Cst is electrically coupled to the gate terminal of the first P-type transistor TP1, and the capacitor Cst is used to store the voltage of the first P-type transistor TP1. voltage at the gate terminal.

The first terminal of the fourth N-type transistor TN4 is electrically coupled to the first terminal of the light-emitting element L1, the second terminal of the fourth N-type transistor TN4 is electrically coupled to the system low voltage terminal VSS, and the fourth N-type transistor The gate terminal of TN4 is used for receiving the first control signal S1.

FIG. 2 is a timing diagram of control signals of the pixel driving circuit 100 in FIG. 1 according to an embodiment. As shown in FIG. 2 , a display period in the control sequence of the pixel driving circuit 100 can be divided into three periods, which are a reset period P1 , a compensation and writing period P2 and a light-emitting period P3 . It should be particularly noted that the time lengths of the periods in FIG. 2 are only used as examples, and are not used to limit the present disclosure.

Specifically, the first control signal S1 has a first logic level (eg, a high logic level VH) during the reset period P1; the first control signal S1 has a second logic level during the compensation and writing period P2 and the light-emitting period P3 level (eg: low logic level VL). The second control signal S2 has a first logic level during the compensation and writing periods P2; the second control signal S2 has a second logic level during the reset period P1 and the light-emitting period P3. The third control signal EM has a first logic level during the reset period P1 and the compensation and writing period P2; the third control signal EM has a second logic level during the light-emitting period P3.

In order to make the overall operation of the pixel driving circuit 100 clearer and easier to understand, please refer to FIGS. 1 to 3C together below. FIG. 3A is a circuit state diagram of the pixel driving circuit 100 in the reset period P1 in FIG. 1 . FIG. 3B is a circuit state diagram of the pixel driving circuit 100 in the compensation and writing period P2 in FIG. 1 . FIG. 3C is a circuit state diagram of the pixel driving circuit 100 in the light-emitting period P3 in FIG. 1 .

During the reset period P1, since the first control signal S1 and the third control signal EM have a high logic level VH, the first N-type transistor TN1 and the third N-type transistor TN3 are turned on, and the second P-type transistor is turned on. The crystal TP2 and the third P-type transistor TP3 are turned off. On the other hand, since the second control signal S2 has a low logic level VL, the second N-type transistor TN2 is turned off.

Specifically, during the reset period P1, the voltage Vss of the system low voltage terminal VSS is transmitted to the gate terminal (node A) of the first P-type transistor TP1 through the first N-type transistor TN1, so as to connect the first P-type voltage The potential of the gate terminal of the transistor TP1 is pulled down to the voltage Vss, thereby resetting the potential of the gate terminal of the first P-type transistor TP1 and turning on the first P-type transistor TP1. At the same time, the voltage Vss of the system low voltage terminal VSS is transmitted to the node D through the first N-type transistor TN1, the third N-type transistor TN3 and the first P-type transistor TP1 until the first P-type transistor TP1 is turned off. This resets the potential of the source terminal (first terminal) of the first P-type transistor TP1.

At this time, the potential of node A and the potential of node D are substantially equal to the potential Vss of the system low voltage terminal VSS, and the potential of node D is substantially equal to the voltage Vss of the system low voltage terminal VSS plus the first P-type transistor TP1. The absolute value of the threshold voltage |Vth|.

It is worth noting that during the reset period P1, since the first control signal S1 has a high logic level VH, the fourth N-type transistor TN4 is turned on, so that the potential of the system low-voltage terminal VSS passes through the fourth N-type transistor TN4 It is transmitted to the first end of the light-emitting element L1, thereby resetting the potential of the first end of the light-emitting element L1. That is, the potential of the node C is substantially equal to the voltage Vss of the system low voltage terminal VSS.

The fourth N-type transistor TN4 transfers the voltage Vss of the system low voltage terminal VSS to the anode terminal (first terminal) of the light-emitting element L1 during the reset period P1, so that the potential of the anode terminal of the light-emitting element L1 can be stabilized at the voltage Vss, thereby improving the contrast of the picture.

During the compensation and writing period P2, since the second control signal S2 and the third control signal EM have a high logic level VH, the second N-type transistor TN2 and the third N-type transistor TN3 are turned on, and the second N-type transistor TN2 and the third N-type transistor TN3 are turned on. The P-type transistor TP2 and the third P-type transistor TP3 are turned off. On the other hand, since the first control signal S1 has a low logic level VL, the first N-type transistor TN1 and the fourth N-type transistor TN4 are turned off.

Specifically, at the beginning of the compensation and writing period P2, the voltage of the gate terminal of the first P-type transistor TP1 is still at Vss, so that the first P-type transistor TP1 is turned on. The data signal DATA is transmitted to the gate terminal (node A) of the first P-type transistor TP1 through the second N-type transistor TN2, the first P-type transistor TP1 and the third N-type transistor TN3 until the first P-type transistor The crystal TP1 is turned off (when the potential difference between the source terminal and the gate terminal of the first P-type transistor TP1 is the absolute value |Vth| of the threshold voltage of the first P-type transistor TP1, the first P-type transistor TP1 is turned off), by This writes the data signal DATA into the gate terminal of the first P-type transistor TP1. At this time, the potential of the node D is substantially equal to the voltage Vdata of the data signal DATA, so the potentials of the node A and the node B are substantially equal to (Vdata-|Vth|). Also, the potential of the node C is maintained at the voltage Vss.

During the light-emitting period P3, since the third control signal EM has a low logic level VL, the second P-type transistor TP2 and the third P-type transistor TP3 are turned on, and the third N-type transistor TN3 is turned off. Moreover, since the first control signal S1 and the second control signal S2 also have the low logic level VL, the first N-type transistor TN1 , the second N-type transistor TN2 and the fourth N-type transistor TN4 are turned off.

In detail, since the first N-type transistor TN1, the third N-type transistor TN3 and the fourth N-type transistor TN4 are turned off, the potential of the gate terminal of the first P-type transistor TP1 is still maintained at (Vdata-| Vth|). And the voltage Vdd of the system high voltage terminal VDD is transmitted to the source terminal of the first P-type transistor TP1 via the second P-type transistor TP2. Therefore, the cross voltage (Vsg) of the source terminal and the gate terminal of the first P-type transistor TP1 is [Vdd-(Vdata-|Vth|)].

Generally speaking, the driving current that the P-type transistor can provide obeys the following formula: Id=k(Vsg-|Vth|) ² . Wherein, k is a constant related to the element characteristics of the second P-type transistor TP2, and |Vth| is the absolute value of the threshold voltage of the second P-type transistor TP2.

Substitute the above-mentioned cross voltage (Vsg) between the source terminal and the gate terminal of the second P-type transistor TP2 into the formula of the driving current Id, the driving current Id is calculated as follows: Id=k(Vsg-|Vth|) ² Id=k {[Vdd-(Vdata-|Vth|)]-|Vth|} ² Id=k(Vdd-Vdata) ²

During the light-emitting period P3, the first P-type transistor TP1 provides a driving current Id=k(Vdd-Vdata) ² to the light-emitting element L1, so that the light-emitting element L1 emits light according to the magnitude of the driving current Id.

For example, if the voltage Vdata of the data signal DATA written by the driving circuit 100 is relatively large during the compensation and writing period P2, then due to the aforementioned formula of the driving current Id, the light-emitting element L1 will be based on a relatively small voltage during the light-emitting period P3. On the other hand, if the voltage Vdata of the data signal DATA written by the driving circuit 100 is small, the light-emitting element L1 is in the light-emitting period due to the aforementioned formula of the driving current Id. P3 will be at a higher brightness (gray scale) according to a larger driving current Id.

Please refer to FIG. 4A . FIG. 4A is a schematic diagram of the voltage of node A in FIG. 1 . In detail, FIG. 4A shows a voltage waveform diagram of node A when the variation (ΔVth) of the threshold voltage Vth of the first P-type transistor TP1 is between 0.5 and -0.5, wherein the voltage of node A is represented by V _A express. Among them, the horizontal axis coordinate is time, and the unit is microsecond (μs), and the vertical axis coordinate is voltage, and the unit is volt (V). In the embodiment of FIG. 4A, the voltage Vdata of the same data signal DATA is used as an example.

If the variation (ΔVth) of the threshold voltage Vth of the first P-type transistor TP1 is 0.5 volts, the value of the node A during the light-emitting period P3 will be 2.149 volts (V).

If the variation (ΔVth) of the threshold voltage Vth of the first P-type transistor TP1 is 0 volts, the value of the node A during the light-emitting period P3 will be 1.674 volts (V).

If the variation (ΔVth) of the threshold voltage Vth of the first P-type transistor TP1 is -0.5 volts, the value of the node A during the light-emitting period P3 will be 1.145 volts (V).

Please refer to Figure 4B, which is a simulation of the current error in Figure 1. In the embodiment shown in FIG. 4B, the left oblique line is filled to represent the current error rate of the driving current Id when the variation (ΔVth) of the threshold voltage Vth of the first P-type transistor TP1 is at -0.5 volts (V), and the right oblique line The fill represents the current error rate of the driving current Id when the variation (ΔVth) of the threshold voltage Vth of the first P-type transistor TP1 is 0.5 volts (V). Among them, the horizontal axis coordinate is the current error rate, and the unit is percentage (%), and the vertical axis coordinate is the voltage, and the unit is volt (V). It is worth mentioning that, since the driving current Id=k(Vdd-Vdata) ² , the order of Vdata from small to large represents the gray scale from high to low. As shown in FIG. 4B , it can be seen that the current error rate of the drive current Id is approximately 3.14% or less. In this way, it can be verified that the driving circuit 100 can effectively compensate for the variation of the threshold voltage Vth of the first P-type transistor TP1.

In some common practices, the current error rates of the driving current of some display driving circuits at low, medium and high gray scales are 9.42 nanoamps (nA), 48.55 nanoamps (nA) and 57.85 nanoamps (nA), respectively. . Under the structure of the driving circuit 100 of the present disclosure, the current error rates of the driving current Id at low, middle, and high gray scales are 0.01 nanoampere (nA), 0.51 nanoampere (nA), and 0.7 nanoampere (nA), respectively. Therefore, it can be seen that under the structure of the driving circuit 100 in which the transistors outside the current path of the driving current Id are all N-type transistors, the leakage current at the gate terminal of the first P-type transistor TP1 can indeed be reduced. In this way, the current error of the driving current of the driving circuit 100 at low, medium and high gray scales can be significantly reduced, thereby avoiding distortion of the display image.

To sum up, the driving circuit 100 of the present disclosure has the capability of compensating for the threshold voltage, and the transistor on the current path of the driving current Id is implemented as a P-type transistor, which can reduce the cross-voltage required to turn on the transistor, In this way, the driving capability is increased, and the transistors outside the current path of the driving current Id are implemented as N-type transistors, which can improve the problem of distortion of the display screen caused by the leakage of the node A. Further, the third N-type transistor shares the third control signal EM with the second P-type transistor and the third P-type transistor, thereby reducing the area of the circuit for generating the control signal.

Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection disclosed shall be determined by the scope of the appended patent application.

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the descriptions of the appended symbols are as follows: 100: Drive circuit L1: Light-emitting element TP1: The first P-type transistor TP2: Second P-type transistor TP3: The third P-type transistor TN1: The first N-type transistor TN2: Second N-type transistor TN3: The third N-type transistor TN4: Fourth N-type transistor Cst: Capacitance A,B,C,D: Nodes VDD: system high voltage terminal VSS: system low voltage side S1: The first control signal S2: The second control signal EM: the third control signal DATA: data signal Id: drive current P1: During reset P2: Compensation and writing period P3: During light emission VH: High logic level VL: low logic level

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows: FIG. 1 is a circuit structure diagram of a driving circuit according to an embodiment of the present disclosure. FIG. 2 is a timing chart of control signals of the driving circuit in FIG. 1 . Fig. 3A is a circuit state diagram of the drive circuit in Fig. 1 during a reset period. FIG. 3B is a circuit state diagram of the drive circuit in FIG. 1 during the compensation and writing periods. Fig. 3C is a circuit state diagram of the drive circuit in Fig. 1 during the light emission period. FIG. 4A is a schematic diagram of the voltage of node A in FIG. 1 . FIG. 4B is a schematic diagram of the current error in FIG. 1 .

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

100: Drive circuit

L1: Light-emitting element

TP1: The first P-type transistor

TP2: Second P-type transistor

TP3: The third P-type transistor

TN1: The first N-type transistor

TN2: Second N-type transistor

TN3: The third N-type transistor

TN4: Fourth N-type transistor

Cst: Capacitance

A,B,C,D: Nodes

VDD: system high voltage terminal

VSS: system low voltage side

S1: The first control signal

S2: The second control signal

EM: the third control signal

DATA: data signal

Claims (10)

A driving circuit includes: a light-emitting element; a first P-type transistor, the first P-type transistor is used to provide a driving current to the light-emitting element; a second P-type transistor, the first terminal of which is electrically coupled to a system high voltage terminal, the second terminal of which is electrically coupled to the first terminal of the first P-type transistor; a third P-type transistor, the first terminal of which is electrically coupled to the first P-type transistor a second end of the crystal, the second end of which is electrically coupled to the first end of the light-emitting element, wherein the second end of the light-emitting element is electrically coupled to a system low voltage end; a first N-type transistor, the first end of which is One end is electrically coupled to the second end of the first P-type transistor, the second end of which is electrically coupled to the low-voltage end of the system; a second N-type transistor, the first end of which is used for receiving a data signal , the second terminal of which is electrically coupled to the first terminal of the first P-type transistor; and a third N-type transistor, the first terminal of which is electrically coupled to the second terminal of the first P-type transistor, Its second terminal is electrically coupled to the first terminal of the first N-type transistor, wherein the gate terminal of the third N-type transistor, the gate terminal of the second P-type transistor and the third P-type transistor The gate terminal is used for receiving a third control signal. The driving circuit of claim 1, further comprising: a capacitor, the first terminal of which is electrically coupled to the high voltage terminal of the system, and the second terminal of which is electrically coupled to the gate terminal of the first P-type transistor. The driving circuit of claim 1, wherein: the gate terminal of the first N-type transistor is used for receiving a first control signal; and the gate terminal of the second N-type transistor is used for receiving a second control signal . The driving circuit of claim 3, wherein during a reset period, the first control signal is at a first logic level to turn on the first N-type transistor, and the third control signal is at the first logic level The standard is to turn off the second P-type transistor and the third P-type transistor and turn on the third N-type transistor, so that the potential of the low-voltage terminal of the system is transmitted to the first N-type transistor through the first N-type transistor. The gate terminal of the P-type transistor turns on the first P-type transistor, and the potential of the low-voltage terminal of the system is transmitted through the first N-type transistor, the third N-type transistor and the first P-type transistor to the first end of the first P-type transistor. The driving circuit of claim 3, wherein during a compensation and writing period, the second control signal is at a first logic level to turn on the second N-type transistor, and the third control signal is at the first logic level The logic level is to turn off the second P-type transistor and the third P-type transistor and turn on the third N-type transistor, so that the data signal passes through the second N-type transistor, the first P-type transistor The crystal and the third N-type transistor are transmitted to the gate terminal of the first P-type transistor until the first P-type transistor is turned off. The driving circuit of claim 3, wherein during a lighting period, the third control signal is at a second logic level to turn off the third N-type transistor and turn on the second P-type transistor and the first Three P-type transistors, so that the first P-type transistor provides the driving circuit to the light-emitting diode. The driving circuit of claim 1, further comprising: a fourth N-type transistor, the first terminal of which is electrically coupled to the first terminal of the light-emitting element, and the second terminal of which is electrically coupled to the system low voltage terminal , and its gate terminal is used to receive a first control signal. The driving circuit of claim 7, wherein during a reset period, the first control signal is at a first logic level to turn on the fourth N-type transistor, so that the potential of the system low voltage terminal passes through the first logic level. Four N-type transistors are transmitted to the first end of the light-emitting element. The driving circuit of claim 7, wherein during a compensation and writing period and a light-emitting period, the first control signal is at a second logic level to turn off the fourth N-type transistor. The driving circuit of claim 1, wherein the first P-type transistor, the second P-type transistor and the third P-type transistor are low temperature polysilicon thin film transistors, wherein the first N-type transistor, the The two N-type transistors, the third N-type transistor and the fourth N-type transistor are indium gallium zinc oxide thin film transistors.

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