TWI474017B - Semiconductor integrated circuit - Google Patents

Description

Semiconductor integrated circuit

The present invention relates to a semiconductor wafer and a semiconductor integrated circuit, and more particularly to a semiconductor wafer mountable to an interposer and a semiconductor integrated circuit using the same.

A semiconductor integrated circuit has been previously provided, which is a wafer (SOC: system single chip) of any main circuit of a computer such as a microprocessor, a chipset, a video chip, or a DRAM. The semiconductor integrated circuit can considerably reduce the area required for mounting, and can greatly suppress power consumption as compared with a system formed by a plurality of wafers having the same circuit. Further, before the shipment of the semiconductor integrated circuit, it is usually necessary to perform tests such as the operation of each main circuit and the connection relationship between the terminals of the main circuit.

Patent Document 1 discloses a bump inspection apparatus which checks a state of a bump hidden under a wafer by using X-ray fluoroscopy on a semiconductor integrated circuit mounted by bump bonding. According to the technique of Patent Document 1, the center position of the bump is detected by X-rays, and the reference bump is set based on the center position, and the shape of the bump is determined by comparing the reference bump with the shape of the bump to be inspected.

Further, Patent Document 2 discloses a technique for performing a connection test between a terminal of a first semiconductor integrated circuit device mounted on a printed circuit board and a terminal of the second semiconductor integrated circuit device. According to the technique of Patent Document 2, the second semiconductor integrated circuit device includes a test data take-in holding mechanism that takes in and holds test data output from the first semiconductor integrated circuit device, and After the test data is taken into consideration of whether or not the output of the holding mechanism is a specific value, the connection test between the terminals of the first and second semiconductor integrated circuit devices is performed.

Further, Patent Document 3 discloses a test apparatus for a printed circuit board on which an MPU is mounted, which can perform an overall test of all the bus bars and other functions of the printed circuit board including the MPU, and can easily determine the final faulty portion. The technique of Patent Document 3 includes a printed circuit board connection mechanism connected to an external device connection mechanism, a test ROM in which a test test program is stored, a test actuator that executes a test program for the MPU, and a print program according to the control program. The board connection mechanism performs a test control mechanism for the MPU operation control, and performs a test of the printed circuit board via an external machine connection mechanism by causing the MPU to execute a test program.

Further, Patent Document 4 discloses a test method for a printed circuit board in which a quality test is performed on a printed circuit board on which a plurality of connectors and electronic components are mounted. According to the technique of Patent Document 4, after the connector of the printed circuit board to be tested is inserted into the interface panel, the printed circuit board is connected to the test machine body, and the connection contents of the printed circuit board are automatically distributed, designed, and displayed in the test. Machine body. Then, when the test information such as the correction, the change, or the addition of the printed circuit board connection content is input from the display screen, the test machine body reads the test circuit program from the circuit mesh pattern of the printed circuit board, and the integration of the test information is made. Test circuit and test program, and execute the test program to test the printed circuit board.

[Patent Document 1] Japanese Patent Laid-Open No. Hei 5-251535

[Patent Document 2] Japanese Patent Laid-Open No. Hei 6-279919

[Patent Document 3] Japanese Patent Laid-Open No. Hei 10-55287

[Patent Document 4] Japanese Patent Laid-Open Publication No. 2002-71756

With the progress of large-scale and high-integration of semiconductor integrated circuits, the interval between the electrodes of the semiconductor integrated circuits is required to be 100 μm or less. As a result, a very large number of electrodes (for example, microbumps) are formed.

Therefore, it is considered that when the semiconductor integrated circuit is inspected, the probe is brought into contact with the semiconductor wafer before the formation of the microbumps, and inspection is performed. However, there is a problem that the metal pad for bump formation is damaged by the needle of the probe card.

On the other hand, in the technique of Patent Document 1, although it is possible to determine whether or not the shape of the bump is good, there is a problem that it is practically impossible to confirm whether or not the main circuit is operating correctly. According to the technique of Patent Document 2, it is necessary to provide a test data generating mechanism for generating test data for connection test in the first semiconductor integrated circuit device mounted on the printed circuit board, which has a problem of hindering high integration.

In addition, the signal pin of the inspection device of the semiconductor integrated circuit needs to be controlled below the 512 pin. For example, assuming a memory chip with a bit width of 256 bits, only 512 pins are needed for input and output bits. Others that take into account the address terminal and mode control terminal will exceed the limit of 512 pins.

In this regard, the techniques of Patent Documents 3 and 4 require the connection of a printed circuit board to an external device. However, if the semiconductor integrated circuit is highly integrated into, for example, 512 bits or more, the number of electrodes becomes 512 or more, and it is virtually impossible to connect all of the electrodes to an external device.

The present invention has been made to solve the above problems, and its purpose is to provide A semiconductor wafer and a semiconductor integrated circuit capable of efficiently and reliably inspecting a highly integrated semiconductor integrated circuit.

The semiconductor wafer of the present invention can be mounted on an interposer, and includes: a plurality of electrodes having a minimum pitch of 100 μm or less, a wiring connecting the interposer and a wiring in the semiconductor wafer; and a plurality of probe electrodes Connected to one of the plurality of electrodes; a dividing mechanism that divides a test signal input to the probe electrode and supplies it to a wiring connected to the plurality of electrodes as a wiring in the semiconductor wafer; And a signal processing unit that performs a specific signal processor based on the test signal divided by the dividing mechanism.

The semiconductor wafer is mounted on the interposer via electrodes having a minimum pitch of 100 μm or less. The probe electrode is attached to a portion of the electrode. Further, the dividing means divides the test signal input to the probe electrode and supplies it to the wiring connected to the plurality of electrodes as the wiring in the semiconductor wafer. Then, the signal processing mechanism performs specific signal processing based on the divided test signals.

Therefore, in the above invention, even in the case of an electrode having a multi-bit width, a test signal can be supplied to the wiring connected to each electrode, so that the inspection can be performed efficiently and surely.

The semiconductor wafer of the present invention can be mounted on an interposer, and includes a signal processing mechanism for performing a specific signal processor, and a plurality of electrodes having a minimum pitch of 100 μm or less and connected to the signal processing mechanism. Wiring and wiring in the interposer; calculation processing mechanism based on test signals from wirings respectively connected to the plurality of electrodes No., a specific calculation processor; and a probe electrode that outputs the calculation result of the calculation processing mechanism.

Therefore, in the above-described invention, even in the case of an electrode having a multi-bit width, a specific calculation can be performed using a test signal from a wiring connected to each electrode, so that the inspection can be performed efficiently and surely.

The semiconductor integrated circuit of the present invention is characterized in that the first and second semiconductor wafers are mounted on the interposer via electrodes having a minimum pitch of 100 μm or less, and the first semiconductor wafer includes an input signal input means; a first transmission mechanism that transmits a signal to the input mechanism to the second semiconductor wafer via the electrode of the pitch; a first receiving mechanism that receives a signal transmitted from the second semiconductor wafer; and an output that is received by the receiving mechanism An output electrode of the signal; the second semiconductor wafer includes: a second receiving unit that receives a signal transmitted from the first semiconductor wafer; and a signal received by the second receiving unit through the electrode of the pitch to the second 1 second transmission mechanism for semiconductor wafer transmission.

Therefore, in the above invention, the signal input to the first semiconductor wafer is transferred from the first semiconductor wafer to the second semiconductor wafer via the electrode, and is transmitted from the second semiconductor wafer to the first semiconductor wafer via the electrode, and then output from the output electrode. Therefore, it is possible to efficiently and reliably check the wiring conditions in the first and second semiconductor wafers and the wiring conditions between the electrodes.

The present invention efficiently and reliably inspects a semiconductor integrated circuit having electrodes having a multi-bit width.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Further, the same symbol (number) is given to the circuit of the same configuration, and a word (letter) is added as needed. Further, the following embodiments are merely examples of the present invention, and design changes can be appropriately made without departing from the scope of the invention.

[First Embodiment]

Figure 1 is a plan view of a semiconductor integrated circuit. The semiconductor integrated circuit includes an interposer 1, a memory chip 10 and an ASIC wafer 80 mounted on the interposer 1. A plurality of probe pads 2 are disposed on the interposer 1.

The memory wafer 10 includes a DRAM 21 to be described later, a plurality of microbumps 11 that are connected to the wiring in the memory wafer 10 and the wiring of the interposer 1 and arranged at a minimum pitch of 100 μm or less, and a plurality of probe pads 12.

The ASIC chip 80 includes an ASIC (specific logic circuit) not shown, a plurality of microbumps 81 connected to the wiring in the ASIC wafer 80 and the wiring of the interposer 1 and arranged at a minimum pitch of 100 μm or less, and a complex number. Pin cushion 82.

Figure 2 is a cross-sectional view taken along line I-I of Figure 1. On the upper surface of the interposer 1 (the surface facing the memory chip 10 and the ASIC wafer 80), a metal wiring pattern 5 including the metal film 3 and the barrier metal film 4 is formed.

On the other hand, metal wiring patterns 13 and 83 are formed on the lower surface of the memory wafer 10 and the ASIC wafer 80 (the surface facing the interposer 1). The metal wiring pattern 13 of the memory wafer 10 is connected to the metal wiring pattern 3 of the interposer 1 via the micro bumps 11. The metal wiring pattern 83 of the ASIC wafer 80 is connected to the metal wiring pattern 3 of the interposer 1 via the micro bumps 81. Thus, the memory chip 10 and the ASIC chip 80 are respectively via the micro bumps 11 and 81. Mounted on the interposer 1 in a flip-chip manner.

FIG. 3 is a block diagram showing the configuration of the memory chip 10. The memory chip 10 includes: a selection circuit 14 that selects one of the signals input from the microbumps 11 and the probe pads 12; a memory circuit 20 that includes the DRAM 21; and a selection circuit 15 that will be used by the memory The output destination of the signal supplied from the circuit 20 is switched to the microbump 11 or the probe pad 12.

The selection circuit 14 selects the signal input to the microbump 11 when the test enable signal TEN is at the L level, and selects the test signal input to the probe pad 12 when the test enable signal TEN is at the H level. Further, the selection circuit 14 of the A region shown in FIG. 3 is connected to one microbump 11, and the selection circuit 14 of the B region is connected to the plurality of microbumps 11.

The selection circuit 15 selects the microbump 11 as the output destination of the signal when the test enable signal TEN is at the L level, and selects the probe pad 12 as the output destination of the signal when the test enable signal TEN is at the H level. Further, the selection circuit 15 of the C area shown in FIG. 3 is connected to one microbump 11, and the selection circuit 15 of the D area is connected to the plurality of microbumps 11.

[Configuration Example 1 of Input Side: Parallel Mode]

4 is a view showing the configuration of the input side of the memory chip 10. 10 memory chips comprising: latch circuits 22A ~ 22N, which via the micro-bump line 11A _in the latch signal inputted by the ~ 11N _in; a latch circuit 22X, which latches the input lines via the micro bumps 11 _SDATA Test signal; buffer circuit 23, which buffers test enable signal TEN; selector 24A, which selects test signal; selectors 27A-27N, which select signals or test signals input via microbumps 11 And buffer circuits 28A~28N.

The latch circuits 22A to 22N and 22X and the buffer circuit 23 are supplied with a voltage VDDQ from a first power supply circuit (not shown). Further, the selectors 24A, 27A to 27N and the buffer circuits 28A to 28N are supplied with a voltage VDD from a second power supply circuit (not shown). Here, since the selectors 24A and 27A to 27N have the same configuration, the configuration of the selector 24A will be described as an example.

Fig. 5 is a logic circuit showing the configuration of the selector 24A. Fig. 6 is a table showing the truth value of the input and output of the selector 24A. The selector 24A includes three NAND circuits 31, 32, 34 and a NOT circuit 33.

The NAND circuit 32 calculates the NAND (negative product) of the binary data of the input B terminal and the S terminal, and outputs the binary data N2. The negative circuit 33 calculates the NOT (negative) of the binary data of the input S terminal, and outputs the binary data SB.

The NAND circuit 31 calculates the binary data of the input A terminal and the NAND of the binary data SB, and outputs the binary data N1. The NAND circuit 34 calculates the NAND of the binary data N1 and N2, and outputs the binary data from the Y terminal. Therefore, the selector 24A, as shown in FIG. 6, when the binary data of the input S terminal is L, the binary data of the input A terminal is output as it is; when the binary data of the input S terminal is H, the input B terminal is input. The binary data is output as it is.

(normal mode)

In the memory wafer 10 configured as above, when the test enable signal TEN is not input to any of the micro bump 11 _TEN-in and the probe pad 12 _TEN-in (the test enable signal TEN is L level) In other words, the selectors 24A and 27A to 27N are in a state in which the signal input to the A terminal is output as it is from the Y terminal. Therefore, inputs to the micro bumps 11A _in ~ 11N _in the signal, the latch circuit 22A ~ 22N, selectors 27A ~ 27N, the buffer circuits 28A ~ 28N, supplied to the respective terminals through the DRAM21.

(test mode)

In the test mode, the probe is brought into contact with the probe pad 12 _TEN-in , and the test start signal TEN of the H level is input to the probe pad 12 _TEN-in . At this time, the selectors 24A and 27A to 27N are in a state in which the signal of the input B terminal is output as it is from the Y terminal.

Then, when a test signal from the probe is input to the probe pad 12 _SDATA-in , the test signal is distributed in parallel to each of the selectors 27A to 27N via the selector 24A, and is input to the DRAM 21 via the respective buffer circuits 28A to 28N. Each terminal.

Therefore, after the memory chips 10 are distributed in parallel with the test signals, the test signals are supplied to the wirings connected to the microbumps 11A _in to 11B _in . Therefore, the memory chip 10 can simultaneously input the test signals input to the single probe pad 12 _SDATA-in to the respective terminals of the DRAM 21.

[Configuration Example 1 of Output Side: Parallel Mode]

Fig. 7 is a view showing the configuration of the output side of the memory chip 10. The memory chip 10 includes buffer circuits 61A to 61N for buffering signals output from respective terminals of the DRAM 21, and an arithmetic circuit 62 for performing specific calculation based on signals output from the respective buffer circuits 61A to 61N; The buffer circuits 65A to 65N buffer the signals output from the buffer circuits 61A to 61N, and the buffer circuit 65X buffer the signals output from the calculation circuit 62.

The calculation circuit 62 is based on the letters output from the buffer circuits 61A to 61N. The circuit in the memory chip 10 is inspected, for example, an AND circuit, an OR circuit, an XOR (exclusive logic sum) circuit, and the like, and is not particularly limited.

(normal mode)

In the memory wafer 10 constructed as above, when the test enable signal TEN is not input to any of the microbump 11 _TEN-out and the probe pad 12 _TEN-out (the test enable signal TEN is the L level) In other cases, the signals output from the respective terminals of the DRAM 21 are output to the interposer 1 via the buffer circuits 61A to 61N and the microbumps 11A _out to 11N _out .

(test mode)

When the test is performed on the input side, a signal reflecting the test signal is output from each terminal of the DRAM 21. These signals are supplied to the arithmetic circuit 62 via the respective buffer circuits 61A to 61N. The calculation circuit 62 performs a specific calculation based on the signals supplied from the buffer circuits 61A to 61N, and then outputs the calculation result via the buffer circuit 65X and the probe pad 12 _CK1-out (or the microbumps 11 _CK1-out ).

Therefore, in the memory chip 10, only the probe is touched to the probe pad 12 _CK1-OUT , and the signal output from the probe pad 12 _CK1-OUT is checked, and the memory of the DRAM 21 having a very large number of terminals can be inspected. The state of the wafer 10.

[Second Embodiment]

Next, a second embodiment of the present invention will be described. The same reference numerals are given to the same circuits as those of the first embodiment, and a circuit different from the first embodiment will be mainly described. In the second embodiment, another configuration example of the input side and the output side of the memory chip 10 will be described.

[Configuration Example 2 of Input Side: Tandem Mode]

FIG. 8 is a view showing the configuration of the input side of the memory chip 10. The memory chip 10 further includes a latch circuit 22Y that latches a clock input via the microbump 11 _SCLK-in , and a selector 24B that selects an input to the micro. Any one of the clock of the bump 11 _{SCLK-in and} the clock input to the probe pad 12 _SCLK-in ; and the flip-flop circuits 25A-25N, which delay each of the selected test signals by one Pulse.

The flip-flop circuits 25A to 25N are connected in series and synchronized with the clock supplied from the selector 24B. Then, after the flip-flop circuits 25B to 25N are synchronized with the clock, the test signals are supplied to the selectors 27B to 27N, and at the same time, the test signals are supplied to the flip-flop circuits of the lower stage. Further, since the flip-flop circuit 25A has no flip-flop circuit of the lower stage, the test signal is supplied to the selector 27A in synchronization with the clock.

(normal mode)

In the memory wafer 10 configured as above, when the test enable signal TEN is not input to any of the microbump 11 _TEN-in and the probe pad 12 _TEN-in (the test enable signal TEN is at the L level) The selectors 24A, 24B, and 27A to 27N are in a state in which the signal input to the A terminal is output as it is from the Y terminal. Therefore, the signals input to the respective microbumps 11 are supplied to the respective terminals of the DRAM 21 via the latch circuits 22A to 22N, the selectors 27A to 27N, and the buffer circuits 28A to 28N.

(test mode)

In the test mode, the probe is brought into contact with the probe pad 12 _TEN-in , and the test start signal TEN of the H level is input to the probe pad 12 _TEN-in . At this time, the selectors 24A and 27A to 27N are in a state in which the signal input to the B terminal is output as it is from the Y terminal.

Then, when a test signal from the probe is input to the probe pad 12 _SDATA-in , the selector 24A supplies a test signal to the flip-flop circuit 25N.

The flip-flop circuit 25N is synchronized with the clock supplied from the microbump 11 _SCLK-in , the latch circuit 22Y, and the selector 24B, and then supplies the test signal supplied from the selector 24A to the selector 27N while being down to the next stage. The flip-flop circuit supplies the test signal. Similarly, the flip-flop circuit 25B is supplied with the test supplied from the front-end flip-flop circuit to the selector 27B in synchronization with the clock supplied from the microbump 11 _SCLK-in , the latch circuit 22Y, and the selector 24B. The signal is supplied to the down-segment flip-flop circuit 25A.

As a result, test signals for delaying each of the respective clocks are supplied to the selectors 27A to 27N. These test signals are supplied to the DRAM 21 via the selectors 27A to 27N and the buffer circuits 28A to 28N.

As described above, when the memory chip 10 inputs a test signal to the probe pad 12 _SDATA-in , the test signals are shifted by one clock, and the test signals each shifted by one clock are supplied to the micro-convex. Each of the blocks 11A _in ~11B _in is wired. Thereby, the memory chip 10 can supply a test signal shifted by one clock to a plurality of wirings by inputting a test signal only to the single probe pad 12 _SDATA-in .

[Configuration Example 3 on the input side: parallel/serial combination mode]

FIG. 9 is a view showing the configuration of the input side of the memory chip 10. The memory chip 10 further includes a latch circuit 22Z that latches a mode signal input via the microbump 11 _SMODE-in , and a selector 24C that selects an input to the micro. The mode signal of the bump 11 _{SMODE-in and} the mode signal input to the probe pad 12 _SMODE-in ; and the selectors 26A-26N switch the signal to be output according to the mode signal.

In the mode signal, it is determined that a test signal (parallel mode) is distributed in parallel to each of the wires, or a signal of a test signal (serial mode) in which one clock is shifted by one is assigned to each of the wiring strings. For example, when the mode signal is L-level, it becomes a parallel mode, and when the mode signal is H-bit, it becomes a serial mode.

The A terminals of the selectors 26A to 26N are connected to the Y terminal of the selector 24B. The B terminals of the selectors 26A to 26N are connected to the output terminals of the flip-flop circuits 25A to 25N. The S terminals of the selectors 26A to 26N are connected to the Y terminal of the selector 24C.

(normal mode)

In the memory wafer 10 configured as above, when the test enable signal TEN is not input to any of the microbump 11 _TEN-in and the probe pad 12 _TEN-in (when the test enable signal TEN is at the L level), the selection is made. The devices 24A to 24C and 27A to 27N are in a state in which the signal input to the A terminal is output as it is from the Y terminal. Therefore, inputs to the micro bumps 11A _in ~ 11N _in the signal, the latch circuit 22A ~ 22N, selectors 27A ~ 27N, the buffer circuits 28A ~ 28N supplied to the respective terminals through the DRAM21.

(test mode)

In the test mode, the probe is brought into contact with the probe pad 12 _TEN-in , and the test start signal TEN of the H level is input to the probe pad 12 _TEN-in . At this time, the selectors 24A to 24C and 27A to 27N are in a state in which the signal input to the B terminal is output as it is from the Y terminal. Further, the selector 24C supplies a mode signal input to the probe pad 12SMODE to each of the S terminals of the selectors 26A to 26N.

Here, when the mode signal is at the L level, the selectors 26A to 26N are in a state in which the signals input to the A terminal are output to the selectors 27A to 27N, respectively. Further, when a test signal from the probe is input to the probe pad 12 _SDATA-in , the test signal is distributed in parallel to each of the selectors 27A to 27N via the selector 24A, and is input to each terminal of the DRAM 21 via each of the buffer circuits 28A to 28N. .

On the other hand, when the mode signal is at the L level, the selectors 26A to 26N are in a state in which the signals of the input B terminal are output to the selectors 27A to 27N, respectively. Further, when a test signal from the probe is input to the probe pad 12 _SDATA-in , the selector 24A supplies a test signal to the flip-flop circuit 25N.

The flip-flop circuit 25N is synchronized with the clock supplied from the microbump 11 _SCLK-in , the latch circuit 22Y, and the selector 24B, and then supplies the test signal supplied from the selector 24A to the selector 27N, and the next stage The flip-flop circuit supplies the test signal. Similarly, the flip-flop circuit 25B is synchronized with the clock supplied from the microbump 11 _SCLK-in , the latch circuit 22Y, and the selector 24B, and then supplied to the selector 27B by the test supplied from the front-end flip-flop circuit. The signal is supplied to the flip-flop circuit 25A of the lower stage.

As a result, test signals each delayed by one clock are supplied to the selectors 27A to 27N, respectively. These test signals are supplied to the DRAM 21 via the selectors 27A to 27N and the buffer circuits 28A to 28N.

As described above, the memory chip 10, to each micro-block 11A can be connected to each wiring _in the ~ 11N _in accordance with the test signal is supplied in parallel allocated test mode signal, or a signal supplied to the serial dispensing.

[Configuration Example 2 of Output Side: Tandem Mode]

FIG. 10 is a view showing the configuration of the output side of the memory chip 10. Memory crystal The slice 10 includes latch circuits 51A and 51B for latching specific signals, a buffer circuit 52 for buffering the test enable signal TEN, and selectors 53A and 53B.

The latch circuit 51A latches the clock input via the microbump 11 _SCLK-out , and supplies the clock to the A terminal of the selector 53A. The latch circuit 51B latches the mode signal input via the microbump 11 _SMODE-out , and supplies the mode signal to the A terminal of the selector 53B. The buffer circuit 52 supplies the test enable signal TEN to the S terminal of the selectors 53A, 53B after buffering the test enable signal TEN input to the microbump 11 _TEN-out or the probe pad 12 _TEN-out .

The selector 53A supplies the clocks input to the A terminal or the B terminal to the flip flop circuits 64A to 64N, respectively. The selector 53B supplies a mode signal input to the A terminal or the B terminal to the selectors 63B to 64N, respectively.

Further, the memory chip 10 includes buffer circuits 61A to 61N that buffer signals output from the respective terminals of the DRAM 21, selectors 63B to 63N, and flip-flop circuits 64A to 64N; and buffers are output from the respective buffer circuits 61A to 61N. The signal buffer circuits 65A to 65N; and the buffer circuit 65Y that buffers the signal output from the flip-flop circuit 64N.

The A terminal of the selector 63B is connected to the snubber circuit 61B, the B terminal thereof is connected to the output terminal of the flip flop circuit 64A, and the Y terminal thereof is connected to the input terminal of the flip flop circuit 64B. Further, the input terminal of the flip-flop circuit 64A is connected to the buffer circuit 61A.

Similarly, the A terminal of the selector 63N is connected to the buffer circuit 61N, the B terminal thereof is connected to the output terminal of the flip-flop circuit of the previous stage of the flip-flop circuit 64N, and the Y terminal thereof is connected to the input terminal of the flip-flop circuit 64N. Further, the input terminal of the flip-flop circuit 64A is connected to the buffer circuit 61A.

Thereby, the flip-flop circuits 64A to 64N are connected in series via the selectors 63B to 61N. Therefore, the flip-flop circuits 64A to 64N are shifted by one clock from the buffer circuit 61A, and then passed through the buffer circuit 65Y, the probe pad 12 _CK1-out (or the microbump 11 _CK1-out ). The output shift register functions (1st to 4th shift registers).

(normal mode)

In the memory wafer 10 configured as above, when the test enable signal TEN is not input to any of the microbump 11 _TEN-out and the probe pad 12 _TEN-out (when the test enable signal TEN is at the L level), The signals output from the respective terminals of the DRAM 21 are output to the interposer 1 via the buffer circuits 61A to 61N and the microbumps 11A _out to 11N _out .

(test mode)

In the test mode, the probe is brought into contact with the probe pad 12 _TEN-out , and the test start signal TEN of the H level is input to the probe pad 12 _TEN-out . Further, a signal reflecting the test signal is output from each terminal of the DRAM 21.

At this time, the selector 53A is in a state in which the clock of the input B terminal is output as it is from the Y terminal. The selector 53B is in a state in which the mode signal of the input B terminal is output as it is from the Y terminal.

Here, when the mode signal is at the L level, the selectors 63B to 63N output signals input to the A terminal. Therefore, the signals output from the buffer circuits 61A to 61N are held in the flip-flop circuits 64A to 64N. Next, when the mode signal is at the H level, the flip-flop circuits 64A to 64N function as shift registers (first to fourth shift registers). Therefore, the signals held by the flip-flop circuits 64A to 64N are synchronized with the clock and output via the buffer circuit 65Y and the probe pad 12 _CK2-out .

As described above, the memory chip 10 converts the signals output from the buffer circuits 61A to 61N into a series, and outputs them via the probe pads 12 _CK2-out . Thereby, the state of the DRAM 21 having a very large number of terminals can be easily inspected only by checking the signal output from the probe pad 12 _CK2-out .

[Configuration Example 2 of Output Side: Parallel/Parallel Combination Mode]

Fig. 11 is a view showing the configuration of the output side of the memory chip 10. The memory chip 10 shown in Fig. 11 is a combination of the components shown in Figs. 7 and 10 . Therefore, the memory chip 10 can check the state of the memory chip 10 in which the DRAM 21 having a very large number of terminals is housed only by inspecting the signal output from the probe pad 12 _CK1-OUT or from 12 _CK1-OUT .

Further, in the first and second embodiments, various configurations of the input side and the output side of the memory chip 10 are shown, but the configuration of the input side and the configuration of the output side can be arbitrarily combined. For example, configuration example 1 may be used on the input side, and configuration example 2 or 3 may be used on the output side. Further, the configuration of the input side and the output side of the ASIC chip 80 can be set in the same manner as in the first and second embodiments.

[Third embodiment]

Fig. 12 is a block diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention. The semiconductor integrated circuit includes an interposer 100, an ASIC wafer 200 (first semiconductor wafer) mounted on the interposer 100, and a memory wafer 300 (second semiconductor wafer).

The wirings of the interposer 100 are connected to the respective wirings of the ASIC wafer 200 via the micro bumps 101 to 114. Each of the wirings of the interposer 100 is connected to each wiring of the memory chip 300 via the micro bumps 121 to 127.

The ASIC chip 200 includes: latch circuits 201-205, 231, 241; buffer circuits 206-209, 211, 214, 221, 224, 233, 243, 246; flip-flop circuits 212, 222, 235, 245; 213, 223, 232, 234, 242, 244.

The memory chip 300 includes latch circuits 301 to 305, selectors 310, 320, 343, and 353, buffer circuits 311, 321, 342, 344, 352, and 354, and flip-flop circuits 312, 333, 341, and 351.

Here, for example, the selector 213 has a connector having an A and a B terminal as an input terminal and a Y terminal as an output terminal, and is configured in the same manner as in FIG. 5 . Further, for example, the selector 232 has a selector terminal 232 as an input terminal and a selector having Y0 and Y1 terminals as output terminals, and is configured as follows.

FIG. 13 is a logic circuit showing the configuration of the selector 232. Fig. 14 is a table showing the truth value of the input and output of the selector 232. The selector 232 includes two NAND circuits 35, 36, and three NOT circuits 37, 38, 39.

The NAND circuit 36 calculates the NAND (negative product) of the binary data input to the A terminal and the S terminal, and outputs the binary data N2. The negative circuit 37 calculates the NOT (negative) of the binary data of the input S terminal, and outputs the binary data SR.

The NAND circuit 35 calculates the binary data of the input A terminal and the NAND of the binary data SB, and outputs the binary data N1. The NOT circuit 38 calculates the NOT of the binary data N1 and outputs the binary data via the Y0 terminal. The NOT circuit 39 calculates the NOT of the binary data N2 and outputs the binary data via the Y1 terminal.

Thereby, the selector 232 is as shown in FIG. 14, when the binary data of the input S terminal is L, the binary data of the input A terminal is output from the Y0 terminal; the input S terminal When the binary data is H, the binary data input to the A terminal is output from the Y1 terminal.

Further, on the interposer 100 side shown in FIG. 12, the microbump 101 (test signal input microbump) is an electrode for inputting a test signal, which is connected to the flip-flop circuit 212 via the latch circuit 201 of the ASIC wafer 200. Input terminal. The microbumps 102 (first bumps for the first clock) are electrodes for inputting logic (ASIC wafer 200), which are connected to the clocks of the flip-flop circuits 212, 222, 235, and 245 via the latch circuit 202. Input terminal. The microbump 103 (the first mode signal microbump) is an electrode for inputting a mode signal for the logic (ASIC wafer 200), and is connected to the S terminals of the selectors 234 and 244 via the latch circuit 203.

The microbumps 104 (second bump microbumps) are electrodes for inputting clocks for a memory, and are connected to the memory chip 300 via the latch circuit 204, the buffer circuit 209, and the micro bumps 109 and 123. The microbump 105 (the second mode signal microbump) is an electrode for inputting a mode signal for the memory, and is connected to the memory chip 300 via the latch circuit 205, the buffer circuit 208, and the micro bumps 108 and 122.

The microbumps 106 are electrodes for inputting the test enable signal TEN, which are connected to the respective S terminals of the selectors 213, 223, 232, 242 via the buffer circuit 206. Furthermore, the microbumps 106 are connected to the memory chip 300 via the buffer circuits 206 and 207 and the micro bumps 107 and 121.

The A terminal of the selector 213 is connected to the buffer circuit 211, and the B terminal thereof is connected to the output terminal of the flip-flop circuit 212. The Y terminal of the selector 213 is connected to the memory chip 300 via the buffer circuit 214, the micro bumps 110 (the first output microbumps), and 124.

The A terminal of the selector 223 is connected to the buffer circuit 221, and the B terminal is connected. The output terminal of the flip-flop circuit 222. Further, the input terminal of the flip-flop circuit 222 is connected to the output terminal of the flip-flop circuit 212. Further, the Y terminal of the selector 223 is connected to the memory chip 300 via the buffer circuit 224, the micro bumps 111 (first output micro bumps), and 125.

The A terminal of the selector 232 is connected to the memory chip 300 via the latch circuit 231, the micro bumps 112 (first input microbumps) 126. The Y0 terminal of the selector 232 is connected to the buffer circuit 233, and its Y1 terminal is connected to the B terminal of the selector 234. The A terminal of the selector 234 is connected to the output terminal of the flip flop circuit 222, and the Y terminal thereof is connected to the input terminal of the flip flop circuit.

Similarly, the A terminal of the selector 242 is connected to the memory chip 300 via the latch circuit 241, the micro bumps 113 (first input microbumps), and 127. The Y0 terminal of the selector 242 is connected to the buffer circuit 243, and its Y1 terminal is connected to the B terminal of the selector 244. The A terminal of the selector 244 is connected to the output terminal of the front-end flip-flop circuit, and the Y terminal is connected to the input terminal of the flip-flop circuit 245. The output terminal of the flip-flop circuit 245 is connected to the microbump 114 via the buffer circuit 246.

On the other hand, on the side of the memory chip 300, the micro bumps 121 are connected to the respective S terminals of the selectors 310, 320, 343, and 353 via the latch circuit 301. The micro bumps 122 are connected to the respective clock input terminals of the flip-flop circuits 312, 333, 341, and 351 via the latch circuit 302. The microbump 123 is connected to the S terminal of the selector 322 via the latch circuit 303.

The micro bumps 124 and 125 (the second input microbumps of the plurality) are connected to the respective A terminals of the selectors 310 and 320 via the latch circuits 304 and 305, respectively. The micro bumps 126 and 127 (the second output microbumps of the plurality) are respectively passed through the buffer circuit 344, 354 is connected to each Y terminal of the selectors 343, 353.

The Y0 terminal of the selector 310 is connected to the buffer circuit 311, and its Y1 terminal is connected to the input terminal of the flip-flop circuit 312. The output terminal of the flip-flop circuit 312 is connected to the A terminal of the selector 322.

The Y0 terminal of the selector 320 is connected to the buffer circuit 321, and its Y1 terminal is connected to the input terminal of the flip-flop circuit 322. The output terminal of the flip-flop circuit 322 is connected to the input terminal of the flip-flop circuit 333.

The A terminal of the selector 343 is connected to the buffer circuit 342, and the B terminal thereof is connected to the output terminal of the flip-flop circuit 341. Similarly, the A terminal of the selector 353 is connected to the buffer circuit 352, and the B terminal thereof is connected to the output terminal of the flip-flop circuit 351.

(normal mode)

In the semiconductor integrated circuit constructed as above, when the test enable signal TEN is not input to the microbump 106 (when the test enable signal TEN is at the L level), the selectors 213 and 223 of the ASIC wafer 200 become signals from the input A terminal. The state of the Y terminal as it is output. Further, the selectors 232 and 242 are in a state in which a signal input to the A terminal is output from the Y0 terminal. Similarly, the selectors 310 and 320 of the ASIC wafer 200 are in a state in which a signal input to the A terminal is output from the Y0 terminal. Further, the selectors 343 and 353 are in a state in which the signal input to the A terminal is output as it is from the Y terminal.

Therefore, the signal output from the ASIC (not shown) of the ASIC chip 200 passes through the buffer circuit 211, the selector 213, the buffer circuit 214, the micro bumps 110, 124, the latch circuit 304, the selector 310, and the buffer circuit 311. A DRAM (not shown) that is supplied to the memory chip 300.

Further, the signal read from the DRAM of the memory chip 300 is supplied via the buffer circuit 342, the selector 343, the buffer circuit 344, the micro bumps 126 and 112, the latch circuit 231, the selector 232, and the buffer circuit 333. ASIC of ASIC wafer 200.

(test mode)

Figure 15 is a flow chart showing the test signals in the test mode. In the test mode, the H-level test enable signal TEN is input to the microbumps 106. Further, it is set to supply a specific clock (first to second clock signals) to the microbumps 102 and 104.

The selectors 213 and 223 of the ASIC chip 200 are in a state in which the signal input to the B terminal is output as it is from the Y terminal. Further, the selectors 232 and 242 are in a state in which a signal input to the A terminal is output from the Y1 terminal. Similarly, the selectors 310 and 320 of the ASIC chip 200 are in a state where the signal of the input A terminal is output from the Y1 terminal. Further, the selectors 343 and 353 are in a state in which the signal input to the B terminal is output as it is from the Y terminal.

Then, when a test signal is input to the microbump 101, a test signal (arrow A) is sequentially held in the flip-flop circuits 212 and 222.

Then, if the H-level memory mode signal is input to the microbump 105, the test signal held in the flip-flop circuit 212 is held in the positive and negative directions via the selector 213, the micro bumps 110, 124, and the selector 310. Circuit 312. Similarly, the test signal held in the flip-flop circuit 222 is held in the flip-flop circuit 333 (arrow B) via the selector 223, the micro bumps 111, 125, and the selectors 320, 322.

Then, when the L mode memory mode signal is input to the microbump 105, the selector 322 supplies the flip flop circuit 333 to the flip flop circuit 312. Test signal. That is, the test signals held in the flip-flop circuits 312, 333 are shifted to the flip-flop circuit (arrow C) of the next output object.

Then, if a logic level mode signal of the H level is input to the microbump 103, for example, the test signal held in the flip flop circuit 341 is held by the selector 343, the micro bumps 126, 112, and the selectors 232, 234. The flip-flop circuit 235. Further, the test signal held in the flip-flop circuit 351 is held in the flip-flop circuit 245 (arrow D) via the selector 353, the micro bumps 127, 113, and the selectors 242, 244.

Then, when the logic mode signal of the L level is input to the microbump 103, the selectors 234 and 244 are in a state where the signal of the input A terminal is output from the Y terminal. Thereby, the test signals held in the flip-flop circuits 235 and 245 are sequentially shifted to the flip-flop circuits of the lower stage. As a result, the test signal output from the flip-flop circuit 245 is output via the buffer circuit 246 and the microbump 114 (test signal output microbump) (arrow E).

Therefore, the inspection device (not shown) can inspect the wiring conditions in the ASIC wafer 200 and the memory chip 300 by inspecting the test signals outputted from the micro bumps 114, and can also check the wiring condition between the micro bumps.

[Other composition]

Fig. 16 is a view showing another configuration of a semiconductor integrated circuit according to a third embodiment of the present invention. The same reference numerals are given to the same circuits as those in Fig. 12, and mainly differences from Fig. 12 will be described.

The microbumps 106 shown in FIG. 12 are replaced with an interposer 100 having microbumps 106a, 106b. The microbump 106a is an electrode for inputting the test enable signal TEN for the memory, via the latch circuit 210, the buffer circuit 209, The microbumps 109 are connected to the microbumps 123. The microbumps 106b are electrodes for inputting the logic test enable signal TEN, and are connected to the respective S terminals of the selectors 213, 223, 232, and 242 via the buffer circuit 206. Thereby, the ASIC wafer 200 shown in FIG. 16 is compared with FIGS. 12 and 15, although the number of input test enable signals TEN is different, the other processes are the same.

On the other hand, on the memory chip 300 side, the microbumps 121 are connected to the S terminal of the selector 322 via the latch circuit 301. The microbumps 123 are connected to the S terminals of the selectors 310, 320, 343, 353 via the buffer circuit 307.

(test mode)

When the H-level memory test enable signal TEN is input to the microbump 106a, the selectors 310 and 320 are in a state where the signal of the input A terminal is output from the Y1 terminal. Further, the selectors 343 and 353 are in a state in which a signal input to the B terminal is output from the Y terminal.

At this time, the test signal held in the flip-flop circuit 212 is held in the flip-flop circuit 312 via the micro bumps 110, 124 and the selector 310. Similarly, the test signal held in the flip-flop circuit 222 is held in the flip-flop circuit 333 via the micro bumps 111, 125.

Further, when the logic level signal of the H level is input to the microbump 105, the selector 322 is in a state of outputting the signal of the input B terminal. At this time, the test signals held in the flip-flop circuits 312, 333 are shifted to the flip-flop circuit of the next output object.

As described above, the ASIC wafer 200 sequentially scans and shifts the test signal held by the flip-flop circuit, and after scanning the shift test signal, transmits a test signal to the ASIC wafer 200 as in the case of FIGS. 12 and 15.

As described above, in the semiconductor integrated circuit of the third embodiment, the test signal is scanned and shifted in the ASIC wafer 200, and is transmitted to the memory chip 300 via the micro bumps. Furthermore, the semiconductor integrated circuit scans and shifts the test signal in the memory chip 300, transfers it to the ASIC wafer 200 via the micro bumps, scans and shifts again in the ASIC wafer 200, and then passes through the micro bump 114. External output. Therefore, by examining the test signal output from the microbumps 114, it is possible to check the overall wiring condition including the connection condition between the micro bumps.

As described above, the wafer test (the first and second embodiments) of the semiconductor wafer connected via the interposer by the micro bumps and the test after the assembly (the third embodiment) can be efficiently performed. In particular, it is possible to efficiently test a semiconductor integrated circuit in which a semiconductor wafer having a multi-bit width is mounted.

Further, the present invention is not limited to the above-described embodiments, and it is of course also applicable to those who have made design changes within the scope described in the scope of the patent application.

For example, in the third embodiment, the test enable signal TEN, the mode signal and the pulse are input to the ASIC wafer 200, but may be input to the memory chip 300.

Further, in the first to third embodiments, the number of probe pads is not particularly limited as long as the number of the microbumps is small.

1, 100‧‧‧Intermediary

10, 300‧‧‧ memory chip

11‧‧‧Microbumps

12‧‧‧ probe pad

80,200‧‧‧ASIC chip

Figure 1 is a plan view of a semiconductor integrated circuit.

Figure 2 is a cross-sectional view taken along line I-I of Figure 1.

Figure 3 is a block diagram showing the construction of a memory chip.

Fig. 4 is a view showing the configuration of the input side of the memory chip.

Fig. 5 is a logic circuit showing the configuration of a selector.

Figure 6 is a table showing the truth values of the input and output of the selector.

Fig. 7 is a view showing the configuration of the output side of the memory chip.

Fig. 8 is a view showing the configuration of the input side of the memory chip.

Fig. 9 is a view showing the configuration of the input side of the memory chip.

FIG. 10 is a view showing the configuration of the output side of the memory chip 10.

Fig. 11 is a view showing the configuration of the output side of the memory chip 10.

Fig. 12 is a block diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention.

Figure 13 is a logic circuit showing the construction of a selector.

Figure 14 is a table showing the truth values of the input and output of the selector.

Figure 15 is a flow chart showing the test signals in the test mode.

Fig. 16 is a view showing another configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

10‧‧‧ memory chip

11A _in ~11N _in ‧‧‧ micro-bumps

11 _SDATA-in ‧‧‧ micro-bumps

11 _TEN-in ‧‧‧ micro-bumps

12 _SDATA-in ‧‧‧ probe pad

12 _TEN-in ‧‧‧ probe pad

21‧‧‧DRAM

22A~22N‧‧‧Latch circuit

22X‧‧‧Latch circuit

23‧‧‧ snubber circuit

24A‧‧‧Selector

27A~27N‧‧‧Selector

28A~28N‧‧‧ buffer circuit

VDD‧‧‧2nd power supply circuit supply voltage

VDDQ‧‧‧1st power supply circuit supply voltage

Claims (2)

A semiconductor integrated circuit characterized in that a first semiconductor wafer and a second semiconductor wafer each having a plurality of micro bumps arranged at a minimum pitch of 100 μm or less are mounted in an interposer; The first semiconductor wafer includes: a test signal input microbump, which inputs a test signal; a first clock microbump, which inputs a first clock signal; and a first mode signal microbump, which is input 1 mode signal; a plurality of first output microbumps for outputting data; a plurality of first input microbumps for inputting data; and a first shift register containing positive and negative of plural numbers And the flip-flops are disposed corresponding to each of the first output microbumps, and maintain a test signal input to the microbump via the test signal, and output the held test signal to each of the corresponding first outputs. The micro bump and the flip-flop of the lower stage shift the held test signal to the flip-flop of the lower stage when the first clock signal is input through the first bump for the first clock; the second shift is temporarily stored a device comprising a plurality of flip-flops, The isolator is provided corresponding to each of the first input microbumps, and when the first mode signal is input via the first mode signal microbump, the first input micro through each of the corresponding first input micro a test signal input by the bump, and outputting the held test signal to the flip-flop of the lower stage, and inputting the first clock signal by using the micro-bump of the first clock And shifting the held test signal to the flip-flop of the lower stage; and the test signal output microbump, which outputs a test signal shifted from the second shift register; the second semiconductor wafer includes : a second bump with a microbump, which inputs a second clock signal; a second mode signal with a microbump, which inputs a second mode signal; and a plurality of second input microbumps, which are used for Data from the respective outputs of the first output microbumps are input via the interposer; a plurality of second output microbumps are used to output data to each of the first input microbumps via the interposer; a third shift register comprising a plurality of flip-flops, wherein the flip-flops are provided corresponding to each of the second input micro-bumps, and the second flip-chip is input via the second mode signal micro-bumps In the case of the mode signal, the test signal input via each of the corresponding second input microbumps is held, and the held test signal is output to the flip-flop of the lower stage, and the micro-bump is input through the second clock. When the 2nd clock signal is shifted, the test signal is kept shifted a flip-flop of the lower stage; and a fourth shift register comprising a plurality of flip-flops, wherein the flip-flops are disposed corresponding to each of the second output micro-bumps, and are retained from the third shift temporarily a test signal after the register is shifted, and the held test signal is output to each of the corresponding second output microbumps and the lower flip-flops, and the second time is input through the second clock microbumps. a pulse signal, shifting the held test signal to the flip-flop of the lower stage; and the above semiconductor integrated circuit The wiring connection may be checked according to a test signal outputting the microbump output from the test signal, and the wiring connection includes a connection state between the first output microbump and the second input microbump, and the second output micro The connection between the bump and the first input microbump. The semiconductor integrated circuit of claim 1, wherein each of the first semiconductor wafer and the second semiconductor wafer which are flip-chip mounted on the interposer has a multi-bit width of 256 bits or more.