TW538526B - Semiconductor chip, semiconductor integrated circuit device using the same, and method of selecting semiconductor chip - Google Patents

Abstract

Semiconductor chips mounted in a laminated manner on a substrate and a semiconductor integrated circuit device using the semiconductor chips. A predetermined semiconductor chip is selected by chip selection signals from an external unit despite the chips having the same wiring pattern are laminated in a plural number one upon the other. The semiconductor integrated circuit device is fabricated by using such semiconductor chips. The semiconductor chip comprises a plurality of first electrode terminals arranged on a front surface maintaining a predetermined pitch to receive reference signals for producing comparison signals that are to be compared with chip selection signals in a comparator circuit to select a chip, a plurality of second electrode terminals arranged on a back surface opposed to the front surface each being deviated by one pitch from the plurality of the first electrode terminals to output the reference signals input to the first electrode terminals, and connection portions for electrically connecting the first and second electrode terminals that are deviated by the one pitch.

Description

538526 V. Description of the Invention (Field of the Invention) The present invention relates to a semiconductor wafer formed on a substrate, a semiconductor integrated circuit element using the semiconductor wafer, and a method for selecting a semi-conductor wafer. [Know-how] In recent years, semiconductor integrated circuit components have been implemented in a highly integrated form and a SOC (system-on-chip system; system_〇n_chip) form, especially semiconductor integrated circuits have been manufactured in a multi-chip form A plurality of semiconductor wafers, one on top of the other, are made into thin sheets by relying on a wafer mounting technique. The wafer mounting method for realizing the multi-chip element can be expressed by a super-connection technology, by which a plurality of electrode terminals are arranged on the surface of a semiconductor wafer, and the semiconductor wafers are one on the other Sheets are made and connected together via electrode terminals. Putting this hyperconnected technology into practical use has promoted research, and research has been expected to be the next technology to emerge. For example, a plurality of semiconductor wafers forming a memory circuit are thinly formed on top of each other by the super-connection technology in order to obtain a high-density and large-capacity memory. Generally, a large storage amount of memory formed by using a super-connection technology has a structure in which the semiconductor wafers are thinly formed on one another through bumps to form a plurality of layers. The same wiring pattern for terminals and circuit components. When the semiconductor wafers are formed into thin sheets to form the plurality of layers, the signal system must be used to select a wafer in operation in order to write or read the data. When all the semiconductor wafers made into thin sheets have the same wiring pattern, however, the size of the paper used to receive the crystalline paper is subject to the Chinese National Standard (CNS) A4 specification (210X297 mm). 4. Explanation of the invention: () 2 The positions of the electrode terminals of the selection signal become all-in-one, allowing the same crystal selection to enter each semiconductor wafer, which makes it difficult to select a wafer in operation. There are two ways to avoid this problem. According to the first method, the plurality of conductor wafers are prepared by disengaging the electrode terminals receiving the wafer selection signals by using a plurality of exposure mask-on-photolithography steps with different circuit patterns. it is good. Then, these semiconductor anodes are made of bumps on a substrate, and a selection signal is continuously output from the substrate to the electrode terminals that receive the wafer selection signals of the semiconductor wafers, thereby Chip selected in operation. According to a second method, a plurality of semiconductor wafers are prepared by forming the same wiring pattern, and a part of the wiring pattern of each semiconductor wafer is irradiated with a laser beam to form electrode terminals which are disengaged in order to receive a wafer selection signal. . These semiconductor wafers are sliced on the bottom via bumps, and a selection signal is continuously output from the substrate to the electrode terminals that receive the wafer selection signals of the semiconductor wafers, thereby selecting the wafer in operation. . y However, this first method requires a plurality of circuit designs and a plurality of expensive masks for exposure, and furthermore, an increased number of photolithography steps are required. With a laser beam, the second method requires a step of cutting the wiring pattern. Therefore, either method requires an increased number of manufacturing steps to increase manufacturing costs. [Summary of the Invention] An object of the present invention is to provide a semiconductor wafer which enables a predetermined wafer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm).

Can be from one

Tablet method. #Although the crystals are selected into thin slices, a use is provided for a choice of a semiconductor crystal

Off the hook. [Brief description of the diagram] FIG. 1 is a cross-sectional view illustrating the structure of a semiconductor integrated circuit element according to a first embodiment of the present invention; FIG. 2 is a diagram illustrating a semiconductor wafer according to the first embodiment of the present invention. A schematic diagram of the main part of the circuit structure; FIG. 3 is a cross-sectional view illustrating a part of the structure of the semiconductor wafer according to the first embodiment of the present invention; and FIG. 4 is a schematic view illustrating a first embodiment of the present invention. A cross-sectional view of a semiconductor integrated circuit element for selecting a logic circuit of a semiconductor wafer; and FIG. 5 is a cross-sectional view illustrating a structure of the semiconductor integrated circuit element according to a second embodiment of the present invention. [Detailed description of the preferred embodiment] This paper size applies to China National Standard (CNS) A4 (210X297 mm) -6- 538526

5. Description of Invention 4) A semiconductor wafer, a semiconductor integrated circuit element using the semiconductor wafer, and a method for selecting a semiconductor wafer according to a first embodiment of the present invention will now be described with reference to FIGS. 1 to 4. Fig. 丨 is a cross-sectional view schematically illustrating a structure of a semiconductor integrated circuit element according to a first embodiment of the present invention. As shown in Fig. 1, three semiconductor wafers 4, 5, and 6 are formed into a sheet on a substrate 2 in this order. The semiconductor integrated circuit element according to this embodiment is about a DRAM (Dynamic Random Access Memory) having three banks composed of semiconductor wafers 4, 5, and 6. A plurality of electrode terminals are arranged in a matrix form on the upper and lower surfaces of the semiconductor integrated circuit element. However, FIG. 1 and the subsequent cross-sectional views are a plurality of electric extremes along a predetermined line or a row. Fig. 2 is a schematic diagram showing the circuit structure of the main parts of the semiconductor wafers 4, 5, and 6 according to the first embodiment of the present invention. As shown in FIG. 2, the semiconductor wafers 4, 5, and 6 each have a memory cell portion 52, and a plurality of memory cell 58 (only one system) are formed in the memory cell portion 52. (Not shown in Fig. 2) Each is composed of a transistor 60 for switching gates and a capacitor 62 in the form of a matrix. In the memory cell 58, a plurality of word lines 54 (only one of which is shown in FIG. 2) is extended in the column direction (in the left-right direction in the drawing) and a plurality of bit lines 56 (where Only one line is shown in Figure 2) extending in the row direction (up and down in the figure). The gate electrodes of the transistors 60 of the memory cell 58 arranged in the same column direction are connected to the same word line 54, and the transistors of the π helium delta memory cell 5 8 arranged in the same direction are arranged. The anodic electrode of 60 is connected to the same bit line 56. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Please read the back first-of-note the matters ·

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V. Description of the invention <) Therefore, due to the increase in the number of thin layers of the semiconductor wafer, the number of electrode terminals 27c, 27d used for the wafer selection signal must be increased in accordance with the number of electrode terminals used for the reference signal. The semiconductor wafer 4 according to this embodiment is made into a thin sheet on the substrate 2 on the front surface of the semiconductor wafer 4 (on the lower side of the illustrated embodiment and on the lower side of the illustrated embodiment), in the On the left side of the figure, electrode terminals 28a and 28b are arranged for the reference signal to maintain a pitch p. On the right side of the electrode terminal 28b, electrode terminals (first electrode terminals) 28 and 28 (1 are used for wafer selection signals in this order. On the right side of the electrode terminal 28d, electrode terminals Me to 28η are arranged. The electrode terminals 28e to 28n are arranged so that, relative to the electrode terminals 273 to 2711 of the substrate 2, the semiconductor wafer 4 is adhered to the substrate 2 via a plurality of bumps 12a to 12n as a wafer connecting member. Therefore, the electrode terminals 28as28n of the semiconductor wafer 4 are electrically connected to the electrode terminals 27a to 27η of the substrate two respectively. It is expected that the electrode terminals for the reference signal are grounded via the bumps 12a and are used for the reference signal. The extreme terminal 28b is grounded via a bump. The electrode terminals 28a, -28n are arranged on the rear surface (upper side in the figure) of the semiconductor wafer 4 for reference to the electrode terminals (second electrode terminals) 28a of 彳 s, And 28b 'are arranged on the surface relative to the electrode terminals "a and 28b for reference signals, and are arranged away from the positive track at a distance toward the right side of the figure. Therefore, the electrode terminal 28a is arranged on the rear surface, not Relative to the front surface The electrode terminal 28a is deviated from the electrode terminal 28a by a distance relative to the electrode terminal 28b. The electrode terminal 28a is connected to the electrode terminal 28a 'through a connection portion, and the electrode terminal 28b is connected through a connection portion. The terminal 29b is electrically connected to the electric device 5. The terminal 29b is grounded via the bump 13b, the connecting portion 8a, and the bump 12a. Furthermore, the semiconductor wafer 6 made into a thin sheet on the semiconductor wafer 5 has a The structures are the same as those of the semiconductor wafers 4 and 5. The electrode terminals 30a to 30n are formed in the same manner as the electrode terminals 28 &amp; to 28n on the front surface of the semiconductor wafer 4 and as in the semiconductor wafer 5 The method of the electrode terminals 29a to 29n on the front surface is arranged on the front surface of the semiconductor wafer 6. On the rear surface of the semiconductor wafer 6, the electrode terminals 28a are formed on the rear surface of the semiconductor wafer 4 in the same manner. The method from 28 to 28 η is arranged in the same way as the electrode terminals 29 a to 29 η formed on the rear surface of the semiconductor wafer 5, and the electrode terminals 30 a ′ to 30 η are arranged. The semiconductor wafer 5 and the semiconductor wafer 6 pass through Several The blocks 14a to 14η are glued together. Therefore, the electrode terminal 30b on the front surface of the semiconductor wafer 6 is electrically connected to the electrode terminal 29a on the rear surface of the semiconductor wafer 5. Similarly, the rear surface of the semiconductor wafer 6 The electrode terminals 30c to 30η on the above are respectively electrically connected to the electrode terminals 29c to 29η on the rear surface of the semiconductor wafer 4. At this time, the reference signals on the front surface of the semiconductor wafer 6 are The electrode terminals 30a and 3Ob are not connected to the grounded electrode terminal 29b. Therefore, neither the electrode terminal 30a nor the electrode terminal 30b is grounded. The electrode terminal 28b on the rear surface of the semiconductor wafer 4 is a non- The connection terminal; that is, the electrode terminal without any electrode terminal 28b connected thereto is disposed on the semiconductor wafer 5 with respect to the electrode terminal 28b. Similarly, the electrode terminal 29b on the rear surface of the semiconductor wafer 5, the electrode terminal 29 on the front surface of the semiconductor wafer 5, and the electrode terminal 30a on the front surface of the semiconductor wafer 6 are non-connecting terminals without any opposite electrode terminals. 538526

Description of the invention (please read the precautions on the back before filling in this page) Figure 3 is a part of the semiconductor wafer shown in Figure 丨. The cross-sectional view is under enlarged scale and is relative to the semiconductor wafer shown in Figure 1. The arrangement of 4 is reversed. Fig. 3 illustrates the structure of the electrode terminals 2a, 2a, 28a ', 28b' used as reference signals, and the cores and ribs of the connection portion of the semiconductor wafer 4. As shown in FIG. 3, an insulating film 22 is formed on a silicon substrate 20 of a silicon type. In the Si substrate 20 and in the insulating film 22, two via holes 24a and 24b are formed to penetrate the Si substrate 20 and the insulating film 22 to maintain a pitch p, and a connection conductor such as a copper (Cu) system Buried in these vias and 24b. The connecting conductor in the via hole 24a, the exposed surface on the surface side after the &amp; substrate 20 serves as the electrode terminal 28a. Similarly, the connecting conductor in the via hole 24b, the exposed surface of the Si substrate 20 after the surface side is used as the electrode terminal 28b '. The electrode terminals 28a, and 28b may be provided with pads for connecting the bumps. On the insulating film 22, wirings 26a and 26b of aluminum (Ai), Cu, or the like are formed. The wiring 26a is electrically connected at one end to the connection conductor in the via hole 24a and at the other end. The arrangement is offset from the electrode terminal 28a 'toward the right in the drawing at a half pitch. Similarly, the wiring 26b is electrically connected to the connection conductor in the via hole 24b at one end thereof and is arranged at the other end thereof to be offset from the electrode terminal 28b at a half pitch toward the right in the drawing. An insulating film 31 is formed on the entire surface of the wirings 2 ^ and 26b. The insulating film 31 has a via hole 3 2a in which an opening is opened at the other end of the wiring 26a, and a via hole 32b is formed therein. The other end of the connection 2 is open. Similar to these vias 24a and 24b, for example, Cu's connection guide system is buried in these vias 32a and 32b. At this via 32a, the Chinese paper standard (CNS) A4 specification (210X297 mm) applies. ) -12-538526 5. The connection guide system in the description of the invention (0) is electrically connected to the wiring—and the connection guide system in the via 32b is electrically connected to the wiring 26b. The wirings 34a and 34b are formed on the front surface (upper side in the drawing) of the semiconductor wafer 4 on the insulating film 22. The wiring 34 is electrically connected to the connection conductor in the via 32a at one end thereof and is arranged at the other end thereof with a distance from the electrode terminal 28a toward the right in the drawing. Similarly, the wiring 34b is electrically connected at one end to the connecting conductor in the hole of the via 3 and is arranged at the other end to be offset from the electrode terminal 28b at a distance toward the right in the drawing. The other end of the wiring 34a serves as the electrode terminal 28a, and the other end of the wiring 341) serves as the electrode terminal 28b. The connection portion 8a is composed of the connection conductors in the vias 24a, 32a and the wirings 26a, 34a. In addition, the connection part 讣 is formed by the vias of the vias, the connection conductors in ^^, 32b, and the 4 wirings 26b, 34b. As will be explained later with reference to FIG. 4, the connection sections 8 &amp; and Pak output a comparison signal to the lucky circuit ′. However, FIG. 3 does not show the wiring for outputting the comparison signals. Next, referring to FIG. 4, it is a cross-sectional view schematically illustrating a circuit structure for selecting a semiconductor wafer in a semiconductor integrated circuit element according to this embodiment, and a circuit structure of a semiconductor integrated circuit element according to this embodiment will be explained. As shown in FIG. 4, the semiconductor wafers 4, 5, and 6 are thinly formed on the substrate 2 in this order. The electrical connection from the substrate 2 to the semiconductor wafers 4, 5, and 6 has been described with reference to FIG. 1 and will not be repeated here, but the circuit structure in these wafers will be explained. First, a wafer selection signal S 〇 is output from the electrode terminal 27c for the wafer selection signal on the substrate 2 and the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -13- 538526 A7 B7 Description of the fifth invention The chip selection signal S1 is output from the electrode terminal 2 7 d for a chip selection signal. The connecting portions 8a and 8b of the semiconductor wafer 4 are respectively connected to a power source Vd 'via a lifting resistor 70 formed in the wafer, and the connecting portion 8a is grounded via the bump 12a and held at a low (L ) Level of potential. Therefore, the connection portion 8a outputs an L-level comparison signal. Similarly, the connection portion 8b is grounded via the bumps 2b and held at a low (L) level. Therefore, 'the connecting portion 8b outputs an L-level comparison signal. That is, the two comparison signals of the L_ level are generated from the semiconductor wafer 4. A comparator circuit composed of two mutually exclusive anti-NOR circuits (Ex-NOR) circuits 72, 73 and a reverse-AND circuit (NADN) circuit 74 is formed on the semiconductor wafer 4, and the connection portion 8a is connected to the semiconductor wafer 4. An input terminal of the Ex-NOR circuit 72, and the connection portion 8b is connected to an input terminal of the Ex-NOR circuit 73. The connection portion 9c is connected to the other input terminal of the Ex-NOR circuit 73, and the connection portion 9d is connected to the other input terminal of the Ex-NOR circuit 72. The output terminal of the Ex-NOR circuit 72 is connected to an input terminal of the NAND circuit 74 and the output terminal of the Ex-NOR circuit 73 is connected to the other input terminal of the NAND circuit 74. An output signal S2 It is output from the nand circuit 74. When the input signal S2 is assumed to be the L-level, the semiconductor wafer 4 operates as an operation wafer, and the memory circuit in the semiconductor wafer 4 receives different instructions and data via predetermined electrode terminals. As in the semiconductor wafer 4, the semiconductor wafer 5 is formed with two mutually exclusive anti-OR circuits (Ex-NOR) circuits 75'76 and one receiving output signals from the two Ex-NOR circuits 75, 76. Reverse Gate (NADN) Circuit 77 This paper is sized for the Chinese National Standard (CNS) A4 (210 X 297 male diamond) Please read-Read the back '. Note,

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-14- 538526 A7 —____ B7_ V. Description of the invention (3) (Please read the precautions on the back before filling this page) According to the description of this embodiment. First, the case where the wafer selection signal training and S1 output the wafer selection signal for the substrate 2 from the electrode terminals 27c and 27d will be described below. One is assumed to be the L-level (0). An L-level comparison signal is input from the connecting portion 8a to an input terminal of the Ex-nor circuit 72 of the semiconductor wafer 4, and an L-level wafer selection signal S1 is from the connecting portion 9d. Is input to the other input terminal. Therefore, the output signal of the Ex_nOR circuit 72 is assumed to be the H-level. On the other hand, a comparison signal of a level is input from the connection portion 8b to an input terminal of the Ex-NOR circuit 73, and a chip selection signal S0 of the L-level is input from the connection portion 9c to the The other input. Therefore, the output signal of the Ex-NOR circuit 73 is assumed to be H-level. An H-level signal is input from the Ex-NOR circuit 72 to an input terminal 'of the NAND circuit 74 and an H-level signal is input from the Ex-NOR circuit 73 to the other input terminal. Therefore, the output signal S2 of the NAND circuit 74 is assumed to be the L-level. An H-level comparison signal is input from the connection portion 14 to an input terminal of the Ex-NOR circuit 75 in the semiconductor wafer 5, and an L-level wafer selection signal S1 is input from the connection portion I6d. Input to this other input. Therefore, the output signal of the Ex-NOR circuit 75 is assumed to be an L-level. On the other hand, an L-level comparison signal is input from the connection portion 15b to an input terminal of the Ex-NOR circuit 76, and an L-level wafer selection signal S0 is input from the connection portion 16c to The other input. Therefore, the output signal of the eX-nOR circuit 76 is assumed to be H-level. An L-level signal is input from the Ex-NOR circuit 75 to an input terminal of the NAND circuit 77, and an H-level signal is input from the Ex_nor circuit 76 to the other input. This paper size applies China National Standard (Q ^ S) A4 specification (21 × 297 mm) 538526 A7 B7 V. Description of the invention (4 terminals so 'the NAND circuit 77's round-out signal S3 is assumed to be the standard. (Please read the note on the back first (Please fill in this page again for more details). The comparison signal of Η-level is input from the connection part i7a to an input terminal of the Ex_dirty circuit 78 in the semiconductor wafer 6, and the level is selected. No. si is input to the other input terminal from the connecting portion 18d, so 'the output signal of the Ex-NOR circuit 78 is assumed to be the L_ level. On the other hand, a comparison signal of the H-level is taken from the connecting portion 17b. It is inputted to one input terminal of the Ex-NOR circuit 79, and the _1 • level chip selection signal so is inputted from the connection portion 18c to the other input terminal. Therefore, the output signal of the Ex_nor circuit 79 is assumed Is the L level. —L_ The level signal is input from the Ex-NOR circuit 78 to an output of the NAND circuit 80. And an L-level signal is input from the Ex_NOR circuit 79 to the other round-in terminal. Therefore, the output signal S4 of the NAND circuit 80 is assumed to be the H_ level. Although the chip selection signal S〇 When s1 is assumed to be L_level as described above, only the output signal S2 from the semiconductor wafer 4 is assumed to be L_level, and the semiconductor wafer 4 is selected as the operation wafer. Next, the following description will be made from the electrode terminal. The wafer selection signal S0 output from 27c is assumed to be the L-level, and the wafer selection signal S1 output from the electrode terminal 27d is assumed to be the H-level (1). A comparison signal of the ^ level is from this connection The portion 8a is input to one input terminal of the Ex_nOR circuit 72 of the semiconductor wafer 4, and an H-level wafer selection signal S1 is input from the connection portion% to the other input terminal. Therefore, the Ex The output signal of the -NOR circuit 72 is assumed to be L·level. On the other hand, a comparison signal of L_level is input from the connecting portion 8b to an input terminal of the Ex-NOR circuit 73, and a ^ A standard wafer selection signal S0 is inputted from the connection portion 90 to the other input terminal. -17- 538526 A7 -------- B7___ 5. Description of the invention (5) Therefore, the output signal of the Ex-NOR circuit 73 is assumed to be the H_ level. An L_ level signal is output from the Ex-NOR The circuit 72 is input to one input terminal of the NAND circuit 74 and an H_ level signal is input from the Ex-NOR circuit 73 to the other input terminal. Therefore, the output signal S2 of the NAND circuit 74 is assumed H_ level. An H-level comparison signal is input from the connection portion 15a to an input terminal of the Ex_N0R circuit 75 in the semiconductor wafer 5, and a small level signal A selection signal S1 is input from the connection portion i6d. Enter the other input. Therefore, the output signal of the Ex-NOR circuit 75 is assumed to be the H_ level. On the other hand, the comparison # of the level is input from the connecting part 15b to the

One input terminal of the Ex-NOR circuit 76, and the _L_ level chip selection signal so is input from the connection portion 16c to the other input terminal. Therefore, the output k number of the Ex_n0r circuit% is assumed to be the Η-level. A Η-level signal is input from the Ex-NOR circuit 75 to one input terminal of the NAND circuit 77, and a H-level signal is input from the Ex_NOR circuit% to the other input terminal. Therefore, the output signal S3 of the NAND circuit 77 is assumed to be the L_ level. A comparison signal of one level is input from the connection portion 17 &amp; to an input terminal of the Ex_N0R circuit 78 in the semiconductor wafer 6, and the sa slice of the _H_ level is selected by the number S1 from the connection portion j 8 (j is input to the other input terminal. Therefore, the output signal of the Ex-NOR circuit 78 is assumed to be the H_ level. On the other hand, a H-level comparison signal is input from the connection portion nb to One input terminal of the Ex NOR circuit 79, and the _L-level chip selection signal so and the connection portion 18c is input to the other input terminal. Therefore, the output signal of the circuit 79 is assumed to be a standard level. -H -Level signal This paper size applies Chinese national standard (3D A4 size (21 × 297 mm)) (Please read the notes on the back before filling this page) • Order — -18- V. Description of the invention (6)

The Ex-NOR circuit 78 is input to an input terminal of the NAND circuit 80, and an L-level signal is input from the Ex_NOR circuit 79 to the other round input terminal. Therefore, the output signal S4 of the NAND circuit 80 is assumed to be at the H_ level. When the wafer selection signal S0 is assumed to be 1-level as described above and the wafer selection signal S1 is assumed to be H-level, only the output signal S3 from the semiconductor wafer 5 is assumed to be L-level, and the semiconductor wafer 5 is selected as the operating crystal. Next, a case where the wafer selection signals S0 and S1 outputted from the electrode terminals 27 () and 27 (1) are assumed to be H-levels will be described. A comparison of L_levels A signal is input from the connection portion 8a to an input terminal of the Ex_nor circuit 72 of the semiconductor wafer 4, and a level-selected wafer selection signal si is input from the connection portion 9d to the other input terminal. The output number of the Ex_n0r circuit is assumed to be an L-level. On the other hand, a comparison number of an L-level is input from the connection portion 8b to an input terminal of the Ex-NOR circuit 73, and An H-level chip selection signal s0 is input from the connection portion% to the other input terminal. Therefore, the output signal of the Ex-NOR circuit 73 is assumed to be an L-level. An L-level signal is from The Ex-NOR circuit 72 is input to an input terminal of the NAND circuit 74, and an L_ level signal is transmitted from the E The x_n〇r circuit 73 is input to the other input terminal. Therefore, the output signal S2 of the nand circuit 74 is assumed to be an H-level. A comparison signal of an H-level is input to the semiconductor from the connection section. An input terminal of the Ex-NOR circuit 75 in the chip 5, and an H-level chip selection signal S1 is input from the connection portion 16d to the other input terminal. Therefore, an output of the Ex-NOR circuit 75 The signal is assumed to be H-level. Another 538526 A7 __ —_B7 V. Description of the invention (7) (Please read the precautions on the back before filling out this page) On the one hand, a comparison signal of the L-level from the connection part 1 5b is input to one input terminal of the Ex-NOR circuit 76, and a chip selection signal so of one level is input from the connecting portion 16c to the other input terminal. Therefore, the output signal of the Ex_n0r circuit 76 It is assumed to be a level. An H_level signal is input from the Ex-NOR circuit 75 to an input terminal of the NAND circuit 77, and an L-level signal is input from the Ex_NOR circuit to the other Input. Therefore, the output signal S3 of the NAND circuit 77 is assumed to be the H-level. A comparison signal of the H-level From the connecting portion 1 to 1 are input to one input terminal of the Ex_NOR circuit 78 in the semiconductor wafer 6, and the -H_ level wafer selection signal S1 is input from the connecting portion 18d to the other input terminal. Therefore, the output signal of the Ex-NOR circuit 78 is assumed to be an H_ level. On the other hand, a comparison signal of an 'H_ level is input from the connection portion 17b to an input terminal of the Ex-NOR circuit 79, And an n-level wafer selection signal SO is input from the connection portion 18c to the other input terminal. Therefore, the Εχ

The output signal of the -NOR circuit 79 is assumed to be the H_ level. An H-level signal is input from the Ex-NOR circuit 78 to an input terminal of the NAND circuit 80, and an H-level signal is input from the Ex-Nor circuit 79 to the other input terminal. Therefore, the output signal S4 of the NAND circuit 80 is assumed to be the L_ level. When the wafer selection signals 80 and s1 are assumed to be level as described above, only the output signal S4 from the semiconductor wafer 6 is assumed to be L-level, and the semiconductor wafer 6 is selected as the operation wafer. The above operations are tabulated in Tables 1 to 3 below, which show output signals S2, 83, and 84 based on the chip selection signals S0 and S1. Table 1 shows the output signal S2 from the semiconductor wafer 4. Table 2 shows that the size of the paper from the semiconductor wafer is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -20- 538526 5. Description of the invention (8) piece 5 The signal S3 is output in turn, and the signal S4 is output. A7 B7 and Table 3 show the --- S1 L S2 from the semiconductor chip 6 &quot; --- ----- Η L Η SELECTION ------ ---- ~ ------ — LZ H j two—S = two

[table 3]

(Please read the precautions on the back before filling this page) In this embodiment, the number of electrode terminals electrically connected to the electrode terminals 27a and 27b for the reference # of the substrate 2 depends on the semiconductor wafers 4 , $ And 6 are different. Therefore, the semiconductor wafers 4, 5 and 6 are supplied with different combinations of reference signals and thus generate different comparison signals regardless of whether the systems are supplied with a common wafer selection signal. Therefore, regardless of the plurality of semiconductor wafers 4, 5 and 6 forming the same wiring pattern being made into thin sheets, the paper size of these semiconductor wafers applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -21- 538526 A7 __ .............. B7 V. Description of the invention (9) '~-Any one of 4,5 and 6 is selected as the _ operation chip by a predetermined comparator circuit The wafer selection signals are compared with the comparison signals. (Please read the precautions on the back before filling this page) Next, referring to FIG. 5, a semiconductor integrated circuit element according to a second embodiment of the present invention will be described. FIG. 5 is a diagram illustrating the semiconductor integrated circuit according to this embodiment. Sectional view of the structure of a bulk circuit element. Referring to FIG. 5, a plurality of electrode terminals 27a to 27 are arranged on the surface before the substrate 2 'to maintain a predetermined distance p, and these electrode terminals (third electrode terminals) 27 & Ground, the chip selection signal is output from the electrode terminals 27c and 27d for output of the electrode terminals 27e to 27o such as chip selection No. 4, to the semiconductor wafers 4, 5, and 6, and the address signal is at the Such as storage, clock signal, clock enable signal and command signals and predetermined data signals for other memory circuits. The electrode terminals (fourth electrode terminals) 28a and 28b for the reference signal are arranged on the front surface (lower side in the figure) of the semiconductor wafers 4 on the substrate 2 'so as to be opposite to the electrode terminals 27a. And 27b. Likewise, the electrode terminals 28c to 280 are arranged so as to be opposite to the electrode terminals 27 and 27. The substrate and the semiconductor wafer 4 are bonded together via a plurality of bumps 12a to 120. Therefore, the electrode terminals 27a to 270 of the substrate 2 'are electrically connected to the electrode terminals 28a to 28 of the semiconductor wafer 4', respectively. In this case, the electrode terminal 28a for the reference signal is grounded via the bump 12a, and the electrode terminal 28b for the reference signal of the semiconductor wafer 4 'is grounded via the bump 12b. The electrode terminals 28a'-28o are arranged on the rear surface (upper side in the drawing) of the semiconductor wafer 4. The electrode terminal 28a for the reference signal is electrically connected to the electrode terminals 28a on the front surface through a connection portion 9a, and the electrode terminal 28a 'is electrically connected to the electrode on the front surface through a connection portion. This paper size applies to the Chinese National Standard (CNS) A4 specification (21〇 \ 297 Gongchu) -22- 5. Description of the invention and) Grasp. Similarly, the electrode terminals 28e ·. Are electrically connected to the electrode terminals 28c and 28,0 through the connecting portions, respectively, and the connecting portions such as to% are penetrated by a dielectric layer formed on the surface of the semiconductor wafer 4 'and almost perpendicular to the surface Holes and connecting conductors buried in these vias. A semiconductor wafer 5 having a sheet on the semiconductor wafer 4 is made, and has a structure identical to that of the semiconductor wafer 4 '. Electrode end center to 29. It is arranged on the surface of the semiconductor wafer 5 '. On the rear surface of the semiconductor wafer 5, electrode terminals 29a to 29 are arranged. 2% of the electrode terminals (fourth electrode terminals) on the front surface of the semiconductor wafer 5 are electrically connected through the connection portion 16a. To the semiconductor wafer 5, and then the electrode terminal 29a with a ☆ reference signal on the table®, and the electrode terminal (fourth electrode terminal) 29b on the front surface of the semiconductor wafer 5 'is electrically connected to the semiconductor via the connection portion 16b The wafer 5 is followed by this electrode terminal 29b for the reference signal. Similarly, in the semiconductor wafer 5, the electrode terminals 29c to 290 on the front surface are electrically connected to the semiconductor wafer 5 through the connecting portions 16c to 160 respectively, and the electrode terminals 29c 'to 29 on the rear surface are electrically connected. 〇 '. $ 海 半 'body wafer 5' and the semiconductor wafer 4 'are bonded together via a plurality of bumps 13b to 13o. Thus, the electrode terminals 29b to 290 on the front surface of the semiconductor wafer 5 are electrically connected to the semiconductor wafer 4, respectively, and the electrode terminals 28b to 28 on the rear surface. Here, bumps 13b to 13 are not formed between the electrode terminal 29a and the electrode 28a for a reference signal 'and therefore the electrode terminal 29a is not connected to the ground electrode terminal 28a. Then, the electrode terminal 29b used only for the reference signal is grounded via the bump 13b, the connection portion 9b, and the bump 12b. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) -23-. Yu Fang 538526 5. Description of the invention &lt; 1 The semiconductor wafer 6 arranged on the semiconductor wafer 5, has a Structure of the semiconductor wafers 4, and 5. The electrode terminals 30a to 30o are arranged on the surface of the semiconductor wafer 6 '. On the rear surface of the semiconductor wafer 6, there are arranged electrode terminals 30a to 30, and the semiconductor wafer 6, the electrode terminal (the fourth electrode terminal) 3 on the front surface is electrically connected through the connection portion 18a. To the semiconductor wafer 6, the electrode terminal 30a for the reference signal on the rear surface, and the electrode terminal (the fourth electrode terminal) 30b on the front surface of the semiconductor wafer 6, is electrically connected through the connection portion 18b. To the semiconductor wafer 6, and then the electrode terminal 30b for the reference signal on the surface. Similarly, in the semiconductor wafer 6, the electrode terminals 3 to 300 on the front surface are electrically connected to the semiconductor wafer 6 through the connecting portions 18c to 180 respectively, and the electrode terminals 3c on the rear surface are electrically connected. 'To 300 ,. The semiconductor wafer 6 and the semiconductor wafer 5 are adhered together via a plurality of bumps 14c to 14o. Thus, the semiconductor wafer 6, the electrode terminals 30c to 30o on the front surface are electrically connected to the semiconductor wafer 5, respectively, and the electrode terminals 29c to 29o on the rear surface. Here, the bump M is not formed. To 14 ° is used for the reference signal between the electrode terminal 3 and the electrode 29a. Similarly, no bumps 14C to 14 are formed between the electrode terminal 30b and the electrode 2 and used. Therefore, the electrode terminals used for the reference signal throughout 30b are electrodes that are not connected to the semiconductor wafer 5, which are grounded. Therefore, the electrode terminals 30a and 30b are not grounded. In this embodiment, In this way, the number of connection terminals of the bumps 12a, m &amp; 13b and the semiconductor wafers 4, '5, and 6, is reduced one by one in the direction of the sheet (toward the upper side), and the connection terminals are electrically connected. (Please read the precautions on the back before filling this page). Order -24-24538526 A7

The electrode terminals 27a and μ for the reference signal of the helium substrate 2 are used. Therefore, these semiconductor films 4, 5, and 6 are supplied with different combinations of reference signals to form a reference signal and thus generate different comparison signals although a common chip selection signal is provided. Thus, regardless of the semiconductor wafers 4, 5, and 6, which form the same wiring pattern, are made into thin sheets, any one of the semiconductor wafers 4 ', 5', and 6 'is selected as an operation wafer by a A predetermined comparator circuit compares the chip selection signals with the comparison signals. The present invention is not limited to the above embodiments but can be modified in different methods. In the above embodiment, by using a plurality of bumps, the substrate and the semiconductor wafer or two semiconductor wafers are adhered together, but it is not limited thereto. According to the present invention, by using any other dielectric wafer to connect members such as a ACF (Anisotropic Conductive Film) They can be glued together. Furthermore, in the above embodiment, the comparator circuit is composed of two Ex_nor circuits and a nanD circuit that receives output signals from the two Ex-NOR circuits. However, the comparator circuit is not limited to this, and the comparator circuit may be implemented by any comparator. It contains the circuit of Ex-OR circuit as a matter of course. Furthermore, 'Although the above embodiments have discussed semiconductor wafers forming a memory circuit and semiconductor integrated circuit elements using these semiconductor wafers, the present invention can be further applied to semiconductor wafers forming a CPU or a system LSI and using the same Semiconductor integrated circuit element of a semiconductor wafer. According to the present invention, as described above, even when the wafers having the same wiring pattern are sheeted one by one in a plural number, this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -25- 538526 A7 B7 V. Description of the invention Φ A predetermined chip can be selected by the chip selection signal sent from an external unit (please read the precautions on the back before filling this page) This paper size applies to Chinese national standards ( CNS) Α4 size (210X297 mm) -26-

Claims (1)

538526 — ^ · Iiti 4 f .-4. 孑 二 —Apply for 'Read' Patent Scope No. 091 105100 Patent Application Application Patent Scope Amendment This type of semiconductor day and day films, including: Date of amendment: scheduled for March: : Γ The first electrode terminal is arranged on the front surface to hold-pre-receive a reference signal to generate a comparison signal, which is to be compared with the chip selection signal in the-乂 circuit to select the -chip; The second electrode terminal is arranged at a distance from the plurality of first electrode terminals with respect to the front surface, and each of the reference signals is lost to the first electrode terminal by a track roller. ; The connecting part is used to electrically connect the ## and the second power which are off the normal track at the pitch. 2. For a semiconductor wafer in the scope of patent application No. ，, wherein the connecting portions have a step-shaped cross-section. Electricity 3 · For example, the semiconductor wafer of item 1 of the patent scope further includes electrode terminals for receiving chip remote selection signals, and the extremes for receiving chip selection signals are the same as those of the first electrodes. Number of ends. '4. For example, the semiconductor wafer of item 2 of the patent scope further includes electrode terminals for receiving wafer selection signals, and the number of electrode terminals for receiving wafer selection signals is the same as the number of the first electrode terminals. form. 5 · —Semiconductor integrated circuit element, comprising: “hard semiconductor wafers having the same wiring pattern and made into a thin sheet on a substrate; a dielectric wafer connecting member for electrically connecting the electrode terminals to (Applicable to the size of this paper) A4 size (210X297) -28- 538526 Arranged opposite to each other, since the substrate and the plurality of semiconductor wafers are stuck together, these semiconductor wafers are any one of items Nos. 1-4 of the patent application scope. 6. The semiconductor integrated circuit element according to item 5 of the scope of patent application, wherein the dielectric chip connection members are bumps. 7 · —Semiconductor integrated circuit element, comprising: a substrate having a plurality of third electrode terminals for outputting a reference signal to generate a comparison signal for comparison in a comparator circuit with a wafer selection signal for selecting a wafer A plurality of semiconductor wafers having the same wiring pattern and made into a thin sheet on the substrate; a plurality of fourth electrodes for receiving the reference signals arranged on the plurality of semiconductor wafers; and a dielectric wafer. The connecting member is used to adhere the substrate to the plurality of semiconductor wafers, and is arranged so that the number of the electrode terminals electrically connected to the first electrode terminals is reduced in the order of the sheets. 8. The semiconductor integrated circuit element according to item 7 of the patent application scope, wherein the number of these connections is reduced one by one in the order of the sheets. • If the semiconductor integrated circuit element of claim 7 is declared, the substrate further has electrode terminals for outputting the chip selection signals, and the electrode terminals for outputting the chip selection signals are the same as the It is formed by the number of three electrode terminals. The semiconductor integrated circuit element of the patent claim No. 8 in which the substrate further has an electrode terminal for outputting the crystal &gt; 5 selection signal, the (CNS) A4 specification (210X297 mm) • 29- 538526 A8 B8 C8 ~ _____ D8 The scope of the patent claimed by D8 for outputting the chip selection signals is the same as that of the three electrode terminals. • The semiconductor integrated circuit element described in the patent claim No. 7 in which the inter-chip connection member is a bump. 12. A method for selecting a semiconductor wafer, comprising the steps of: outputting a wafer selection signal to a plurality of semiconductor wafers having the same wiring pattern and formed into a sheet on a substrate; and &quot; selecting the plurality of semiconductor wafers Any one is based on the special comparison signal and the chip selection signal generated for the special V-body film. U. A method for selecting a semiconductor wafer as in item 12 of the scope of patent application, wherein the comparison signal is generated for each of these semiconductor wafers according to the reference signals applied from the substrate. 14. The method for selecting a semiconductor wafer according to item 13 of the scope of the patent application, wherein the comparison signal is generated as a plurality of signals for different combinations of state levels of each of these semiconductor wafers. Grandpa Order -30-