KR100900239B1 - Stack package and method of fabricating the same - Google Patents

Abstract

A stack package and a method for fabricating the same are provided to prevent the degradation of productivity of the whole stack package by omitting an additional patterning process for forming the rewiring by connecting a metal rewiring with a line width with a nano size between respective electrode terminals of the substrate and a pad for selecting each chip. A plurality of semiconductor chips(106,108,110,112) are stacked on a substrate(102) having an electrode terminal. Each semiconductor chip includes pads(106a,106b) for selecting a chip and a penetrating electrode is electrically connected by the penetrating electrode. One surface of the substrate including the semiconductor chip is sealed by an encapsulation material. The pads for selecting each chip of each stacked semiconductor chip is connected to the electrode terminal of the substrate by a metal rewiring(111) with a line width with a nano size formed along the edge of the semiconductor chip.

Description

STACK PACKAGE AND METHOD OF FABRICATING THE SAME

The present invention relates to a stack package and a method for manufacturing the same, and more particularly, to a stack package and a method for manufacturing the same that can minimize the increase in cost and yield loss in forming the stack package.

In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technologies for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. I'm making it.

In addition, as miniaturization of electric and electronic products and high performance is required, various technologies for providing a high capacity semiconductor module have been researched and developed.

As a method for providing a high capacity semiconductor module, there is a high integration of a memory chip, which can be realized by integrating a larger number of cells in a limited space of the semiconductor chip.

However, such high integration of the memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width. Therefore, a stack technology has been proposed as another method for providing a high capacity semiconductor module.

Such a stacking technique includes a method of embedding two stacked chips in one package, and a method of stacking two packaged packages. However, the method of stacking two single packages as described above has a limit of height of the semiconductor package with the trend of miniaturization of electrical and electronic products.

Therefore, research on a stack package and a stack package for mounting two or three semiconductor chips in one package has been actively conducted in recent years.

Here, the stack package generally includes a method of simply arranging and packaging a plurality of semiconductor chips on a substrate, and a method of packaging by stacking two or more semiconductor chips in a stacked structure.

Such a stack package generally forms a hole penetrating the semiconductor chip in the semiconductor chip, and forms a through electrode called a through silicon via (TSV) by filling a conductive material in the penetrated hole. The upper and lower semiconductor chips are connected to each other via electrodes.

On the other hand, since the stack package as described above cannot implement correct memory operation as a stack package having improved density by simply connecting the upper and lower semiconductor chips, the upper and lower semiconductor chips are stacked when each semiconductor chip is stacked. Each redistribution layer (RDL) is formed in each semiconductor chip so as to be distinguished by each different signal of the semiconductor chip of the semiconductor chip, and the redistribution is connected to a through electrode formed in each semiconductor chip and an electrode terminal corresponding thereto. In this way, semiconductor chips are divided.

However, although not shown and described in detail, in the conventional stack package as described above, a method of distinguishing signals of each semiconductor chip by forming different redistributions within each semiconductor chip is performed by forming the redistribution lines for each semiconductor chip. A separate patterning process must be performed, and accordingly, a mask for the patterning must be separately formed.

Furthermore, in performing the process, the patterning process must be performed while changing the position of the mask according to the stack position in which the semiconductor chips are stacked, thereby decreasing productivity and increasing cost.

In addition, since stacking between semiconductor chips is fixed at the minimum yield according to the difference in the quantity of good-die of each wafer, the yield of the good-die is different in the present situation in which wafers having different yields are used. Loss inevitably occurs.

The present invention provides a stack package and a method of manufacturing the stack package which can prevent a decrease in productivity and an increase in cost in forming a stack package.

In addition, the present invention provides a stack package and a method for manufacturing the stack package that can minimize the yield loss in stack package formation.

A stack package according to the present invention includes a substrate having an electrode terminal; A plurality of semiconductor chips stacked on the substrate and provided with chip selection pads and through electrodes, respectively, and electrically connected to each other by the through electrodes; And an encapsulant for sealing one surface of the substrate including the semiconductor chip, wherein each of the chip selection pads of each of the stacked semiconductor chips has a nano-sized line width formed along an edge of the semiconductor chip. It is characterized in that connected to the electrode terminal of the substrate by.

The through electrodes are connected to the remaining pads except for the chip selection pad of the semiconductor chips, respectively.

At least two to four semiconductor chips are stacked.

The metal redistribution is characterized in that consisting of copper or gold and alloys thereof.

The metal rewiring is made of an insulating material coated with copper or gold.

The nano-size line width is characterized by consisting of a size of 1 ~ 9nm.

In addition, a method of manufacturing a stack package according to the present invention includes attaching a first semiconductor chip having first and second chip selection pads on a substrate having first and second electrode terminals; Connecting the first and second chip selection pads and the second electrode terminal to each other by metal redistribution having a nano-sized line width; Attaching a second semiconductor chip having third and fourth chip selection pads on the first semiconductor chip; Connecting the third chip selection pad, the first electrode terminal, the fourth chip selection pad and the second electrode terminal to each other by metal redistribution having a nanoscale line width; Attaching a third semiconductor chip having a fifth and a sixth chip selection pad on the second semiconductor chip; Connecting the fifth chip selection pad, the second electrode terminal, the sixth chip selection pad, and the first electrode terminal to each other by metal redistribution having a nanoscale line width; Attaching a fourth semiconductor chip having seventh and eighth chip selection pads on the third semiconductor chip; Connecting the seventh and eighth chip selection pads and the first electrode terminal to each other by metal redistribution having a nano-sized line width; And sealing one surface of the substrate including the first, second, third and fourth semiconductor chips with an encapsulant.

The first and second electrode terminals are formed of a power source and a ground terminal.

The first, second, third and fourth semiconductor chips are characterized in that through electrodes are formed to electrically connect the semiconductor chips.

The first, third, fifth and seventh chip selection pads are formed of power pads.

The second, fourth, sixth, and eighth chip selection pads may be ground pads.

The metal redistribution is formed of copper or gold and alloys thereof.

The metal redistribution is formed of an insulating material coated with copper or gold.

The metal redistribution is formed by ink jet printing.

The metal redistribution is formed along an edge of each semiconductor chip.

The nano-size line width is formed to a size of 1 ~ 9nm.

According to the present invention, when forming a stack package, at least two or more semiconductor chips having power and ground chip selection pads corresponding to the power and ground terminals are stacked on a substrate having power and ground terminals, and each chip of the semiconductor chips is selected. The pads and the respective electrode terminals of the substrate are connected to each other in each semiconductor chip by connecting metal nanowires having a nano-sized line width made of copper or gold to match each signal along the edges of the stacked semiconductor chips. A separate patterning process for forming different redistributions to distinguish the signals of each semiconductor chip, and thus forming the redistributions, and thus lowering the mass productivity and cost of the entire stack package by eliminating the need for a separate mask. The increase can be prevented.

In addition, the present invention is different from the conventional method of forming a through electrode in the chip selection pad portion connected to the substrate using only a good-die to connect to the substrate when forming a stack package, the signal is connected between each semiconductor chip as described above The chip selection pad portion connected to the substrate is electrically connected to the substrate using only a metal redistribution line having a nano-sized line width without forming a through electrode, so that the yield between stacks of semiconductor chips is different from each other. Yield loss can be minimized as the minimum yield is fixed according to the difference in the quantity of good-die.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

In detail, FIG. 1 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention, and FIG. 2 is a plan view illustrating the stack package according to an embodiment of the present invention.

As shown in FIGS. 1 and 2, the stack package 100 according to an exemplary embodiment of the present invention includes electrode terminals 118a, 118b, and 118c including power and ground terminals 118a and 118b. And a power supply and ground chip selection pad 106a, 106b, 108a, 108b, 110a, 110b, 112a, and 112b corresponding to the power supply and ground terminals 118a and 118b of the substrate 102 on the substrate 102. At least two semiconductor chips 106, 108, 110, 112 having bonding pads 106a, 106b, 106c, 108a, 108b, 108c, 110a, 110b, 110c, 112a, 112b, 112c Four to four semiconductor chips 106, 108, 110, and 112 have a stacked structure.

In addition, one surface of the substrate 102 including the at least two semiconductor chips 106, 108, 110, 112 protects the at least two semiconductor chips 106, 108, 110, 112 from external stress. It is sealed with an encapsulant 114, such as an epoxy molding compound (EMC).

Here, the plurality of power and ground chip selection pads 106a, 106b, 108a, 108b, 110a, 110b, 112a, and 112b of at least two or more of the semiconductor chips 106, 108, 110, and 112 are each semiconductor chip ( Metal redistribution 111 having a nanoscale line width made of copper or gold and alloys thereof formed along edges of the semiconductor chips 106, 108, 110, and 112 to match the signals of 106, 108, 110, and 112. ) Is electrically connected to the power supply and ground electrode terminals 118a and 118b of the substrate 102.

In addition, the metal redistribution 111 having the nano-sized line width is formed of an insulating material coated with copper or gold.

In this case, the remaining bonding pads 106c, 108c, 110c, and 112c of the semiconductor chips 106, 108, 110, and 112 that are not electrically connected by the metal redistribution 111 having the nano-scale line width are the semiconductors. It is connected by through electrodes V1, V2, V3, V4 formed in the chips 106, 108, 110, 112, respectively.

Here, the nano-size line width of the metal redistribution 111 has a range of 1 to 9 nm.

In addition, a ball land (not shown) on the other surface of the substrate 102 is provided with a plurality of external connection terminals 116 such as solder balls as mounting means.

Specifically, FIGS. 3A to 3E are cross-sectional views illustrating a method of manufacturing a stack package according to an exemplary embodiment of the present invention, and FIGS. 4A to 4E illustrate a method of manufacturing a stack package according to an exemplary embodiment of the present invention. As a plan view for each process, which will be described below.

Referring to FIGS. 3A and 4A, a power source and a ground terminal corresponding to the substrate 102 on the substrate 102 having the first and second electrode terminals 118a and 118b on the upper surface, such as a power source and a ground terminal, respectively. And a first semiconductor chip 106 having first and second chip selection pads 106a and 106b, respectively, such as a power supply and ground pad.

Then, between the first and second chip selection pads 106a and 106b and the second electrode terminal 118b is formed along the edge of the first semiconductor chip 106 by ink jet printing. It is electrically connected using a metal redistribution 111 having a nano-sized line width made of copper or gold and alloys thereof.

In addition, the metal redistribution 111 having the nano-size line width is formed of an insulating material coated with copper or gold.

Here, the nano-size line width of the metal redistribution 111 is preferably formed in the range of 1 ~ 9nm.

At this time, the first through electrode (V1) in the remaining portion of the bonding pad (106c) other than the first and second chip selection pad (106a, 106b), such as the power supply and ground pad of the first semiconductor chip 106. And electrically connect with the substrate 102 via the first through electrode V1.

3B and 4B, a second semiconductor chip 108 having third and fourth chip selection pads 108a and 108b of power and ground pads, respectively, on the first semiconductor chip 106. Attach. Then, a nano-sized line width is formed between the third chip selection pad 108a and the first electrode terminal 118a and between the fourth chip selection pad 108b and the second electrode terminal 118b. It is connected to the metal redistribution 111 having.

In this case, the connection by the metal redistribution 111 having the nano-sized line width is formed by the ink jet printing method which is the same method as the connection between the first semiconductor chip 106 and the substrate 102.

In addition, a second through electrode V2 is formed in the remaining portion of the bonding pad 108c other than the third and fourth chip selection pads 108a and 108b on the second semiconductor chip 108. The second semiconductor chip 108, the first semiconductor chip 106, and the substrate 102 connected to the second semiconductor chip 108 and the first semiconductor chip 106 may be formed of the first semiconductor chip 106. The first through electrode V1 and the second through electrode V2 of the second semiconductor chip 108 are electrically connected to each other.

3C and 4C, a third semiconductor chip 110 having fifth and sixth chip selection pads 110a and 110b formed of power and ground pads on the second semiconductor chip 108, respectively. Attach. Thereafter, the fifth chip selection pad 110a, the second electrode terminal 118b, and the sixth chip selection pad 110b and the first electrode terminal 118a have a nanowire width having a nano-sized line width. 111).

In this case, the connection by the metal redistribution 111 having the nano-sized line width is formed by the ink jet printing method which is the same method as the connection between the second semiconductor chip 108 and the substrate 102.

In addition, a third through electrode V3 is formed in the remaining portion of the bonding pad 110c other than the fifth and sixth chip selection pads 110a and 110b on the third semiconductor chip 110. The third semiconductor chip 110 and the first and second semiconductor chips 106 and 108 are connected to the first and second through electrodes V1 and V2 of the first and second semiconductor chips 106 and 108. In addition, between the third semiconductor chip 110 and the substrate 102, the first and second through electrodes V1 and V2 of the first and second semiconductor chips 106 and 108 and the third semiconductor chip ( It is electrically interconnected by the third through electrode (V3) of 110.

3D and 4D, a fourth semiconductor chip 112 having seventh and eighth chip selection pads 112a and 112b formed of power and ground pads on the third semiconductor chip 110, respectively. Attach. Thereafter, the seventh and eighth chip selection pads 112a and 112b and the first electrode terminal 118a are connected to each other using a metal redistribution 111 having a nanoscale line width.

At this time, the connection by the metal redistribution 111 having the nano-sized line width is formed by the ink jet printing method which is the same method as the connection between the third semiconductor chip 110 and the substrate 102, and In addition, a fourth through-electrode V3 is also formed in the remaining portion of the bonding pad 112c other than the seventh and eighth chip selection pads 112a and 112b on the fourth semiconductor chip 112. And the first, second and third through electrodes V1, V2, and V3 of the second and third semiconductor chips 106, 108, and 110, and the fourth semiconductor chip 112 and the first and second electrodes. Between the second and third semiconductor chips 106, 108 and 110, and between the fourth semiconductor chip 112 and the substrate 102, the first, second and third semiconductor chips 106, 108 and 110 The first, second and third through electrodes V1, V2, and V3 are electrically connected to each other by the fourth through electrode V4 of the fourth semiconductor chip 112.

3E and 4E, one surface of the substrate 102 including the first, second, third, and fourth semiconductor chips 106, 108, 110, and 112 may be disposed on the semiconductor chip 106, 108, 110. , 112 are sealed with an encapsulant 114 such as EMC to protect against external stress, and a plurality of external connection terminals such as solder balls are mounted on the ball lands (not shown) of the other surface of the substrate 102 as mounting means. 116 is attached to form a stack package 100 according to an embodiment of the present invention.

As described above, the stack package and the method of manufacturing the same according to the present invention form different redistribution within each semiconductor chip to distinguish signals of the semiconductor chips, and separate patterning for forming the redistribution. Unlike a conventional stack package in which a process and a mask are separately formed and manufactured by moving a mask according to positions of stacked semiconductor chips, the power and ground terminals may be formed on a substrate having power and ground terminals as described above. Stacking at least two semiconductor chips having corresponding power supply and ground chip selection pads, and between each chip selection pad of the semiconductor chip and each electrode terminal of the substrate, along each edge of the stacked semiconductor chips The entire stack package accordingly by connecting them with a metal redistribution with nanoscale line widths to fit The mass production can be prevented from degradation and increased costs.

In addition, unlike the conventional method of forming a penetrating electrode in the chip selection pad portion connected to the substrate using only a good-die to connect with the substrate, as described above, the chip selection pad connected according to the signal connected between the semiconductor chips. The parts are electrically connected to the substrate only by metal redistribution having a nano-sized line width without forming through-electrodes, so that the yield between stacks of semiconductor chips is good-die to each wafer having different yields. Yield loss can be minimized as the minimum yield is fixed according to the difference in quantity.

In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

1 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

2 is a plan view illustrating a stack package according to an embodiment of the present invention.

3A to 3E are cross-sectional views illustrating processes for manufacturing a stack package according to an embodiment of the present invention.

Figures 4a to 4e is a plan view for each process for explaining the manufacturing method of the stack package according to an embodiment of the present invention.

Claims (16)

A substrate having electrode terminals; A plurality of semiconductor chips stacked on the substrate and provided with chip selection pads and through electrodes, respectively, and electrically connected to each other by the through electrodes; And An encapsulant for sealing one surface of the substrate including the semiconductor chip; Including; And each chip selection pad of each of the stacked semiconductor chips is connected to an electrode terminal of the substrate by metal redistribution having a nano-sized line width formed along an edge of the semiconductor chip. The method of claim 1, And the through electrodes are connected to the remaining pads except for the chip selection pad of the semiconductor chips, respectively. The method of claim 1, The semiconductor chip stack stack, characterized in that at least two to four. The method of claim 1, The metal redistribution is a stack package, characterized in that consisting of copper or gold and alloys thereof. The method of claim 4, wherein The metal redistribution is a stack package, characterized in that made of an insulating material coated with copper or gold. The method of claim 1, The nano-size line width is 1 ~ 9nm stack package, characterized in that consisting of. Attaching a first semiconductor chip having first and second chip selection pads on a substrate having first and second electrode terminals; Connecting the first and second chip selection pads and the second electrode terminal to each other by metal redistribution having a nano-sized line width; Attaching a second semiconductor chip having third and fourth chip selection pads on the first semiconductor chip; Connecting the third chip selection pad, the first electrode terminal, the fourth chip selection pad and the second electrode terminal to each other by metal redistribution having a nanoscale line width; Attaching a third semiconductor chip having a fifth and a sixth chip selection pad on the second semiconductor chip; Connecting the fifth chip selection pad, the second electrode terminal, the sixth chip selection pad, and the first electrode terminal to each other by metal redistribution having a nanoscale line width; Attaching a fourth semiconductor chip having seventh and eighth chip selection pads on the third semiconductor chip; Connecting the seventh and eighth chip selection pads and the first electrode terminal to each other by metal redistribution having a nano-sized line width; And Sealing one surface of the substrate including the first, second, third and fourth semiconductor chips with an encapsulant; Method of manufacturing a stack package comprising a. The method of claim 7, wherein The first and second electrode terminals are formed of a power supply and a ground (Ground) terminal, characterized in that the stack package manufacturing method. The method of claim 7, wherein The first, second, third and fourth semiconductor chip is a manufacturing method of a stack package, characterized in that the through-electrode is formed so that each semiconductor chip is electrically connected. The method of claim 7, wherein The first, third, fifth and seventh chip selection pad is a power supply pad, characterized in that the manufacturing method of the stack package. The method of claim 7, wherein The second, fourth, sixth and eighth chip selection pads may be formed as ground pads. The method of claim 7, wherein The metal redistribution method of manufacturing a stack package, characterized in that formed of copper or gold and alloys thereof. The method of claim 12, The metal redistribution method of manufacturing a stack package, characterized in that formed of an insulating material coated with copper or gold. The method of claim 12, The metal redistribution method of manufacturing a stack package, characterized in that formed by ink jet printing (Ink Jet Printing) method. The method of claim 12, The metal redistribution is formed along an edge of each semiconductor chip. The method of claim 12, The nano-size line width is formed in the size of 1 ~ 9nm manufacturing method of the stack package.

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