JPH0286147A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the degree of integration of IC, and shorten the signal delay time by forming a plurality of IC block in a wafer for circuit use, and forming wirings for signal use and power supply voltage use which connect IC blocks and constitute a prescribed circuit. CONSTITUTION:On a wafer 1 for circuit use, a plurality of IC blocks 3 are formed in a lattice type with high density; on the main surface of each IC block 3, a plurality of substratum electrodes 9 for signal use and power supply voltage use, which lead out electrodes from word lines 5, data lines 6 and wirings 7, are formed; on the wafer 2 for wiring use, a multilayer interconnection is formed; on each wiring layer thereof, wirings 10a-10e for signal use and power supply voltage use are formed: an insulating film is formed between the respective wiring layers: an opening is formed at a part of the insulating film 11f; a plurality of substratum electrodes 13 are formed in the wiring 10e, and protruding electrodes 14 are formed by using solder and the like; the wafer 1 for circuit use and the wafer 2 for wiring use are connected via the lump electrodes 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor device technology, for example, wafer scale integration (wafer scale integration).
Integration: hereinafter referred to as wsr)
It relates to a technique that is particularly effective when applied to.

[Conventional technology]

For 'vVs [see IEJ Journal of Solid State Circuits, 198
6th year lO month, N015, Volume 21 (IE MiE J[)
URNAL OF 5QLIO-9TATE C
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OBER1986) r Silicon Hybrid
Wafer-scale packaging technology (Sili)
con Hybrid Wafer-5cale Pa
ckage Techno! .

gy) J pp, 845-851, and in this document, a rectangular hole is made in a silicon wafer, and an sm circuit (hereinafter referred to as I
The WSL technology for embedding a chip (referred to as C) is described.

In WS+, even when multiple IC chips are embedded in a silicon wafer, multiple IC chips are embedded in the silicon wafer.
Even in the case of forming a IC, a wiring area is provided between ICs, and in this wiring area, signal wiring for connecting between ICs and power supply voltage wiring for supplying power supply voltage to the IC are installed. was forming.

The reason why it was necessary to provide a wiring area between ICs is that if no wiring area were provided, the wiring for the above-mentioned signals and power supply voltage would have to be formed on top of the IC, and from the perspective of the ground level difference. This is because there are reliability problems such as disconnection of these wirings and increased resistance.

[Problem to be solved by the invention]

However, the present inventors have found that the above-mentioned conventional technique of providing a wiring area on a silicon wafer provided with ICs has the following problem.

That is, in order to connect the ICs, a wiring area must be provided between the ICs, and this wiring area has hindered the high integration of the ICs.

However, the wiring area could not be easily narrowed down. This is because, for example, the power supply voltage wiring formed in the wiring area needs to be wider than the signal wiring in consideration of power supply voltage supply, noise, and the like.

Furthermore, in recent years, the number of elements constituting ICs has become smaller and smaller. Therefore, as the number of elements increases, the number of wires also increases, but the wires cannot be easily miniaturized from the viewpoint of electromigration or stress migration, or the distance between the wires cannot be reduced from the viewpoint of noise and the like. For this reason, it is assumed that the wiring area will have to become wider and wider, and the degree of integration will decrease.

Furthermore, as the width of the wiring area becomes wider, that is, the distance between ICs becomes wider, the length of the wiring that connects the ICs becomes longer (as a result, the resistance and capacitance of the wiring also increase. Even if the circuit operation within the IC becomes faster, the signal delay time within the recon wafer on which the IC is formed will become longer.

Also, since the wiring that connects the ICs and the ICs are formed on the same silicon wafer, the faster the circuit operation becomes, the more noticeable the influence of noise from the wiring that connects the ICs on the ICs becomes. is assumed.

The present invention has been made with attention to the above-mentioned problems, and its purpose is to provide a technique that can improve the degree of integration of ICs in WSI.

Another object of the present invention is to provide a technique that can shorten WSI signal delay time.

The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, it is a semiconductor device in which a pair of semiconductor wafers whose main surfaces face each other are connected via a protruding electrode, one semiconductor wafer having a plurality of Ic blocks formed thereon, and the other semiconductor wafer having: The semiconductor device has a structure in which wiring for signals and power supply voltage is formed to connect the IC blocks to form a predetermined circuit.

[Effect]

According to the above means, a semiconductor wafer on which a plurality of IC blocks are formed has signal wiring for transmitting signals between each IC block and a power supply voltage for supplying a power supply voltage to each IC block. Since there is no need to arrange wiring for this purpose, there is no need to provide a wiring area.

〔Example〕

FIG. 1 is a schematic partially cutaway perspective view showing essential parts of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic partially cutaway view of this semiconductor device.

For example, the semiconductor device of this embodiment, which is applied to the main memory section of a large-sized computer, consists of a pair of semiconductor wafers made of single-crystal silicon (Si), that is, a circuit wafer 1 and a wiring wafer 2 shown in FIG. A plurality of IC blocks 3 are formed in a grid pattern at high density on a device circuit wafer l composed of
Unlike conventional WSI, no wiring area is provided.

That is, each IC block 3 is electrically independent from each other on the circuit wafer 1.

Each IC block 3 has a 4M bit dynamic RA
An IC (not shown) such as M is constituted by, for example, an MO8 type transistor.

As shown in FIG. 2, stacked cells 4, for example, are used as memory cells. Stacked cell 4 is MO
The stacked cell 4 includes a word line 5 made of polycrystalline Sl, a data line 6 made of aluminum (A1), etc., and arranged in a direction perpendicular to each other. are connected to form a cell array (not shown).

In addition, a wiring 7 made of Af etc. and an MO5 type transistor 8
For example, predetermined peripheral circuits (not shown) such as a decoder circuit, a sense amplifier circuit, and an address buffer circuit are configured.

On the main surface of each IC block 3, a word line 5, a data line 6
, a plurality of base electrodes 9 for signals and power supply voltage for drawing out electrodes from the wiring 7 are formed.

Note that among these base electrodes 9, the base electrode for power supply voltage also includes an electrode for ground. Furthermore, a protruding electrode (not shown) made of solder (Pb-3n) or the like is formed on the base electrode 9.

On the other hand, a multilayer wiring layer is formed on the wiring wafer 2, and in each wiring layer, wirings 10a-106 for signals and power supply voltage are formed, which are arranged perpendicularly to each other. has been done. Note that among the wirings 10a to 10e, the wiring for power supply voltage also includes wiring for ground. The wirings 108 to 10e are made of Af or the like, and the insulating films 11a to 11a, such as silicon dioxide (S10□), are formed between each wiring layer.
ie, and the wiring 10e is insulated from the insulating film 1.
1. Protected from the outside by f.

Conductivity between the wirings 10a to 10e in each wiring layer is achieved through through holes B12.12H formed at predetermined intersections of the wirings 10a to 10e in each wiring layer.

Then, a part of the insulating film 11f is opened, and the wiring 1
A plurality of base electrodes 13 are formed on Oe. Note that a protruding electrode (not shown) made of solder or the like is formed on the base electrode 13.

Further, although not shown, electrodes for connection to a large-sized computer are formed on a predetermined portion of the outer periphery of the wiring wafer 2.

Next, the circuit wafer l and the wiring wafer 2 explained above.
The procedure for assembling the semiconductor device of this example by connecting the two will be explained.

First, the base electrode 9 of each IC formed on the circuit wafer 1
A probe is placed on the protruding electrode to sort out good and defective products.

Next, based on the distribution of non-defective ICs in the circuit wafer 1, the wiring 10e and the through-hole portion 1 of the wiring wafer 2 are
2a, and further, a base electrode 13 is formed at a position corresponding to the base electrode 9 of the non-defective IC.

Then, the positions of the protruding electrodes of the base electrode 9 of the circuit wafer 1 and the protruding electrodes of the base electrode 13 of the wiring wafer 2 are accurately aligned and temporarily fixed.

Furthermore, after that, reflow is performed to connect the circuit wafer 1 and the wiring wafer 2 through the protruding electrodes 14, and assemble the semiconductor device.

As described above, according to this embodiment, signal transmission between the IC blocks 3 and supply of power supply voltage to each IC block 3 are performed by the wirings 10a to 10e formed on the wiring wafer 2.

Therefore, the circuit wafer 1 includes signal wiring for connecting each IC block 3 and transmitting signals, and each IC block 3.
There is no need to form wiring for the power supply voltage to supply the power supply voltage to the power supply voltage.

Therefore, there is no need to provide a wiring area on the circuit wafer 1. Furthermore, since the IC blocks 3 can be formed at a higher density on the circuit wafer 1 by the amount of wiring area eliminated, the degree of integration can be reliably improved.

Then, as the interval between the IC blocks 3 becomes narrower, the wirings 10a to 10 connecting the IC blocks 3 to each other become narrower.
Since the degree of freedom in routing of wires 10a to 1 is improved,
The length of 0e can be designed to be short. Therefore, the signal delay time in the entire semiconductor device can be shortened.

When a plurality of such semiconductor devices are connected to a large computer, the signal delay time within the semiconductor device is shortened, so that the signal delay time between the plurality of connected semiconductor devices is also shortened.

Further, wirings 108 to 1 connecting between each IC block 3
Since the length of 0e can be shortened and designed to be wide, a semiconductor device that is resistant to noise and the like can be constructed. and,
Since these wirings 103 to 10e and each IC block 3 are separated, the elements of each IC block 3 are
It becomes less susceptible to noise etc. from a to toe.

Further, for example, the word structure of the memory may be changed, the memory capacity may be changed, or the circuit function of the semiconductor device may be changed in accordance with the user's request.

In this case, in the semiconductor device of this embodiment, by changing the wiring wafer 2, it is possible to provide a semiconductor device with circuit functions that meet the user's needs.

For example, it is easy to arrange the wirings 10a to 10e that connect each IC block 3, for example, because the degree of freedom in routing the wirings 10a to 10e is improved, so it is very easy to change the circuit function. It's easy.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

For example, in the above embodiment, 4
Although the case where an M-bit dynamic RAM is configured has been described, it is not limited to this, for example,
Dynamic RAM and static RA with a predetermined number of bits
Various applications are possible, such as when M is formed.

Furthermore, in the above embodiments, a case has been described in which the semiconductor device is applied to a large-sized computer, but the invention is not limited to this, and can be applied to various other devices, such as communication equipment and image equipment, for example.

Further, the outer peripheries of the wiring wafer and the circuit wafer may be sealed with a predetermined resin or the like, except for the electrode portions connected to external devices.

Further, in the above embodiment, a case was explained in which electrodes connected to external devices were formed on a predetermined portion of a wiring wafer, but the invention is not limited to this. The wafer may be fitted into a rectangular printed wiring board, and electrodes connected to external devices may be taken out from the four sides of this printed wiring board. By doing so, the degree of integration of the IC is improved, and even if the number of electrodes for connection with external devices increases, it can be handled.

In the above explanation, the invention made by the present inventor was mainly applied to a memory section, which is the background field of application, but the invention is not limited to this. It is also possible to form a plurality of logic circuits and apply it to other semiconductor devices equipped with predetermined logic functions.In this case, by changing the wiring wafer variously, semiconductor devices with different functions can be configured.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, it is a semiconductor device in which a pair of semiconductor wafers whose principal surfaces face each other are connected via a protruding electrode, the circuit wafer having a plurality of IC blocks formed thereon, and the wiring wafer having the IC blocks formed thereon. By forming wiring for signals and power supply voltage that connect blocks to each other to form a predetermined circuit, connections between ICs and supply of power supply voltage to ICs are formed on the wiring wafer. Since this is done by using fixed wiring, the circuit wafer does not require a wiring area.

Therefore, the degree of integration of ICs on the circuit wafer can be improved.

Furthermore, since the length of the wiring connecting each IC can be designed to be short, the signal delay time can be shortened.

Furthermore, even if the layout of the ICs on the circuit wafer is the same, the connections between the ICs are made by the wiring wafer, so it is easy to change the circuit functions to various circuit functions by changing the wiring wafer. .

[Brief explanation of the drawing]

FIG. 1 is a schematic partially cutaway perspective view showing essential parts of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic partially cutaway view of this semiconductor device. 113~llf ・Through hole part, ・Protrusion electrode.・Insulating film, 13 ・ 12.12a ・Base electrode, l...Circuit wafer 2...Wiring wafer 3...
IC block, 4...stacked cell, 4a...M
OS type transistor, 4b...charge storage section, 5...
・Word line, 6...Data line, 7...Wiring, 8...
・MO3 type transistor, 9... base electrode, lOa~
lOe...Wiring, diagram

Claims (1)

[Claims] 1. A semiconductor device in which a pair of semiconductor wafers whose principal surfaces face each other are connected via a protruding electrode, one semiconductor wafer having a plurality of integrated circuit blocks formed thereon,
A semiconductor device characterized in that the other semiconductor wafer is formed with signal wiring and power supply voltage wiring that connects the integrated circuit blocks to form a predetermined circuit. 2. The semiconductor device according to claim 1, wherein a memory circuit is configured in the integrated circuit block. 3. The semiconductor device according to claim 1, wherein the integrated circuit block includes a logic circuit.