WO2007077849A1

WO2007077849A1 - Semiconductor chip and semiconductor integrated circuit

Info

Publication number: WO2007077849A1
Application number: PCT/JP2006/325981
Authority: WO
Inventors: Koichi Kumagai
Original assignee: System Fabrication Technologies, Inc.
Priority date: 2005-12-28
Filing date: 2006-12-26
Publication date: 2007-07-12
Also published as: JP2007178396A; TWI474017B; JP4473215B2; TW200739103A

Abstract

Provided is a semiconductor chip which can be mounted on an interposer. The semiconductor chip has a minimum pitch interval of 100μm or less. The semiconductor chip is provided with a plurality of electrodes for connecting a wiring in the interposer with a wiring in the semiconductor chip; a plurality of probe electrodes connected to a part of the electrodes; a dividing means for dividing a test signal inputted to the probe electrodes and supplying the divided signals to the wiring which is in the semiconductor chip and connected with the electrodes; and a signal processing means for performing prescribed signal processing based on the test signal divided by the dividing means.

Description

Specification

Semiconductor chip and semiconductor integrated circuit

Technical field

TECHNICAL FIELD [0001] The present invention relates to a semiconductor chip and a semiconductor integrated circuit, and more particularly to a semiconductor chip mounted on an interposer and a semiconductor integrated circuit using the same.

Background art

[0002] Semiconductor integrated circuits, which are chips (SOC: system-on-chip) on which arbitrary main circuits of a computer such as a microprocessor, a chip set, a video chip, and a DRAM are integrated, are provided. Such a semiconductor integrated circuit can drastically reduce the area required for mounting, and can further reduce power consumption compared to a system with multiple chips having equivalent circuits. . In addition, before the semiconductor integrated circuit is shipped, tests such as operation of each main circuit and connection relation between terminals of the main circuit are performed.

[0003] A bump inspection apparatus that inspects the state of a bump hidden behind a chip by X-ray fluoroscopy with respect to a semiconductor integrated circuit mounted by bump bonding is disclosed (Patent Document 1). See;). The technique of Patent Document 1 detects the center position of a bump using X-rays, sets a reference bump based on the center position, and compares the reference bump with the bump shape to be inspected. Judge the quality of the.

[0004] Further, a technique for performing a connection test between a terminal of a first semiconductor integrated circuit device mounted on a printed board and a terminal of a second semiconductor integrated circuit device is disclosed (Patent Document 2). O) The technology of Patent Document 2 is that the second semiconductor integrated circuit device includes a test data fetching and holding means for fetching and holding test data output from the first semiconductor integrated circuit device. A connection test between the terminals of the first and second semiconductor integrated circuit devices is performed by checking whether the output of the data fetching and holding means is a predetermined value.

[0005] Furthermore, a test apparatus for an MPU-mounted printed board that enables testing of all buses and other functions of the printed board including the MPU and that can easily determine the final failure location is disclosed. (See Patent Document 3.) ₀ The technology of Patent Document 3 is an external device. Printed circuit board connection means connected to the connection means, test ROM storing a test program for testing, test execution means for executing a control program for MPU test, and MPU operation control according to the control program on the printed board And a test control means for performing the test of the printed circuit board through the external device connection means by causing the MPU to execute a test program.

[0006] Further, (see Patent Document 4.) That print circuit test method is disclosed plate to conduct a quality test of the plurality of connectors and electronic components printed circuit board mounted ₀ the technique of Patent Document 4 Then, insert the interface board into the connector of the printed circuit board to be tested, connect the printed circuit board to the main body of the tester, and automatically assign the connection contents of the printed circuit board to display on the main body of the tester. When test information such as correction, change, or addition of the printed circuit board connection contents is input from the displayed screen, the tester body reads the test circuit program from the circuit pattern on the printed circuit board, and displays test information. Create a test circuit and a test program that can be matched to each other, and execute the test program to test the printed circuit board.

Patent Document 1: JP-A-5-251535

Patent Document 2: JP-A-6-279919

Patent Document 3: Japanese Patent Laid-Open No. 10-55287

Patent Document 4: Japanese Patent Laid-Open No. 2002-71756

Disclosure of the invention

Problems to be solved by the invention

[0007] As semiconductor integrated circuits have become larger and more highly integrated, the distance between electrodes of the semiconductor integrated circuit is required to be 100 m or less. As a result, a very large number of electrodes (for example, microbumps) are formed.

[0008] Then, when inspecting a semiconductor integrated circuit, it is conceivable to inspect the semiconductor chip by contacting the probe before forming the micro bumps. However, there is a problem that the bump forming metal pad is scratched by the probe card needle.

[0009] On the other hand, although the technique of Patent Document 1 can determine the quality of the bump shape, there is a problem that it cannot be confirmed whether the main circuit actually operates correctly. Patent Document 2 In the technology, it is necessary to provide test data generation means for generating test data for connection test in the first semiconductor integrated circuit device mounted on the printed board, and there is a problem that hinders high integration.

[0010] In addition, the signal pins of the semiconductor integrated circuit inspection device need to be limited to 512 pins or less in practice. For example, assuming a memory chip having a bit width of 256 bits, 512 pins are required only for input / output bits. In addition, if the address pin and mode control pin are considered, the 512 pin limit will be exceeded.

[0011] On the other hand, the techniques of Patent Documents 3 and 4 require the connection of a printed board to an external device. However, for example, if a semiconductor integrated circuit is highly integrated to 512 bits or more, the number of electrodes becomes 512 or more, and it is virtually impossible to connect all these electrodes to an external device.

The present invention has been proposed to solve the above-described problems, and provides a semiconductor chip and a semiconductor integrated circuit that can efficiently and reliably inspect a highly integrated semiconductor integrated circuit. For the purpose.

Means for solving the problem

[0013] The semiconductor chip according to the present invention is a semiconductor chip that can be mounted on an interposer, and has a minimum pitch interval of 100 m or less, and a plurality of electrodes that connect the wiring in the interposer and the wiring in the semiconductor chip. A plurality of probe electrodes connected to a part of the plurality of electrodes, and a test signal input to the probe electrode, and a wiring in the semiconductor chip connected to the plurality of electrodes And a signal processing means for performing predetermined signal processing based on the test signal divided by the dividing means.

The semiconductor chip is mounted on the interposer via electrodes having a minimum pitch interval of 100 μm or less. The probe electrode is connected to a part of this electrode. Then, the dividing means divides the test signal input to the probe electrode and supplies it to the wiring in the semiconductor chip that is connected to the plurality of electrodes. Then, the signal processing means performs predetermined signal processing based on the divided test signals.

[0015] Therefore, the above invention is connected to each electrode even when it has a multi-bit width electrode. Since a test signal can be supplied to the connected wiring, inspection can be performed efficiently and reliably.

A semiconductor chip according to the present invention is a semiconductor chip that can be mounted on an interposer, and is connected to the signal processing means for performing predetermined signal processing and the signal processing means with a minimum pitch interval of 100 m or less. A plurality of electrodes for connecting the interconnected wiring and the wiring in the interposer, arithmetic processing means connected to each of the plurality of electrodes and performing predetermined arithmetic processing based on a test signal having a wiring strength, And a probe electrode for outputting a calculation result of the calculation processing means.

[0017] Therefore, the above invention can perform a predetermined calculation using the test signal of the wiring force connected to each electrode even in the case of having a multi-bit width electrode. An inspection can be surely performed.

[0018] The semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit in which the first and second semiconductor chips are mounted on an interposer via electrodes having a minimum pitch interval of 100 m or less, and the first semiconductor chip The chip includes an input means for inputting a signal, a first transfer means for transferring a signal input to the input means to a second semiconductor chip via the electrodes having the pitch interval, and the second semiconductor chip. A first receiving means for receiving a signal transferred from the output means, and an output electrode for outputting the signal received by the receiving means, wherein the second semiconductor chip is derived from the first semiconductor chip. Second receiving means for receiving the transferred signal; and second transferring means for transferring the signal received by the second receiving means to the first semiconductor chip via the electrodes of the pitch interval; It is characterized by having

Therefore, in the above invention, the signal input to the first semiconductor chip is transferred to the second semiconductor chip via the first semiconductor chip force and the electrode, and the second semiconductor chip force is also transferred via the electrode. Since the output electrode force is output after the transfer to the first semiconductor chip, the wiring situation in the first and second semiconductor chips and the wiring situation between the electrodes can be inspected efficiently and reliably.

The invention's effect

The present invention efficiently and reliably inspects a semiconductor integrated circuit having a multi-bit width electrode. Brief Description of Drawings

FIG. 1 is a plan view of a semiconductor integrated circuit.

FIG. 2 is a cross-sectional view taken along line I I in FIG.

FIG. 3 is a block diagram showing a configuration of a memory chip.

FIG. 4 is a diagram showing a configuration of an input side of a memory chip.

FIG. 5 is a logic circuit showing the configuration of the selector.

FIG. 6 is a truth table showing selector inputs and outputs.

FIG. 7 is a diagram showing a configuration on the output side of the memory chip.

FIG. 8 is a diagram showing a configuration of an input side of a memory chip.

FIG. 9 is a diagram showing the configuration of the input side of the memory chip.

FIG. 10 is a diagram showing a configuration on the output side of the memory chip 10.

FIG. 11 is a diagram showing a configuration on the output side of the memory chip 10.

FIG. 12 is a diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 13 is a logic circuit showing the configuration of the selector.

FIG. 14 is a truth table showing input / output of the selector.

FIG. 15 is a diagram showing a test signal flow in a test mode.

FIG. 16 is a diagram showing another configuration of the semiconductor integrated circuit according to the third embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

. In addition, the same code | symbol (number) is attached | subjected to the circuit of the same structure, and also a subscript (alphabet) shall be attached | subjected as needed. The following embodiments are merely examples of the present invention.

The design can be changed as appropriate without departing from the scope of the invention.

[First Embodiment]

FIG. 1 is a plan view of a semiconductor integrated circuit. The semiconductor integrated circuit is interposer 1 and

The memory chip 10 and the ASIC chip 80 mounted on the interposer 1 are provided. The interposer 1 is provided with a plurality of probe pads 2.

[0024] The memory chip 10 connects a DRAM 21, which will be described later, to the wiring in the memory chip 10 and the wiring of the interposer 1, and includes a plurality of memory chips 10 arranged at a minimum pitch of 100 μm or less. A micro bump 11 and a plurality of probe pads 12 are provided.

[0025] The ASIC chip 80 is not shown in the figure! The ASIC (specific logic circuit) is connected to the wiring in the ASIC chip 80 and the wiring of the interposer 1 with a minimum pitch of 100 μm or less. A plurality of micro bumps 81 and a plurality of probe pads 82 are arranged.

FIG. 2 is a cross-sectional view taken along the line I I in FIG. On the upper surface of the interposer 1 (the surface facing the memory chip 10 and the ASIC chip 80), a metal wiring pattern 5 having a metal film 3 and a via metal film 4 is formed.

On the other hand, metal wiring patterns 13 and 83 are formed on the lower surfaces (surfaces facing the interposer 1) of the memory chip 10 and the ASIC chip 80, respectively. The metal wiring pattern 13 of the memory chip 10 is connected to the metal wiring pattern 3 of the interposer 1 through the micro bumps 11. The metal wiring pattern 83 of the ASIC chip 80 is connected to the metal wiring pattern 3 of the interposer 1 through the micro bumps 81. As described above, the memory chip 10 and the ASIC chip 80 are mounted face-down on the interposer 1 via the micro bumps 11 and 81, respectively.

FIG. 3 is a block diagram showing a configuration of the memory chip 10. The memory chip 10 selects and outputs one of the signals input to the micro bump 11 and the probe pad 12, a memory circuit 20 including the DRAM 21, and an output destination of a signal supplied from the memory circuit 20. And a selection circuit 15 for switching to a microbump 11 or a probe pad 12.

[0029] The selection circuit 14 selects a signal input to the microbump 11 when the test enable signal TEN is at the TEN power level, and selects a test signal input to the probe pad 12 when the test enable signal TEN is at the H level. select. Note that the A region selection circuit 14 shown in FIG. 3 is connected to one micro bump 11, and the B region selection circuit 14 is connected to a plurality of micro bumps 11.

[0030] When the test enable signal TEN is at the TEN power level, the selection circuit 15 selects the micro bump 11 as the signal output destination, and when the test enable signal TEN is at the H level, the selection circuit 15 selects the probe pad 12 as the signal output destination. select. In addition, the selection circuit 15 in the C region shown in FIG. 3 is connected to one micro bump 11, and the selection circuit 15 in the D region includes a plurality of micro bumps 11. It is connected to the.

[0031] [Configuration example on input side 1: Parallel mode]

FIG. 4 is a diagram showing the configuration of the input side of the memory chip 10. The memory chip 10 includes a latch circuit 22A to 22N that latches a signal input via the microphone bump 11A to L1N, and a latch circuit 22X that latches a test signal input via the microbump 11.

SDATA

A buffer circuit 23 for buffering the test enable signal TEN, a selector 24A for selecting the test signal, a selector 27A to 27N for selecting the signal or the test signal input via the microbump 11, and a buffer circuit 28A to 28N.

The latch circuits 22A to 22N, 22X and the buffer circuit 23 are supplied with a first power supply circuit power voltage VDDQ (not shown). The selectors 24A, 27A to 27N and the buffer circuits 28A to 28N are also supplied with the voltage VDD by the second power supply circuit (not shown). Here, since the selectors 24A and 27A to 27N have the same configuration, the configuration will be described by taking the selector 24A as an example.

FIG. 5 is a logic circuit showing the configuration of the selector 24A. FIG. 6 is a truth table showing the input / output of the selector 24A. The selector 24A includes three NAND circuits 31, 32, and 34, and a NOT circuit 33.

The NAND circuit 32 calculates a NAND (negative product) of binary data input to the B terminal and the S terminal, and outputs binary data N2. The negation circuit 33 calculates NOT of the binary data input to the S terminal, and outputs binary data SB.

The NAND circuit 31 calculates a NAND of the binary data input to the A terminal and the binary data SB, and outputs binary data N1. The NAND circuit 34 calculates a NAND of the binary data N1 and N2, and outputs binary data from the Y terminal. Therefore, as shown in Fig. 6, when the binary data input to the S terminal is L, the selector 24A outputs the binary data input to the A terminal as it is and the binary data input to the S terminal. When the data is H, the binary data input to the B terminal is output as it is.

[0036] (Normal mode)

In the memory chip 10 configured as described above, the micro bump 11 and the probe

TEN "in knot 12 !, even if the test enable signal TEN is input! Enable signal TEN force level), the selectors 24A, 27A to 27N are in a state to output the signal input to the A terminal as it is to the Y terminal force. Therefore, the signals input to each microbump 11A ~: L 1N are latch circuits 22A ~ 22N, selectors 27A ~ 27 in in

N, supplied to each terminal of the DRAM 21 via the buffer circuits 28A to 28N.

[0037] (Test mode)

In test mode, the probe is applied to probe pad 12 and probe pad 12

イネーブル level test enable signal TEN is input to TEN-in T. At this time, selector 24A, 2

EN—in

7A to 27N are in a state where the signal input to the B terminal outputs the Y terminal force as it is.

[0038] When a test signal having a probe strength is input to the probe pad 12, this test is performed.

SDATA-in

The strike signal is distributed in parallel to each of the selectors 27A to 27N via the selector 24A, and is input to each terminal of the DRAM 21 via each buffer circuit 28A to 28N.

Therefore, the memory chip 10 distributes the test signals in parallel and supplies each test signal to the wiring connected to the microphone opening bumps 11A to 11B. Therefore, memory chip 1 in in

0 indicates that the test signal input to the single lobe pad 12 is

SDATA-in

Can be input simultaneously.

[0040] [Configuration example on output side 1: Parallel mode]

FIG. 7 is a diagram showing a configuration on the output side of the memory chip 10. The memory chip 10 performs a predetermined operation based on the buffer circuits 61A to 61N that buffer the signals output from the respective terminals of the DRA M21 and the signals output from the buffer circuits 61A to 61N. An arithmetic circuit 62, buffer circuits 65A to 65N for buffering signals output from the buffer circuits 61A to 61N, and a buffer circuit 65X for buffering signals output from the arithmetic circuit 62 are provided.

[0041] The arithmetic circuit 62 is a circuit that inspects the inside of the memory chip 10 based on signals output from the nother circuits 61A to 61N. For example, an AND circuit, an OR circuit, an XOR (exclusive OR) circuit, etc. There is no particular limitation.

[0042] (Normal mode)

In the memory chip 10 configured as described above, the micro bump 11 and the pro

TEN-out If the test enable signal TEN is input to!

TEN-out

When the test enable signal TEN is at the L level), the signals output from the respective terminals of the DRAM 21 are passed through the buffer circuits 61A to 61N and the micro bumps 11A to L1N.

out out

Output to the interposer 1.

[0043] (Test mode)

When a test is executed on the input side, a signal reflecting each terminal force test signal of DRAM 21 is output. These signals are supplied to the arithmetic circuit 62 via the respective buffer circuits 61A to 61N. The arithmetic circuit 62 performs a predetermined calculation based on the signal supplied with the buffer circuits 61A to 61N, and outputs the calculation result via the buffer circuit 65X and the probe pad 12 (or the micro bump 11).

CKl-out CKl-out

Therefore, the memory chip 10 applies the probe to the probe pad 12 to

CK1-OUT 1 Bupput 12 There are so many terminals just by checking the output signal.

CK1-OUT

The state of the memory chip 10 with the built-in DRAM 21 can be inspected.

[0045] [Second Embodiment]

Next, a second embodiment of the present invention will be described. The same circuits as those in the first embodiment are denoted by the same reference numerals, and circuits different from those in the first embodiment will be mainly described. In the second embodiment, another configuration example of the input side and the output side of the memory chip 10 will be described.

[0046] [Configuration example 2: input side serial mode]

FIG. 8 is a diagram showing the configuration of the input side of the memory chip 10. In addition to the configuration shown in FIG. 4, the memory chip 10 latches a clock that latches a clock input through the micro bump 11.

SCLK-in

Touch circuit 22Y and micro bump 11 Clock input, probe pad 12

SCLK-in SCLK-i further includes a selector 24B for selecting a shift of the clock input to SCLK-i, and flip-flop circuits 25A to 25N for delaying the selected test signal by one clock.

The flip-flop circuits 25A to 25N are connected in series and synchronized with the clock supplied from the selector 24B. Then, the flip-flop circuits 25B to 25N supply the test signal to the selectors 27B to 27N in synchronization with the clock, and supply the test signal to the flip-flop circuit of the next stage. Note that the flip-flop circuit 25A Since there is no flip-flop circuit in the next stage, a test signal is supplied to the selector selector 27A in synchronization with the clock.

[0048] (Normal mode)

TEN "in

If the test enable signal TEN is input to the!

TEN-in

Selector enable signal TEN is at L level), selectors 24A, 24B, and 27A to 27N are in a state to output the signal that is input to the A terminal as it is to the Y terminal. Therefore, the signal input to each microphone opening bump 11 is supplied to each terminal of the DRAM 21 via the latch circuits 22 to 22, the selectors 27 to 27, and the buffer circuits 28 to 28.

[0049] (Test mode)

In test mode, the probe is applied to probe pad 12 and probe pad 12

H level test enable signal TEN is input to TEN-in T. At this time, selector 24A, 2

EN- in

[0050] When a test signal from the probe is input to the probe pad 12,

SDATA-in

The data 24A supplies the test signal to the flip-flop circuit 25N.

[0051] The flip-flop circuit 25N includes a micro bump 11, a latch circuit 22Y, and a selector 24.

SCLK-in

In synchronization with the clock supplied via B, the test signal supplied from the selector 24A is supplied to the selector 27N, and the test signal is supplied to the flip-flop circuit in the next stage. Similarly, the flip-flop circuit 25B includes a micro bump 11 and a latch circuit 22Y.

SCLK-in

In synchronization with the clock supplied via the selector 24B, the test signal to which the previous stage flip-flop circuit power is also supplied is supplied to the selector 27B, and the test signal is supplied to the next stage flip-flop circuit 25A. To do.

As a result, a test signal delayed by one clock is supplied to each of the selectors 27A to 27N. These test signals are supplied to the DRAM 21 via the selectors 27A to 27N and the buffer circuits 28A to 28N.

As described above, in the memory chip 10, the test signal is input to the probe pad 12.

SDATA-in

Then, the test signal is shifted by one clock, and the test signal shifted by one clock is supplied to each of the wirings connected to the microbumps 11A to LIB. As a result, the memory chip 10 can be used for multiple wiring by simply inputting a test signal to a single probe pad 12.

SDATA-in

Test signals that are shifted by one clock at a time can be supplied.

[Configuration example on input side 3: Parallel Z-serial combination mode]

FIG. 9 is a diagram showing the configuration of the input side of the memory chip 10. In addition to the configuration shown in FIG. 8, the memory chip 10 latches a mode signal input via the micro bump 11.

S ODE-in

Mode circuit and probe input to latch circuit 22Z and micro bump 11

SMODE-in

A selector 24C that selects one of the mode signals input to the knot 12 and a mode

SMODE-in

Selectors 26A to 26N for switching signals to be output in response to the control signal.

[0054] The mode signal is a signal that determines whether the test signal is distributed in parallel to each wiring (parallel mode) or whether the test signal shifted by one clock is serially distributed to each wiring (serial mode). . For example, when the mode signal level is high, the parallel mode is selected. When the mode signal is high level, the serial mode is selected.

[0055] The A terminals of the selectors 26A to 26N are all connected to the Y terminal of the selector 24B. The B terminals of the selectors 26A to 26N are connected to the output terminals of the flip-flop circuits 25A to 25N. The S terminals of selectors 26A to 26N are connected to the Y terminal of selector 24C.

[0056] (Normal mode)

TEN "in knot 12 !, even if the test enable signal TEN is input!

TEN-in

Enable signal TEN force level), selectors 24A to 24C and 27A to 27N are in a state to output the signal input to the A terminal with the Y terminal force as it is. Therefore, the signals input to the respective microphone opening bumps 11A to L1N are latch circuits 22 to 22 and selector 2

7A to 27N and buffer circuit 28A to 28N are supplied to each terminal of DRAM21

[0057] (Test mode)

In test mode, the probe is applied to probe pad 12 and probe pad 12

H level test enable signal TEN is input to TEN-in T. At this time, the selector 24A ~

EN—in 24C and 27A to 27N are in a state where the signal input to the B terminal outputs the Y terminal force as it is. The selector 24C supplies the mode signal input to the probe pad 12SMODE to the S terminals of the selectors 26A to 26N.

[0058] Here, in the case of the mode signal power level, the selectors 26A to 26N are in a state of outputting the signals input to the A terminal to the selectors 27A to 27N, respectively. When a test signal having a probe force is input to the probe pad 12, the test signal is sent to the selector 24.

SDATA-in

A is distributed in parallel to each of the selectors 27A to 27N via A, and is input to each terminal of the DRAM 21 via each buffer circuit 28A to 28N.

On the other hand, when the mode signal is at the L level, the selectors 26A to 26N are in a state of outputting the signals input to the B terminal to the selectors 27A to 27N, respectively. When a test signal having a probe force is input to the probe pad 12, the selector 24A selects the test signal.

SDATA-in

Supply to the flip-flop circuit 25N.

[0060] The flip-flop circuit 25N includes a micro bump 11, a latch circuit 22Y, and a selector 24.

SCLK-in

[0062] As described above, the memory chip 10 is connected to each of the micro bumps 11A to L1N.

in in

Depending on the mode signal, the test signal allocated to the normal can be supplied to each wiring, or the test signal distributed serially can be supplied.

[0063] [Configuration example on output side 2: Serial mode]

FIG. 10 is a diagram showing a configuration on the output side of the memory chip 10. The memory chip 10 includes latch circuits 51 A and 5 IB that latch predetermined signals, and a test enable signal TEN. A buffer circuit 52 for buffering and selectors 53A and 53B are provided.

[0064] The latch circuit 51A latches the clock input via the micro bump 11.

SCLK-out

This clock is supplied to the A terminal of the selector 53A. The latch circuit 51B latches the mode signal input via the micro bump 11 and outputs the mode signal to the selector 53.

S ODE-out

Supply to the A terminal of B. The noffer circuit 52 is connected to the micro bump 11 or the probe pad.

TEN-out

Buffer the test enable signal TEN input to

TEN-out

Supply enable signal TEN to S terminal of selector 53A, 53B.

The selector 53A supplies the clock input to the A terminal or B terminal to the flip-flop circuits 64A to 64N, respectively. The selector 53B supplies the mode signal input to the A terminal or the B terminal to the selectors 63B to 64N, respectively.

Further, the memory chip 10 includes buffer circuits 61A to 61N for buffering signals output from the respective terminals of the DRAM 21, selectors 63B to 63N, flip-flop circuits 64A to 64N, and buffer circuits 61A. Buffer circuits 65A to 65N for buffering signals output from ˜61N, and a buffer circuit 65Y for buffering signals output from flip-flop circuit 64N.

[0067] The A terminal of the selector 63B is connected to the buffer circuit 61B, its B terminal is connected to the output terminal of the flip-flop circuit 64A, and its Y terminal is connected to the input terminal of the flip-flop circuit 64B. Note that the input terminal of the flip-flop circuit 64A is connected to the buffer circuit 61A.

[0068] Similarly, the A terminal of selector 63N is connected to buffer circuit 61N, its B terminal is connected to the output terminal of the flip-flop circuit in the preceding stage of flip-flop circuit 64N, and its Y terminal is connected to flip-flop circuit 64N. Connected to the input terminal. Note that the input terminal of the flip-flop circuit 64A is connected to the buffer circuit 61A.

Thus, the flip-flop circuits 64A to 64N are connected in series via the selectors 63B to 61N. Therefore, the flip-flop circuits 64A to 64N shift the signal output from the buffer circuit 61A by one clock at a time so that the buffer circuit 65Y and the probe pad 12

CKl-o

It functions as a shift register that outputs via (or micro bump 11).

[0070] (Normal mode) In the memory chip 10 configured as described above, the micro bump 11 and the pro

TEN-out 1 Bupat 12 !, even if the test enable signal TEN is input to the gap!

TEN-out

When the test enable signal TEN is at the L level), the signals output from the respective terminals of the DRAM 21 are output out through the buffer circuits 61A to 61N and the micro bumps 11A to L1N.

Output to the interposer 1.

[0071] (Test mode)

In test mode, the probe is applied to probe pad 12 and probe pad 12

TEN-out

H level test enable signal TEN is input. Each DRAM21

TEN-out

A signal reflecting the various terminal force test signals is output.

[0072] At this time, the selector 53A is in a state of outputting the clock input to the B terminal as it is from the Y terminal. The selector 53B is in a state of outputting the mode signal input to the B terminal as it is from the Y terminal.

Here, in the case of the mode signal power level, the selectors 63B to 63N output a signal input to the A terminal. For this reason, the flip-flop circuits 64A to 64N hold the signals output from the buffer circuits 61A to 61N. Next, when the mode signal becomes H level, the flip-flop circuits 64A to 64N function as shift registers. Therefore, the signals held in the flip-flop circuits 64A to 64N are output via the buffer circuit 65γ and the probe pad 12 in synchronization with the clock.

CK2-out

As described above, the memory chip 10 converts the signals output from the buffer circuits 61A to 61N to serial and outputs the signals via the probe pad 12. As a result, the probe

CK2-out

D 12 has a large number of terminals just by checking the output signal

CK2-out

The state of the RAM 21 can be easily inspected.

[0075] [Configuration example on output side 2: Serial Z parallel use mode]

FIG. 11 is a diagram showing a configuration on the output side of the memory chip 10. A memory chip 10 shown in FIG. 11 is a combination of the configurations shown in FIGS. Therefore, the memory chip 10 checks the signal output by the probe pad 12 or 12 force.

CK1-OUT CK1-OUT

Therefore, the state of the memory chip 10 with a built-in DRAM 21 having a large number of terminals can be inspected. In the first and second embodiments, the force input side configuration and the output side configuration showing various configurations on the input side and output side of the memory chip 10 can be arbitrarily combined. For example, configuration example 1 may be used on the input side, and configuration example 2 or 3 may be used on the output side. Furthermore, the configuration of the input side and the output side of the ASI C chip 80 can be made the same as in the first and second embodiments.

[0077] [Third Embodiment]

FIG. 12 is a diagram showing a configuration of a semiconductor integrated circuit according to the third embodiment of the present invention. The semiconductor integrated circuit includes an interposer 100, and an ASIC chip 200 and a memory chip 300 mounted on the interposer 100.

[0078] Each wiring of the interposer 100 is connected to each wiring of the ASIC chip 200 via the micro bumps 101 to 114. Each wiring of the interposer 100 is connected to each wiring of the memory chip 300 via the micro bumps 121 to 127.

[0079] The ASIC chip 200 includes latch circuits 201 to 205, 231 and 241, nother circuits 206 to 209, 211, 214, 221, 224, 233, 243 and 246, and flip-flop circuits 212, 222, 235 and 245. And selectors 213, 223, 232, 234, 242 and 244!

[0080] The memory chip 300 includes latch circuits 301 to 305, selectors 310, 320, 343, 353, notfer circuits 311, 321, 342, 344, 352, 354, flip-flop circuits 312, 333, 341, 3 51.

Here, for example, as in the selector 213, the A and B terminals as input terminals and the output terminal

The selector having the Y terminal is configured in the same manner as in FIG. For example, a selector having an A terminal as an input terminal and Y0 and Y1 terminals as output terminals, such as the selector 232, is configured as follows.

FIG. 13 is a logic circuit showing the configuration of selector 232. FIG. 14 is a truth table showing the input / output of the selector 232. Selector 232 consists of two NAND circuits 35, 36 and three NO

T-circuits 37, 38, and 39 are provided.

The NAND circuit 36 calculates a NAND (negative product) of the binary data input to the A terminal and the S terminal, and outputs binary data N2. The negation circuit 37 calculates NOT of the binary data input to the S terminal and outputs binary data SB. The NAND circuit 35 calculates NAND of the binary data input to the A terminal and the binary data SB, and outputs binary data N1. The NOT circuit 38 calculates the NOT of the binary data N1 and outputs the binary data via the Y0 terminal. The NOT circuit 39 calculates the NOT of the binary data N2 and outputs the binary data via the Y1 terminal.

Accordingly, as shown in FIG. 14, when the binary data input to the S terminal is, the selector 232 outputs the binary data input to the A terminal to the Y0 terminal and inputs to the S terminal. If the binary data is H, the binary data input to the A terminal is output as the Y1 terminal force.

Further, on the interposer 100 side shown in FIG. 12, the microbump 101 is an electrode to which a test signal is input, and is connected to the input terminal of the flip-flop circuit 212 via the latch circuit 201 of the ASIC chip 200. ing. The micro bump 102 is an electrode to which a clock for logic (ASIC chip 200) is input, and is connected to the clock input terminals of the flip-flop circuits 212, 222, 235, and 245 via the latch circuit 202. The micro bump 103 is an electrode to which a mode signal for logic (ASIC chip 200) is input, and is connected to the S terminals of the selectors 234 and 244 via the latch circuit 203.

The micro bump 104 is an electrode to which a memory clock is input, and is connected to the memory chip 300 via the latch circuit 204, the buffer circuit 209, and the micro bumps 109 and 123. The micro bump 105 is an electrode to which a memory mode signal is input, and is connected to the memory chip 300 via the latch circuit 205, the sofa circuit 208, and the micro amplifiers 108 and 122.

The micro bump 106 is an electrode to which the test enable signal TEN is input, and is connected to the S terminals of the selectors 213, 223, 232, and 242 via the buffer circuit 206. Further, the micro amplifier 106 is connected to the memory chip 300 via notch circuits 206 and 207 and micro amplifiers 107 and 121.

The A terminal of the selector 213 is connected to the buffer circuit 211, and its B terminal is connected to the output terminal of the flip-flop circuit 212. The Y terminal of the selector 213 is connected to the memory chip 300 via a notch circuit 214 and micro bumps 110 and 124.

The A terminal of the selector 223 is connected to the buffer circuit 221, and the B terminal is connected to the output terminal of the flip-flop circuit 222. The input terminal of the flip-flop circuit 222 The child is connected to the output terminal of the flip-flop circuit 212. The Y terminal of the selector 223 is connected to the memory chip 300 via the buffer circuit 224 and the micro bumps 111 and 125.

The A terminal of the selector 232 is connected to the memory chip 300 via the latch circuit 231 and the micro bumps 112 and 126. The Y0 terminal of selector 232 is connected to buffer circuit 233, and its Y1 terminal is connected to the B terminal of selector 234. The A terminal of the selector 234 is connected to the output terminal of the flip-flop circuit 222, and its Y terminal is connected to the input terminal of the flip-flop circuit.

Similarly, the A terminal of the selector 242 is connected to the memory chip 300 via the latch circuit 241 and the micro bumps 113 and 127. The YO terminal of the selector 242 is connected to the buffer circuit 243, and its Y1 terminal is connected to the B terminal of the selector 244. The A terminal of the selector 244 is connected to the output terminal of the preceding flip-flop circuit, and its Y terminal is connected to the input terminal of the flip-flop circuit 245. The output terminal of the flip-flop circuit 245 is connected to the micro bump 114 via the buffer circuit 246.

On the other hand, on the memory chip 300 side, the micro bump 121 is connected to the S terminals of the selectors 310, 320, 343, and 353 via the latch circuit 301. The micro amplifier 122 is connected to the clock input terminals of the flip-flop circuits 312, 333, 341, and 351 via the latch circuit 302. The micro bump 123 is connected to the S terminal of the selector 322 via the latch circuit 303.

Micro bumps 124 and 125 are connected to A terminals of selectors 310 and 320 via latch circuits 304 and 305, respectively. The micro bumps 126 and 127 are connected to the Y terminals of the selectors 343 and 353 via buffer circuits 344 and 354, respectively.

The Y0 terminal of the selector 310 is connected to the buffer circuit 311, and the Y1 terminal is connected to the input terminal of the flip-flop circuit 312. The output terminal of the flip-flop circuit 312 is connected to the A terminal of the selector 322.

The Y0 terminal of the selector 320 is connected to the buffer circuit 321 and the Y1 terminal is connected to the input terminal of the flip-flop circuit 322. The output terminal of the flip-flop circuit 322 is connected to the input terminal of the flip-flop circuit 333. The A terminal of the selector 343 is connected to the buffer circuit 342, and its B terminal is connected to the output terminal of the flip-flop circuit 341. Similarly, the A terminal of the selector 353 is connected to the buffer circuit 352, and its B terminal is connected to the output terminal of the flip-flop circuit 351.

[0098] (Normal mode)

In the semiconductor integrated circuit configured as described above, when the test enable signal TEN is input to the micro bump 106!, NA! /, (When the test enable signal is at the TEN power level), the selector 213 of the ASIC chip 200, The 223 is in a state where the signal input to the A terminal outputs the Y terminal output as it is. In addition, the selectors 232 and 242 enter a state in which the signal input to the A terminal is output from the YO terminal. Similarly, the selectors 310 and 320 of the ASIC chip 200 are in a state of outputting the signal input to the A terminal from the YO terminal. In addition, the selectors 343 and 353 are in a state of outputting the signal input to the A terminal as it is from the Y terminal.

[0099] Therefore, the signal output from the ASIC (not shown) of the ASIC chip 200 is buffered.

211, selector 213, knot: Γ-times 214, microphone P-nops 110 and 124, latch-times 304, selector 310, and buffer circuit 311, supplied to DRAM (not shown) of the memory chip 300.

[0100] The signal read from the DRAM of the memory chip 300 includes a buffer circuit 342, a selector 343, a knot: Γ times 344, a microphone P amplifier 126, 112, a latch times 231, a selector 23 2, The data is supplied to the ASIC of the ASIC chip 200 via the buffer circuit 333.

[0101] (Test mode)

FIG. 15 is a diagram showing the flow of test signals in the test mode. In the test mode, the H level test enable signal TEN is input to the micro bump 106. It is assumed that a predetermined clock is supplied to the microphone opening bumps 102 and 104.

[0102] The selectors 213 and 223 of the ASIC chip 200 are in a state of outputting the signal input to the B terminal as it is from the Y terminal. In addition, the selectors 232 and 242 are in a state of outputting the signal input to the A terminal from the Y1 terminal. Similarly, the selectors 310 and 320 of the ASIC chip 200 are in a state of outputting the signal input to the A terminal from the Y1 terminal. In addition, the selectors 343 and 353 are in a state in which the signal input to the B terminal is output as it is from the Y terminal. [0103] When a test signal is input to the microbump 101, the test signal is sequentially held in the flip-flop circuits 212 and 222 (arrows).

Next, when an H-level memory mode signal is input to the microbump 105, the test signal held in the flip-flop circuit 212 passes through the selector 213, the microbumps 110 and 124, and the selector 310. And held in the flip-flop circuit 312. Similarly, the test signal held in the flip-flop circuit 222 is held in the flip-flop circuit 333 via the selector 223, the micro bumps 111 and 125, and the selectors 320 and 322 (arrow B).

Next, when an L-level memory mode signal is input to the microbump 105, the selector 322 supplies the test signal held in the flip-flop circuit 312 to the flip-flop circuit 333. That is, the test signal held in the flip-flop circuits 312 and 333 is shifted to the next output destination flip-flop circuit (arrow C).

Next, when an H-level logic mode signal is input to the microbump 103, for example, the test signal held in the flip-flop circuit 341 includes the selector 343, the micro-nops 126 and 112, and the selector 232. , 234, the flip-flop circuit 235 is held. The test signal held in the flip-flop circuit 351 is held in the flip-flop circuit 245 via the selector 353, the micro amplifiers 127 and 113, and the selectors 242 and 244 (arrow D).

Next, when an L-level logic mode signal is input to the microbump 103, the selectors 234 and 244 enter a state in which the signal input to the A terminal is output from the Y terminal. Therefore, the test signals held in the flip-flop circuits 235 and 245 are sequentially shifted to the flip-flop circuit in the next stage. As a result, the signal is output from the flip-flop circuit 245 via the output test signal force notch circuit 246 and the micro bump 114 (arrow E).

Therefore, an inspection device (not shown) can inspect not only the wiring state in the ASIC chip 200 and the memory chip 300 but also the wiring state between the micro bumps by examining the test signal output from the micro bump 114. it can.

[0109] [Other configurations]

FIG. 16 is a diagram showing another configuration of the semiconductor integrated circuit according to the third embodiment of the present invention. is there. The same circuits as those in FIG. 12 are denoted by the same reference numerals, and different points from FIG. 12 will be mainly described.

[0110] The interposer 100 includes micro bumps 106a and 106b instead of the micro bumps 106 shown in FIG. The microbump 106a is an electrode to which a memory test enable signal TEN is input, and is connected to the microbump 123 via the latch circuit 210, the buffer circuit 209, and the microbump 109. The micro bump 106b is an electrode to which the logic test enable signal TEN is input, and is connected to the S terminals of the selectors 213, 223, 232, and 242 via the buffer circuit 206. Therefore, the A SIC chip 200 shown in FIG. 16 is different from FIG. 12 and FIG. 15 in that the number of input test enable signals TEN is different, but the other processes are the same.

On the other hand, on the memory chip 300 side, the micro bump 121 is connected to the S terminal of the selector 322 via the latch circuit 301. The micro bump 123 is connected to the S terminals of the selectors 310, 320, 343, and 353 via the buffer circuit 307.

[0112] (Test mode)

When the H level memory test enable signal TEN is input to the micro bump 106a, the selectors 310 and 320 are in a state of outputting the signal input to the A terminal from the Y1 terminal. The selectors 343 and 353 are in a state of outputting the signal input to the B terminal from the Y terminal.

At this time, the test signal held in the flip-flop circuit 212 is held in the flip-flop circuit 312 via the micro bumps 110 and 124 and the selector 310. Similarly, the test signal held in the flip-flop circuit 222 is held in the flip-flop circuit 333 via the micro bumps 111 and 125.

Furthermore, when an H-level logic mode signal is input to microbump 105, selector 322 enters a state of outputting a signal input to the B terminal. At this time, the test signals held in the flip-flop circuits 312 and 333 are shifted to the next output destination flip-flop circuit.

[0115] As described above, the ASIC chip 200 sequentially scan-shifts the test signals held in the flip-flop circuit, and after the scan-shift of the test signals, the ASIC chip 200 performs the operations shown in FIGS. The test signal is transferred to the ASIC chip 200 in the same manner as described above.

As described above, the semiconductor integrated circuit according to the third embodiment scan-shifts the test signal within the ASIC chip 200 and transfers it to the memory chip 300 via the micro bumps. Further, the semiconductor integrated circuit scan-shifts the test signal in the memory chip 300, transfers the test signal to the ASIC chip 200 via the micro bump, and then scan-shifts again in the ASIC chip 200. Output to the outside via the bump 114. Therefore, by inspecting the test signal output from the micro bump 114, the entire wiring state including the connection state between the micro bumps can be inspected.

[0117] As described above, the wafer test (first and second embodiments) of the semiconductor chips connected by micro bumps via the interposer and the test after assembly (third embodiment) are efficiently executed. can do. In particular, it is possible to efficiently test a semiconductor integrated circuit on which a semiconductor chip having a multi-bit width is mounted.

[0118] It should be noted that the present invention is not limited to the above-described embodiments, but can be applied to those modified in design within the scope described in the claims. is there.

[0119] For example, in the third embodiment, the test enable signal TEN, the mode signal, and the clock are

It is input to the ASIC chip 200! However, it may be input to the memory chip 300!

[0120] In the first to third embodiments, the number of probe pads is not particularly limited, and may be less than the number of micro bumps.

Explanation of symbols

[0121] 1, 100 interposer

10, 300 meage chip

11 Micro bump

12 Probe pad

80, 200 ASIC chip

Claims

The scope of the claims

[1] A semiconductor chip that can be mounted on an interposer,

A plurality of electrodes having a minimum pitch interval of 100 m or less and connecting the wiring in the interposer and the wiring in the semiconductor chip;

A plurality of probe electrodes connected to a part of the plurality of electrodes;

Dividing means for dividing a test signal input to the probe electrode and supplying the divided test signal to a wiring connected to the plurality of electrodes in the semiconductor chip;

Signal processing means for performing predetermined signal processing based on the test signal divided by the dividing means;

A semiconductor chip comprising:

[2] The dividing means divides the test signal input to the probe electrode, and the divided test signals are connected in parallel to wirings in the semiconductor chip and connected to the plurality of electrodes. Supply

The semiconductor chip according to claim 1.

[3] The distribution unit divides the test signal input to the probe electrode into test signals having different delay times, and each of the divided test signals is a wiring in the semiconductor chip and includes the plurality of electrodes. Supply serially to the wiring connected to

The semiconductor chip according to claim 1.

[4] The dividing means divides the test signal input to the probe electrode, and each divided test signal is connected in parallel to the wiring in the semiconductor chip and connected to the plurality of electrodes. A first mode to be supplied and a test signal input to the probe electrode are divided into test signals having different delay times, and each of the divided test signals is a wiring in the semiconductor chip, and the plurality of electrodes It is possible to switch between the second mode of supplying serially to the wiring connected to

The semiconductor chip according to claim 1.

[5] A semiconductor chip that can be mounted on an interposer,

Signal processing means for performing predetermined signal processing;

The minimum pitch interval is 100 m or less, the wiring connected to the signal processing means and the A plurality of electrodes connecting the wiring in the interposer,

Arithmetic processing means connected to each of the plurality of electrodes and performing a predetermined arithmetic processing based on a wiring force test signal;

A probe electrode from which the calculation result of the calculation processing means is output;

A semiconductor chip comprising:

[6] A semiconductor chip that can be mounted on an interposer,

Signal processing means for performing predetermined signal processing;

A plurality of electrodes that connect the wiring connected to the signal processing means and the wiring in the interposer with a minimum pitch interval of 100 m or less;

Signal conversion means for converting a test signal of the wiring force connected to each of the plurality of electrodes into a serial signal;

A probe electrode from which the conversion result of the signal conversion means is output;

A semiconductor chip comprising:

[7] A semiconductor chip that can be mounted on an interposer,

Signal processing means for performing predetermined signal processing;

A first probe electrode that outputs a calculation result of the calculation processing means;

A second probe electrode from which the conversion result of the signal conversion means is output;

A semiconductor chip comprising:

[8] The signal processing means is a memory circuit or a theoretical circuit for specific applications.

The semiconductor chip according to claim 1, wherein the force is any one of claims 1 to 7.

[9] A semiconductor integrated circuit in which first and second semiconductor chips are mounted on an interposer via electrodes having a minimum pitch interval of 100 μm or less, The first semiconductor chip includes input means for inputting a signal, and first transfer means for transferring the signal input to the input means to the second semiconductor chip via the electrodes having the pitch interval. A first receiving means for receiving a signal transferred from the second semiconductor chip, and an output electrode for outputting the signal received by the receiving means,

The second semiconductor chip includes a second receiving means for receiving a signal transferred from the first semiconductor chip, and a signal received by the second receiving means with an electrode at the pitch interval. And a second transfer means for transferring to the first semiconductor chip through the semiconductor integrated circuit.

The signal input to the input means is at least one of a test signal, a first mode signal for controlling the operation of the first semiconductor chip, and a second mode signal for controlling the operation of the second semiconductor chip. Be

The semiconductor integrated circuit according to claim 9.