TWI464754B - Resistance module and manufacturing method thereof - Google Patents

Resistance module and manufacturing method thereof Download PDF

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TWI464754B
TWI464754B TW099124220A TW99124220A TWI464754B TW I464754 B TWI464754 B TW I464754B TW 099124220 A TW099124220 A TW 099124220A TW 99124220 A TW99124220 A TW 99124220A TW I464754 B TWI464754 B TW I464754B
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layer
contact
resistor
resistive layer
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TW099124220A
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TW201205607A (en
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Chien Hua Chen
Teck-Chong Lee
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Advanced Semiconductor Eng
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Description

電阻器模組及其製造方法Resistor module and method of manufacturing same

本發明是有關於一種電阻器模組及其製造方法,且特別是有關於一種具有多層結構之電阻器模組及其製造方法。The present invention relates to a resistor module and a method of fabricating the same, and more particularly to a resistor module having a multilayer structure and a method of fabricating the same.

傳統的電阻元件係個別製作完成後再一顆顆分別固定於基板上。然而,傳統電阻器的體積較大,當基板所需的電阻元件的數量愈多時,需要較大面積的基板,導致最終產品的尺寸過大。並且,傳統電阻元件須一顆顆地插入或組裝至基板中,相當耗時且耗成本。The conventional resistor elements are individually fixed to the substrate after being individually fabricated. However, the size of the conventional resistor is large, and the larger the number of resistive elements required for the substrate, the larger the area of the substrate is required, resulting in an oversized size of the final product. Moreover, conventional resistive elements have to be inserted or assembled into the substrate one by one, which is quite time consuming and costly.

本發明係有關於一種電阻器模組及其製造方法,電阻器模組具有多層電阻層,可同時提供多個電阻元件。此外,透過多層電阻層的設計,可增加電阻的電性路徑長度,以增加電阻值。The invention relates to a resistor module and a manufacturing method thereof. The resistor module has a plurality of resistor layers, and a plurality of resistor elements can be simultaneously provided. In addition, through the design of the multilayer resistance layer, the electrical path length of the resistor can be increased to increase the resistance value.

根據本發明之一方面,提出一種電阻器模組。電阻器模組包括一基板及數個電阻結構。每個電阻結構形成於基板上並包括一第一電阻層、一介電層及一第二電阻層。第一電阻層形成於基板上。介電層形成於第一電阻層之上表面上。第二電阻層形成介電層上。According to an aspect of the invention, a resistor module is provided. The resistor module includes a substrate and a plurality of resistor structures. Each of the resistor structures is formed on the substrate and includes a first resistive layer, a dielectric layer, and a second resistive layer. The first resistance layer is formed on the substrate. A dielectric layer is formed on the upper surface of the first resistive layer. The second resistive layer is formed on the dielectric layer.

根據本發明之另一方面,提出一種電阻器模組之製造方法。製造方法包括以下步驟。提供一基板;形成一第一電阻層於基板上,第一電阻層定義一第一接點及一第二接點;形成一介電層覆蓋第一電阻層之上表面,介電層具有一第一開孔及一第二開孔,第一開孔露出第一接點且第二開孔露出第二接點;以及,形成一第二電阻層於介電層上,第二電阻層透過第一開孔電性連接於第一接點。According to another aspect of the present invention, a method of fabricating a resistor module is provided. The manufacturing method includes the following steps. Providing a substrate; forming a first resistive layer on the substrate, the first resistive layer defining a first contact and a second contact; forming a dielectric layer covering the upper surface of the first resistive layer, the dielectric layer having a a first opening and a second opening, the first opening exposing the first contact and the second opening exposing the second contact; and forming a second resistive layer on the dielectric layer, the second resistive layer transmitting The first opening is electrically connected to the first contact.

為讓本發明之上述內容能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:In order to make the above-mentioned contents of the present invention more comprehensible, the preferred embodiments are described below, and the detailed description is as follows:

第一實施例First embodiment

請參照第1圖,其繪示依照本發明第一實施例之電阻器模組的上視圖。電阻器模組100包括基板102及數個電阻結構104。基板102例如是晶圓(wafer)、氧化矽基板或含有塑膠或樹脂成份的半導體基板。電阻結構104形成於基板102上。Referring to FIG. 1, a top view of a resistor module in accordance with a first embodiment of the present invention is shown. The resistor module 100 includes a substrate 102 and a plurality of resistor structures 104. The substrate 102 is, for example, a wafer, a ruthenium oxide substrate, or a semiconductor substrate containing a plastic or resin component. The resistive structure 104 is formed on the substrate 102.

請參照第2圖,其繪示第1圖中方向2-2’的剖視圖。電阻結構104包括第一電阻層106、第二電阻層108、第一介電層110、第二介電層128、第一電性觸點(electrical contact)134及第二電性觸點136。其中,第一電阻層106形成於基板102上,第一介電層110形成於第一電阻層106之上表面124上,使第二電阻層108形成於第一介電層110之上表面150上後,第一電阻層106與第二電阻層108構成上下重疊之雙層結構。Please refer to Fig. 2, which is a cross-sectional view taken along line 2-2' in Fig. 1. The resistor structure 104 includes a first resistive layer 106, a second resistive layer 108, a first dielectric layer 110, a second dielectric layer 128, a first electrical contact 134, and a second electrical contact 136. The first resistive layer 106 is formed on the substrate 102, the first dielectric layer 110 is formed on the upper surface 124 of the first resistive layer 106, and the second resistive layer 108 is formed on the upper surface 150 of the first dielectric layer 110. After the upper layer, the first resistance layer 106 and the second resistance layer 108 constitute a two-layer structure in which the upper and lower layers overlap.

本實施例中,第一電阻層106與第二電阻層108係電性連接。相較於傳統的單層電阻結構,本實施例之電阻結構104藉由第一電阻層106與第二電阻層108所構成之雙層結構來增加電阻層的長度,大幅提高電阻結構104之電阻值。本發明之電阻層的層數並不限於雙層,於其它實施態樣中,電阻器模組之電阻層的層數亦可超過二層。In this embodiment, the first resistance layer 106 and the second resistance layer 108 are electrically connected. Compared with the conventional single-layer resistor structure, the resistor structure 104 of the present embodiment increases the length of the resistor layer by the two-layer structure formed by the first resistor layer 106 and the second resistor layer 108, and greatly increases the resistance of the resistor structure 104. value. The number of layers of the resistive layer of the present invention is not limited to two layers. In other embodiments, the number of layers of the resistive layer of the resistor module may exceed two.

如第1圖及第2圖所示,整個第二電阻層108隔著第一介電層110與第一電阻層106重疊,使電阻結構104的鋪設範圍較小,可節省基板102的面積,然此非用以限制本發明。於一實施態樣中,如第1圖所示,電阻結構104’之第二電阻層108’中僅一部分隔著第一介電層110(第一介電層110未繪示於第1圖)重疊於第一電阻層106’。As shown in FIGS. 1 and 2, the entire second resistance layer 108 overlaps with the first resistance layer 106 via the first dielectric layer 110, so that the laying range of the resistance structure 104 is small, and the area of the substrate 102 can be saved. This is not intended to limit the invention. In one embodiment, as shown in FIG. 1 , only a portion of the second resistive layer 108 ′ of the resistive structure 104 ′ is interposed between the first dielectric layer 110 (the first dielectric layer 110 is not shown in FIG. 1 ). ) overlapping the first resistive layer 106'.

請繼續參照第1圖,雖然電阻結構104’的鋪設範圍較電阻結構104大,然第二電阻層108’的寬度W較大,使電阻結構104’的電阻值減小。進一步地說,透過電阻層之長度及寬度的設計,可設計出不同的電阻值。一般而言,電阻層的長度愈長,電阻值愈大,而電阻層的寬度愈寬,電阻值愈小。Continuing to refer to Fig. 1, although the resistive structure 104' is laid over the resistive structure 104, the width W of the second resistive layer 108' is large, and the resistance of the resistive structure 104' is reduced. Further, different resistance values can be designed by designing the length and width of the resistive layer. In general, the longer the length of the resistive layer, the larger the resistance value, and the wider the width of the resistive layer, the smaller the resistance value.

此外,如第1圖所示,數個第二電阻層108鋪設出的範圍大致上含蓋基板102的整個上表面122,可降低電磁干擾(electromagnetic interference,EMI)的影響與干擾。Further, as shown in FIG. 1, the range in which the plurality of second resistance layers 108 are laid substantially covers the entire upper surface 122 of the lid substrate 102, and the influence and interference of electromagnetic interference (EMI) can be reduced.

如第2圖所示,第二電阻層108與第一電阻層106係位於不同的垂直高度位置,即第二電阻層108往基板102的厚度方向延伸發展。如此一來,在有限的基板面積下可往基板102的厚度方向形成較多數量的電阻結構。電阻器模組100之電阻結構104的數量大約介於28個至32個之間,然此非用以限制本發明,電阻結構104的數量可以超過32個或小於28個。As shown in FIG. 2, the second resistance layer 108 and the first resistance layer 106 are located at different vertical height positions, that is, the second resistance layer 108 extends toward the thickness direction of the substrate 102. As a result, a larger number of resistance structures can be formed in the thickness direction of the substrate 102 under a limited substrate area. The number of the resistor structures 104 of the resistor module 100 is between about 28 and 32. However, instead of limiting the invention, the number of resistor structures 104 may exceed 32 or less.

第一介電層110覆蓋第一電阻層106之上表面124並具有第一開孔112及第二開孔114,第一電阻層106之上表面124定義第一接點116及第二接點118,第一開孔112露出第一接點116,而第二開孔114露出第二接點118。The first dielectric layer 110 covers the upper surface 124 of the first resistive layer 106 and has a first opening 112 and a second opening 114. The upper surface 124 of the first resistive layer 106 defines a first contact 116 and a second contact. 118, the first opening 112 exposes the first contact 116, and the second opening 114 exposes the second contact 118.

第二電阻層108之上表面126定義第三接點120,第二電阻層108之一部分108a形成於第一開孔112內並電性連接於第一接點116,使第二電阻層108電性連接於第一電阻層106。第二電阻層108之該部分108a大致上垂直於第一電阻層106。The upper surface 126 of the second resistive layer 108 defines a third contact 120. One portion 108a of the second resistive layer 108 is formed in the first opening 112 and electrically connected to the first contact 116, so that the second resistive layer 108 is electrically connected. It is connected to the first resistance layer 106. The portion 108a of the second resistive layer 108 is substantially perpendicular to the first resistive layer 106.

第一接點116、第二接點118及第三接點120係定義於電阻層之表面上的電性接觸區域(region),銲線、電性觸點、接墊、凸塊金屬、表面處理層(surface finish)或其它電性結構可形成於該電性連接區上。The first contact 116, the second contact 118, and the third contact 120 are electrical contact regions defined on the surface of the resistive layer, the bonding wires, the electrical contacts, the pads, the bump metal, and the surface. A surface finish or other electrical structure may be formed on the electrical connection region.

第一接點116、第二接點118及第三接點120的位置決定第二接點118至第三接點120間的電性路徑長度,藉此可設計出不同的電阻值。本實施例之第一接點116、第二接點118及第三接點120的位置可視實際的電阻設計值而定,不受本發明實施所限制。The positions of the first contact 116, the second contact 118, and the third contact 120 determine the length of the electrical path between the second contact 118 and the third contact 120, whereby different resistance values can be designed. The positions of the first contact 116, the second contact 118, and the third contact 120 of this embodiment may be determined by actual resistance design values, and are not limited by the implementation of the present invention.

第二接點118及第三接點120可作為第一電阻層106與第二電阻層108所構成之結構的正、負極。第二接點118及第三接點120可透過銲線(solder wire)電性連接於一外部電路,例如是觸控面板的控制模組。The second contact 118 and the third contact 120 can serve as positive and negative electrodes of the structure formed by the first resistive layer 106 and the second resistive layer 108. The second contact 118 and the third contact 120 can be electrically connected to an external circuit through a solder wire, such as a control module of the touch panel.

雖然第三接點120的位置重疊於第一電阻層106,然此非用以限制本發明,第三接點120的位置亦可不重疊於第一電阻層106。舉例來說,於其它實施態樣中,第二電阻層108之一部分亦可不重疊於第一電阻層106,而第三接點120定義於第二電阻層108之該部分上,如此第三接點120的位置便不重疊於第一電阻層106。Although the position of the third contact 120 overlaps the first resistive layer 106, the third contact 120 may not overlap the first resistive layer 106. For example, in other implementations, a portion of the second resistive layer 108 may not overlap the first resistive layer 106, and the third contact 120 is defined on the portion of the second resistive layer 108, such that the third interface The position of the point 120 does not overlap the first resistive layer 106.

第二介電層128覆蓋第二電阻層108並具有第三開孔130及第四開孔132。第四開孔132露出第二開孔114及第二接點118,第三開孔130露出第三接點120。The second dielectric layer 128 covers the second resistance layer 108 and has a third opening 130 and a fourth opening 132. The fourth opening 132 exposes the second opening 114 and the second contact 118 , and the third opening 130 exposes the third contact 120 .

第一電性觸點134形成於第三開孔130內及第三接點120上以電性連接於第二電阻層108,並用以與外部電路電性接觸。第二電性觸點136形成於第二開孔114內、第四開孔132內及第二接點118上以電性連接於第一電阻層106,並用以與外部電路電性接觸。The first electrical contact 134 is formed in the third opening 130 and the third contact 120 to be electrically connected to the second resistive layer 108 for electrically contacting an external circuit. The second electrical contact 136 is formed in the second opening 114, in the fourth opening 132, and the second contact 118 to be electrically connected to the first resistive layer 106 for electrically contacting an external circuit.

第一電性觸點134及第二電性觸點136例如是鋁墊(pad),其可提供較佳的電性連接品質外,亦可保護第二接點118及第三接點120,避免其受到環境的破壞。The first electrical contact 134 and the second electrical contact 136 are, for example, aluminum pads, which can provide better electrical connection quality, and can also protect the second contact 118 and the third contact 120. Avoid being damaged by the environment.

雖然第一電性觸點134及第二電性觸點136以鋁墊(pad)為例說明,然此非用以限定本發明。於一實施態樣中,第一電性觸點134及第二電性觸點136亦可為凸塊金屬(Under-Bump Metallization,UBM)。Although the first electrical contact 134 and the second electrical contact 136 are exemplified by an aluminum pad, the present invention is not limited thereto. In one embodiment, the first electrical contact 134 and the second electrical contact 136 may also be Under-Bump Metallization (UBM).

以下係以第3圖並搭配第4A至4D圖說明第1圖之電阻器模組的製造方法。第3圖繪示依照本發明第一實施例之電阻器模組的製造流程圖,第4A至4D圖繪示第1圖之電阻器模組的製造示意圖。Hereinafter, a method of manufacturing the resistor module of Fig. 1 will be described with reference to Fig. 3 in conjunction with Figs. 4A to 4D. FIG. 3 is a flow chart showing the manufacture of the resistor module according to the first embodiment of the present invention, and FIGS. 4A to 4D are diagrams showing the manufacturing of the resistor module of FIG. 1.

於步驟S102中,提供如第4A圖所示之基板102。基板102定義有數個(第4A圖僅繪示出單個)電阻器模組定義區R。後續步驟所形成的結構對應地形成於該些電阻器模組定義區R內。於切割步驟中沿著電阻器模組定義區R的範圍進行切割動作,即可切出多個電阻器模組100。進一步地說,本實施例之電阻器模組之製造方法可一次製造數個電阻器模組,提升生產量,然此非用以限制本發明。於一實施態樣中,基板102可僅定義單個電阻器模組定義區R。In step S102, the substrate 102 as shown in FIG. 4A is provided. The substrate 102 is defined with a plurality of (the FIG. 4A only shows a single) resistor module defining region R. The structures formed in the subsequent steps are correspondingly formed in the resistor module defining regions R. A plurality of resistor modules 100 can be cut out by performing a cutting operation along the range of the resistor module defining region R in the cutting step. Further, the manufacturing method of the resistor module of the present embodiment can manufacture a plurality of resistor modules at a time to increase the throughput, which is not intended to limit the present invention. In one embodiment, the substrate 102 can define only a single resistor module definition region R.

然後,於步驟S104中,如第4A圖所示,形成數個第一電阻層106於基板102之上表面122上,並於第一電阻層106之上表面124定義第一接點116及第二接點118。Then, in step S104, as shown in FIG. 4A, a plurality of first resistive layers 106 are formed on the upper surface 122 of the substrate 102, and a first contact 116 and a first surface are defined on the upper surface 124 of the first resistive layer 106. Two junctions 118.

於本步驟S104中,可應用濺鍍(sputter)方式形成一電阻材料於基板102之上表面122上。然後再應用圖案化技術圖案化該電阻材料以形成該些第一電阻層106。其中,該電阻材料例如是氮化鉭(TaN)、PbTiO3、二氧化釕(RuO2)、磷化鎳(NiP)、鉻化鎳(NiCr)及NCAlSi等高電阻值材料。In this step S104, a resistive material may be formed on the upper surface 122 of the substrate 102 by a sputtering method. The resistive material is then patterned using a patterning technique to form the first resistive layers 106. The resistive material is, for example, a high-resistance material such as tantalum nitride (TaN), PbTiO3, ruthenium dioxide (RuO2), nickel phosphide (NiP), nickel chrome (NiCr), and NCAlSi.

上述圖案化技術例如是微影製程(photolithography)、化學蝕刻(chemical etching)、電漿蝕刻(plasma etching)、雷射鑽孔(laser drilling)、機械鑽孔(mechanical drilling)或雷射切割。The above patterning techniques are, for example, photolithography, chemical etching, plasma etching, laser drilling, mechanical drilling, or laser cutting.

然後,於步驟S106中,如第4B圖所示,形成第一介電層110覆蓋第一電阻層106之上表面124。第一介電層110具有第一開孔112及第二開孔114,第一開孔112露出第一接點116,且第二開孔114露出第二接點118。Then, in step S106, as shown in FIG. 4B, the first dielectric layer 110 is formed to cover the upper surface 124 of the first resistance layer 106. The first dielectric layer 110 has a first opening 112 and a second opening 114 . The first opening 112 exposes the first contact 116 , and the second opening 114 exposes the second contact 118 .

為清楚表示電阻結構,第4B至4D圖僅繪示出單個電阻結構。To clearly show the resistance structure, the 4B to 4D drawings only show a single resistance structure.

於本步驟S106中,可應用數種塗佈技術之一種來形成一介電材料,介電材料例如是光阻劑。該些塗佈技術例如是印刷(printing)、旋塗(spinning)或噴塗(spraying)。之後,應用上述圖案化技術圖案化該介電材料以形成如第4B圖所示之第一介電層110。In this step S106, one of several coating techniques may be applied to form a dielectric material such as a photoresist. Such coating techniques are, for example, printing, spinning or spraying. Thereafter, the dielectric material is patterned using the patterning techniques described above to form a first dielectric layer 110 as shown in FIG. 4B.

然後,於步驟S108中,如第4C圖所示,形成第二電阻層108於第一介電層110上,第二電阻層108之上表面126定義第三接點120。第二電阻層108透過第一開孔112電性連接於第一電阻層106之第一接點116。Then, in step S108, as shown in FIG. 4C, the second resistive layer 108 is formed on the first dielectric layer 110, and the upper surface 126 of the second resistive layer 108 defines the third contact 120. The second resistance layer 108 is electrically connected to the first contact 116 of the first resistance layer 106 through the first opening 112 .

然後,於步驟S110中,如第4D圖所示,形成第二介電層128覆蓋第二電阻層108。第二介電層128具有第三開孔130及第四開孔132,第四開孔132露出第二開孔114及第二接點118,而第三開孔130露出第三接點120。形成第二介電層128的方法相似於形成第一介電層110的方法,在此不再贅述。Then, in step S110, as shown in FIG. 4D, a second dielectric layer 128 is formed to cover the second resistance layer 108. The second dielectric layer 128 has a third opening 130 and a fourth opening 132. The fourth opening 132 exposes the second opening 114 and the second contact 118, and the third opening 130 exposes the third contact 120. The method of forming the second dielectric layer 128 is similar to the method of forming the first dielectric layer 110, and details are not described herein again.

然後,於步驟S112中,應用例如是濺鍍的方式,分別形成如第2圖所示之第一電性觸點134及第二電性觸點136於第三接點120及第二接點118上。Then, in step S112, the first electrical contact 134 and the second electrical contact 136 as shown in FIG. 2 are formed on the third contact 120 and the second contact, respectively, by sputtering. 118 on.

步驟S112之後,對應各電阻器模組100的電阻器模組定義區R的範圍,切割第一介電層110、第二介電層128及基板102,以形成數個如第1圖所示之電阻器模組100。After step S112, the first dielectric layer 110, the second dielectric layer 128, and the substrate 102 are cut corresponding to the range of the resistor module defining region R of each resistor module 100 to form a plurality of images as shown in FIG. The resistor module 100.

第二實施例Second embodiment

請參照第5A及5B圖,第5A圖繪示依照本發明第二實施例之電阻器模組的上視圖,第5B圖繪示第5A圖中方向5B-5B’的剖視圖。第二實施例中與第一實施例相同之處沿用相同標號,在此不再贅述。第二實施例之電阻器模組200與第一實施例之電阻器模組100不同之處在於,電阻器模組200中電阻結構204之第二電阻層208具有第四接點238,其可作為第二電阻層208之正或負極。5A and 5B, FIG. 5A is a top view of the resistor module according to the second embodiment of the present invention, and FIG. 5B is a cross-sectional view of the direction 5B-5B' in FIG. 5A. The same reference numerals are used in the second embodiment in the same manner as the first embodiment, and details are not described herein again. The resistor module 200 of the second embodiment is different from the resistor module 100 of the first embodiment in that the second resistor layer 208 of the resistor structure 204 in the resistor module 200 has a fourth contact 238, which can As the positive or negative electrode of the second resistance layer 208.

如第5A圖所示,電阻器模組200包括基板102及數個電阻結構204。如第5B圖所示,電阻結構204形成於基板102上。電阻結構204包括第一電阻層206、第二電阻層208、第一介電層210、第二介電層228、第一電性觸點234及第二電性觸點236。第一電阻層206形成於基板102上。第一介電層210形成於第一電阻層206之上表面224上。As shown in FIG. 5A, the resistor module 200 includes a substrate 102 and a plurality of resistor structures 204. As shown in FIG. 5B, the resistor structure 204 is formed on the substrate 102. The resistor structure 204 includes a first resistive layer 206, a second resistive layer 208, a first dielectric layer 210, a second dielectric layer 228, a first electrical contact 234, and a second electrical contact 236. The first resistance layer 206 is formed on the substrate 102. The first dielectric layer 210 is formed on the upper surface 224 of the first resistive layer 206.

第二電阻層208包括第一子電阻層208a及第二子電阻層208b,第一子電阻層208a與第二子電阻層208b在空間上係彼此隔離。第一子電阻層208a透過第一開孔212電性連接於第一接點216而第二子電阻層208b透過第二開孔214電性連接於第二接點218,使第一子電阻層208a電性連接於第二子電阻層208b。The second resistance layer 208 includes a first sub-resistive layer 208a and a second sub-resistive layer 208b. The first sub-resistive layer 208a and the second sub-resistive layer 208b are spatially isolated from each other. The first sub-resistive layer 208a is electrically connected to the first contact 216 through the first opening 212, and the second sub-resistor layer 208b is electrically connected to the second contact 218 through the second opening 214, so that the first sub-resistive layer 208a is electrically connected to the second sub resistance layer 208b.

第一子電阻層208a之一部分形成於第一開孔212內並與第一電阻層206上下重疊,其餘部分係與第一子電阻層208a錯開而不重疊,第二子電阻層208b亦同。A portion of the first sub-resistive layer 208a is formed in the first opening 212 and overlaps the first resistive layer 206, and the remaining portion is offset from the first sub-resistive layer 208a without overlapping, and the second sub-resistive layer 208b is also the same.

由上述第一實施例及第二實施例可知,第一電阻層206與第二電阻層208的走向以及正、負極位置配置具有多種變化,可提供多種電性路徑長度及電阻值的實施態樣。It can be seen from the first embodiment and the second embodiment that the orientations of the first resistive layer 206 and the second resistive layer 208 and the positions of the positive and negative electrodes have various changes, and various embodiments of the electrical path length and the resistance value can be provided. .

第一電阻層206之上表面224定義第一接點216及第二接點218,第二電阻層208之上表面226定義第三接點220及第四接點238,第三接點220及第四接點238可作為第二電阻層208之正、負極。其中,第三接點220及第四接點238的位置不與第一電阻層206重疊。The upper surface 224 of the first resistive layer 206 defines a first contact 216 and a second contact 218, and the upper surface 226 of the second resistive layer 208 defines a third contact 220 and a fourth contact 238, and a third contact 220 The fourth contact 238 can serve as the positive and negative electrodes of the second resistive layer 208. The positions of the third contact 220 and the fourth contact 238 do not overlap with the first resistance layer 206.

第二介電層228具有第三開孔230及第四開孔232,第三開孔230及第四開孔232分別露出第三接點220及第四接點238。第一電性觸點234及第二電性觸點236分別形成於第三接點220及第四接點238上以與外部電路電性接觸。第一電性觸點234及第二電性觸點236可以是鋁墊或凸塊金屬,本實施例之第一電性觸點234及第二電性觸點236係以鋁墊為例作說明。The second dielectric layer 228 has a third opening 230 and a fourth opening 232. The third opening 230 and the fourth opening 232 respectively expose the third contact 220 and the fourth contact 238. The first electrical contact 234 and the second electrical contact 236 are respectively formed on the third contact 220 and the fourth contact 238 to be in electrical contact with an external circuit. The first electrical contact 234 and the second electrical contact 236 may be aluminum pads or bump metal. The first electrical contact 234 and the second electrical contact 236 of the embodiment are exemplified by aluminum pads. Description.

第5A圖之電阻器模組200的製造方法相似於第一實施例之電阻器模組100的製造方法,在此不再重複贅述。The manufacturing method of the resistor module 200 of FIG. 5A is similar to the manufacturing method of the resistor module 100 of the first embodiment, and details are not described herein again.

第三實施例Third embodiment

請參照第6圖,其繪示依照本發明第三實施例之電阻器模組的剖視圖。第三實施例中與第一實施例相同之處沿用相同標號,在此不再贅述。第三實施例之電阻器模組300與第一實施例之電阻器模組100不同之處在於,電阻器模組300之第一電阻層306與第二電阻層308在空間上及在電性上係彼此隔離。Referring to FIG. 6, a cross-sectional view of a resistor module in accordance with a third embodiment of the present invention is shown. In the third embodiment, the same reference numerals are used for the same parts as the first embodiment, and details are not described herein again. The resistor module 300 of the third embodiment is different from the resistor module 100 of the first embodiment in that the first resistive layer 306 and the second resistive layer 308 of the resistor module 300 are spatially and electrically The upper lines are isolated from each other.

電阻器模組300包括基板102及數個電阻結構304(第6圖僅繪示單個電阻結構304)。電阻結構304形成於基板102上。電阻結構304包括第一電阻層306、第二電阻層308、第一介電層310、第二介電層328、第一電性觸點334、第二電性觸點336、第三電性觸點344及第四電性觸點346。The resistor module 300 includes a substrate 102 and a plurality of resistor structures 304 (only a single resistor structure 304 is illustrated in FIG. 6). A resistor structure 304 is formed on the substrate 102. The resistor structure 304 includes a first resistive layer 306, a second resistive layer 308, a first dielectric layer 310, a second dielectric layer 328, a first electrical contact 334, a second electrical contact 336, and a third electrical Contact 344 and fourth electrical contact 346.

第一電阻層306形成於基板102上並定義第一接點316及第二接點318,第一介電層310形成於第一電阻層306上,第二電阻層308形成於第一介電層310上並定義第三接點320及第四接點338。第二電阻層308之第三接點320及第四接點338係與第一電阻層306電性隔離。進一步地說,電阻結構304具有電性分離之二個電阻層,分別係第一電阻層306及第二電阻層308。其中,第一接點316及第二接點318可作為第一電阻層306之正、負極,而第三接點320及第四接點338可作為第二電阻層308之正、負極。The first resistive layer 306 is formed on the substrate 102 and defines a first contact 316 and a second contact 318. The first dielectric layer 310 is formed on the first resistive layer 306, and the second resistive layer 308 is formed on the first dielectric. A third contact 320 and a fourth contact 338 are defined on layer 310. The third contact 320 and the fourth contact 338 of the second resistive layer 308 are electrically isolated from the first resistive layer 306. Further, the resistor structure 304 has two electrically resistive layers, which are respectively a first resistive layer 306 and a second resistive layer 308. The first contact 316 and the second contact 318 can serve as the positive and negative electrodes of the first resistive layer 306, and the third contact 320 and the fourth contact 338 can serve as the positive and negative terminals of the second resistive layer 308.

此外,請參照第7圖,其繪示依照本發明一實施例之電阻器模組的剖視圖。電阻器模組400之第一電性觸點434可透過銲線448電性連接於第三電性觸點444。如此一來,第一電阻層306電性連接於第二電阻層308,使第一電阻層306與第二電阻層308電性連接而成為單一電阻。相較於分離之第一電阻層306與第二電阻層308,由第一電阻層306與第二電阻層308所連接成的單一電阻,其電性路徑增長、電阻值增大。反過來說,若欲得到電阻值較小的電阻結構,可比照第6圖之電阻器模組,於電阻結構中形成多層電性分離之電阻層。In addition, please refer to FIG. 7, which is a cross-sectional view of a resistor module in accordance with an embodiment of the present invention. The first electrical contact 434 of the resistor module 400 can be electrically connected to the third electrical contact 444 through the bonding wire 448. As a result, the first resistive layer 306 is electrically connected to the second resistive layer 308, and the first resistive layer 306 and the second resistive layer 308 are electrically connected to form a single resistor. Compared with the separated first resistive layer 306 and the second resistive layer 308, a single resistor connected by the first resistive layer 306 and the second resistive layer 308 has an electrical path increasing and an increased resistance value. Conversely, if a resistor structure having a small resistance value is to be obtained, a plurality of electrically separated resistor layers may be formed in the resistor structure in accordance with the resistor module of FIG.

以下係以第3圖並搭配第8圖說明第6圖之電阻器模組的製造方法。第8圖繪示第6圖之電阻器模組的製造示意圖。製造電阻器模組300之步驟S102至S106相似於製造電阻器模組100之步驟S102及S106,在此不再重複說明,以下從步驟S108開始說明。Hereinafter, a method of manufacturing the resistor module of Fig. 6 will be described with reference to Fig. 3 and Fig. 8 . FIG. 8 is a schematic view showing the manufacture of the resistor module of FIG. 6. Steps S102 to S106 of manufacturing the resistor module 300 are similar to steps S102 and S106 of manufacturing the resistor module 100, and the description thereof will not be repeated here, and the following description will be made from step S108.

於步驟S108中,如第8圖所示,形成第二電阻層308於第一介電層310上。第二電阻層308包括第三子電阻層308a、第四子電阻層308b1及第五子電阻層308b2。第三子電阻層308a之上表面326定義第三接點320及第四接點338。In step S108, as shown in FIG. 8, a second resistance layer 308 is formed on the first dielectric layer 310. The second resistance layer 308 includes a third sub-resistive layer 308a, a fourth sub-resistive layer 308b1, and a fifth sub-resistive layer 308b2. The upper surface 326 of the third sub-resistive layer 308a defines a third contact 320 and a fourth contact 338.

第四子電阻層308b1形成於第一介電層310之第一開孔312內及第一接點316上。第五子電阻層308b2形成於第一介電層310之第二開孔314內及第二接點318上,第四子電阻層308b1及第五子電阻層308b2大致上垂直於第一電阻層306。The fourth sub-resistive layer 308b1 is formed in the first opening 312 of the first dielectric layer 310 and on the first contact 316. The fifth sub resistance layer 308b2 is formed in the second opening 314 of the first dielectric layer 310 and the second contact 318. The fourth sub resistance layer 308b1 and the fifth sub resistance layer 308b2 are substantially perpendicular to the first resistance layer. 306.

於本步驟S108中,可應用濺鍍技術形成上述電阻材料於第一介電層310之上表面350上。然後再應用上述圖案化技術圖案化該電阻材料,以形成彼此隔離之第三子電阻層308a、第四子電阻層308b1與第五子電阻層308b2。In this step S108, the above-mentioned resistive material may be formed on the upper surface 350 of the first dielectric layer 310 by using a sputtering technique. The resistive material is then patterned using the patterning technique described above to form a third sub-resistive layer 308a, a fourth sub-resistive layer 308b1, and a fifth sub-resistive layer 308b2 that are isolated from each other.

然後,於步驟S110中,形成如第6圖所示之第二介電層328覆蓋第二電阻層308。Then, in step S110, a second dielectric layer 328 as shown in FIG. 6 is formed to cover the second resistive layer 308.

然後,於步驟S112中,分別形成如第6圖所示之第一電性觸點334、第二電性觸點336、第三電性觸點344及第四電性觸點346於第一接點316、第二接點318、第三接點320及第四接點338上。然後,對應各電阻器模組300的電阻器模組定義區的範圍,切割第一介電層310、第二介電層328及基板102,以形成數個如第6圖所示之電阻器模組300。Then, in step S112, the first electrical contact 334, the second electrical contact 336, the third electrical contact 344, and the fourth electrical contact 346 are formed as shown in FIG. The contact 316, the second contact 318, the third contact 320 and the fourth contact 338 are connected. Then, corresponding to the range of the resistor module defining regions of each resistor module 300, the first dielectric layer 310, the second dielectric layer 328, and the substrate 102 are cut to form a plurality of resistors as shown in FIG. Module 300.

此外,於另一實施例中,請第9圖所示,其繪示依照本發明另一實施例之電阻器模組的剖視圖,電阻器模組500更包括種子層(seed layer)552。電阻器模組500的製造方法中於步驟S110之後更包括以下步驟:以濺鍍或電鍍方式形成種子層552於第一接點316、第二接點318、第三接點320及第四接點338上;然後,以電鍍方式形成第一電性觸點534、第二電性觸點536、第三電性觸點544及第四電性觸點546於種子層552上,以形成如第9圖所示之電阻器模組500。其中,第一電性觸點534、第二電性觸點536、第三電性觸點544及第四電性觸點546係凸塊金屬。In addition, in another embodiment, FIG. 9 is a cross-sectional view showing a resistor module according to another embodiment of the present invention. The resistor module 500 further includes a seed layer 552. In the manufacturing method of the resistor module 500, after the step S110, the method further includes the steps of: forming the seed layer 552 on the first contact 316, the second contact 318, the third contact 320, and the fourth connection by sputtering or electroplating. The first electrical contact 534, the second electrical contact 536, the third electrical contact 544, and the fourth electrical contact 546 are formed on the seed layer 552 by electroplating to form, for example, The resistor module 500 shown in FIG. The first electrical contact 534, the second electrical contact 536, the third electrical contact 544, and the fourth electrical contact 546 are bump metal.

第四實施例Fourth embodiment

請參照第10圖,其繪示依照本發明第四實施例之電阻器模組的剖視圖。第四實施例中與第三實施例相同之處沿用相同標號,在此不再贅述。第四實施例之電阻器模組600與第三實施例之電阻器模組300不同之處在於,電阻器模組600之第一電性觸點634及第二電性觸點636形成於第一電阻層606上。Referring to FIG. 10, a cross-sectional view of a resistor module in accordance with a fourth embodiment of the present invention is shown. The same reference numerals are used in the fourth embodiment in the same manner as the third embodiment, and details are not described herein again. The resistor module 600 of the fourth embodiment is different from the resistor module 300 of the third embodiment in that the first electrical contact 634 and the second electrical contact 636 of the resistor module 600 are formed in the first A resistor layer 606.

電阻器模組600包括基板102及數個電阻結構604(第10圖僅繪示出單個電阻結構604)。電阻結構604形成於基板102上。電阻結構604包括第一電阻層606、第二電阻層608、第一介電層610、第二介電層628、第一電性觸點634、第二電性觸點636、第三電性觸點644及第四電性觸點646。The resistor module 600 includes a substrate 102 and a plurality of resistor structures 604 (only a single resistor structure 604 is depicted in FIG. 10). A resistor structure 604 is formed on the substrate 102. The resistor structure 604 includes a first resistive layer 606, a second resistive layer 608, a first dielectric layer 610, a second dielectric layer 628, a first electrical contact 634, a second electrical contact 636, and a third electrical Contact 644 and fourth electrical contact 646.

第一電性觸點634及第二電性觸點636係接墊,其形成於第一電阻層606上,而第三電性觸點644及第四電性觸點646係接墊,其形成於第二電阻層608上。The first electrical contact 634 and the second electrical contact 636 are connected to the pad, and the third electrical contact 644 and the fourth electrical contact 646 are connected to the pad. Formed on the second resistance layer 608.

第一介電層610覆蓋部分之第一電性觸點634及部分之第二電性觸點636,第一電性觸點634及第二電性觸點636夾設於第一介電層610與第一電阻層606之間,使第一電性觸點634及第二電性觸點636更穩固地形成於第一電阻層606上。The first dielectric layer 610 covers a portion of the first electrical contact 634 and a portion of the second electrical contact 636. The first electrical contact 634 and the second electrical contact 636 are sandwiched between the first dielectric layer. Between the 610 and the first resistive layer 606, the first electrical contact 634 and the second electrical contact 636 are more stably formed on the first resistive layer 606.

相似於第一介電層610的技術特徵,第二介電層628覆蓋部分之第三電性觸點644及部分之第四電性觸點646,第三電性觸點644及第四電性觸點646夾設於第二電阻層608與第二介電層628之間,使第三電性觸點644及第四電性觸點646更穩固地形成於第二電阻層608上。Similar to the technical features of the first dielectric layer 610, the second dielectric layer 628 covers a portion of the third electrical contact 644 and a portion of the fourth electrical contact 646, the third electrical contact 644 and the fourth electrical The contact 646 is disposed between the second resistive layer 608 and the second dielectric layer 628 to form the third electrical contact 644 and the fourth electrical contact 646 more firmly on the second resistive layer 608.

以下係以第11圖並搭配第12A至12D圖說明第10圖之電阻器模組的製造示意圖。第11圖繪示依照本發明第四實施例之電阻器模組的製造流程圖,第12A至12D圖繪示第10圖之電阻器模組的製造示意圖。第11圖之步驟S602及S604相似於第3圖之步驟S102及S104,在此不再重複贅述,以下係從步驟S606開始說明。The manufacturing diagram of the resistor module of Fig. 10 will be described below with reference to Fig. 11 and with reference to Figs. 12A to 12D. 11 is a flow chart showing the manufacture of a resistor module according to a fourth embodiment of the present invention, and FIGS. 12A to 12D are diagrams showing the manufacture of the resistor module of FIG. Steps S602 and S604 of FIG. 11 are similar to steps S102 and S104 of FIG. 3, and the description thereof will not be repeated here, and the following description will be made from step S606.

於步驟S606中,如第12A圖所示,形成第一電性觸點634及第二電性觸點636於第一電阻層606之第一接點616及第二接點618上。第一接點616及第二接點618係定義於第一電阻層606之上表面624上。In step S606, as shown in FIG. 12A, the first electrical contact 634 and the second electrical contact 636 are formed on the first contact 616 and the second contact 618 of the first resistive layer 606. The first contact 616 and the second contact 618 are defined on the upper surface 624 of the first resistive layer 606.

然後,於步驟S608中,如第12B圖所示,形成第一介電層610覆蓋第一電阻層606、部份之第一電性觸點634及部分之第二電性觸點636。第一介電層610具有第一開孔612及第二開孔614,其分別露出第一電性觸點634及第二電性觸點636。Then, in step S608, as shown in FIG. 12B, the first dielectric layer 610 is formed to cover the first resistive layer 606, a portion of the first electrical contact 634, and a portion of the second electrical contact 636. The first dielectric layer 610 has a first opening 612 and a second opening 614 respectively exposing the first electrical contact 634 and the second electrical contact 636.

然後,於步驟S610中,如第12C圖所示,形成第二電阻層608於第一介電層610之上表面650上。第二電阻層608之上表面626定義第三接點620及第四接點638,第二電阻層608並與第一電阻層606係電性分離。Then, in step S610, as shown in FIG. 12C, a second resistance layer 608 is formed on the upper surface 650 of the first dielectric layer 610. The upper surface 626 of the second resistive layer 608 defines a third contact 620 and a fourth contact 638, and the second resistive layer 608 is electrically separated from the first resistive layer 606.

然後,於步驟S612中,如第12D圖所示,形成第三電性觸點644及第四電性觸點646於第二電阻層608之第三接點620及第四接點638上。Then, in step S612, as shown in FIG. 12D, the third electrical contact 644 and the fourth electrical contact 646 are formed on the third contact 620 and the fourth contact 638 of the second resistive layer 608.

然後,於步驟S614中,形成如第10圖所示之第二介電層628覆蓋部分之第三電性觸點644、部分之第四電性觸點646及第二電阻層608。第二介電層628具有第三開孔630及第四開孔632,其分別露出第三電性觸點644及第四電性觸點646。至此,形成第10圖之電阻器模組600。Then, in step S614, a portion of the third electrical contact 644, a portion of the fourth electrical contact 646, and a second resistive layer 608 are formed by the second dielectric layer 628 as shown in FIG. The second dielectric layer 628 has a third opening 630 and a fourth opening 632 respectively exposing the third electrical contact 644 and the fourth electrical contact 646. So far, the resistor module 600 of FIG. 10 is formed.

此外,於另一實施例中,請參照第13圖,其繪示依照本發明其它實施例之電阻器模組的剖視圖。相較於電阻器模組600,電阻器模組700更包括種子層752、第一凸塊金屬754、第二凸塊金屬756、第三凸塊金屬758及第四凸塊金屬760。以下係以第11圖說明電阻器模組700的製造方法。於步驟S612後,電阻器模組700的製造方法更包括:以濺鍍或電鍍方式形成種子層752於第一電性觸點634、第二電性觸點636、第三電性觸點644及第四電性觸點646上。然後,形成第一凸塊金屬754、第二凸塊金屬756、第三凸塊金屬758及第四凸塊金屬760於種子層752上,以形成如第13圖所示之電阻器模組700。In addition, in another embodiment, please refer to FIG. 13 , which illustrates a cross-sectional view of a resistor module in accordance with other embodiments of the present invention. The resistor module 700 further includes a seed layer 752, a first bump metal 754, a second bump metal 756, a third bump metal 758, and a fourth bump metal 760, as compared to the resistor module 600. Hereinafter, a method of manufacturing the resistor module 700 will be described with reference to FIG. After the step S612, the manufacturing method of the resistor module 700 further includes: forming a seed layer 752 on the first electrical contact 634, the second electrical contact 636, and the third electrical contact 644 by sputtering or electroplating. And the fourth electrical contact 646. Then, a first bump metal 754, a second bump metal 756, a third bump metal 758, and a fourth bump metal 760 are formed on the seed layer 752 to form the resistor module 700 as shown in FIG. .

本發明上述實施例所揭露之電阻器模組及其製造方法,具有多項特徵,列舉部份特徵說明如下:The resistor module and the manufacturing method thereof disclosed in the above embodiments of the present invention have a plurality of features, and some of the features are as follows:

(1).第二電阻層與第一電阻層係位於不同的垂直高度位置,即第二電阻層可往基板的厚度方向延伸發展。如此一來,在有限的基板面積下可形成較多數量的電阻結構。(1) The second resistance layer and the first resistance layer are located at different vertical height positions, that is, the second resistance layer can extend toward the thickness direction of the substrate. As a result, a larger number of resistor structures can be formed with a limited substrate area.

(2).數個第一電阻層及數個第二電阻層鋪設成的範圍大致上含蓋基板的上表面,具有降低EMI干擾的效果。(2) The range in which the plurality of first resistance layers and the plurality of second resistance layers are laid substantially covers the upper surface of the cover substrate, and has an effect of reducing EMI interference.

(3).第一電阻層可與第二電阻層電性連接或電性分離,實際應用可視設計需求而定。若第一電阻層及第二電阻層電性連接,則可增加電性路徑的長度以提高電阻值;若第一電阻層及第二電阻層電性分離,則可增加電阻的數目。(3) The first resistance layer can be electrically connected or electrically separated from the second resistance layer, and the actual application depends on the visual design requirements. If the first resistance layer and the second resistance layer are electrically connected, the length of the electrical path can be increased to increase the resistance value; if the first resistance layer and the second resistance layer are electrically separated, the number of resistors can be increased.

(4).電阻器模組係以半導體技術完成,大幅地縮小最終電阻器模組的體積。(4). The resistor module is completed by semiconductor technology, which greatly reduces the volume of the final resistor module.

綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100、200、300、400、500、600、700...電阻器模組100, 200, 300, 400, 500, 600, 700. . . Resistor module

102...基板102. . . Substrate

104、104’、204、304、604...電阻結構104, 104', 204, 304, 604. . . Resistance structure

106、106’、206、306、606...第一電阻層106, 106', 206, 306, 606. . . First resistance layer

108、108’、208、308、608...第二電阻層108, 108', 208, 308, 608. . . Second resistance layer

110、210、310、610...第一介電層110, 210, 310, 610. . . First dielectric layer

112、212、312、612...第一開孔112, 212, 312, 612. . . First opening

114、214、314、614...第二開孔114, 214, 314, 614. . . Second opening

116、216、316、616...第一接點116, 216, 316, 616. . . First contact

118、218、318、618...第二接點118, 218, 318, 618. . . Second contact

120、220、320、620...第三接點120, 220, 320, 620. . . Third junction

122、124、126、150、224、226、326、350、624、626、650...上表面122, 124, 126, 150, 224, 226, 326, 350, 624, 626, 650. . . Upper surface

128、228、628...第二介電層128, 228, 628. . . Second dielectric layer

130、230、630...第三開孔130, 230, 630. . . Third opening

132、232、632...第四開孔132, 232, 632. . . Fourth opening

134、234、334、434、534、634...第一電性觸點134, 234, 334, 434, 534, 634. . . First electrical contact

136、236、336、536、636...第二電性觸點136, 236, 336, 536, 636. . . Second electrical contact

238、338、638...第四接點238, 338, 638. . . Fourth junction

208a...第一子電阻層208a. . . First sub-resistive layer

208b...第二子電阻層208b. . . Second sub-resist layer

308a...第三子電阻層308a. . . Third sub-resist layer

308b1...第四子電阻層308b1. . . Fourth sub-resist layer

308b2...第五子電阻層308b2. . . Fifth sub-resistance layer

344、444、544、644...第三電性觸點344, 444, 544, 644. . . Third electrical contact

346、546、646...第四電性觸點346, 546, 646. . . Fourth electrical contact

448...銲線448. . . Welding wire

552、752...種子層552, 752. . . Seed layer

754...第一凸塊金屬754. . . First bump metal

756...第二凸塊金屬756. . . Second bump metal

758...第三凸塊金屬758. . . Third bump metal

760...第四凸塊金屬760. . . Fourth bump metal

108a...一部分108a. . . portion

R...電阻器模組定義區R. . . Resistor module definition area

S102-S112、S602-614...步驟S102-S112, S602-614. . . step

W...寬度W. . . width

第1圖繪示依照本發明第一實施例之電阻器模組的上視圖。1 is a top view of a resistor module in accordance with a first embodiment of the present invention.

第2圖繪示第1圖中方向2-2’的剖視圖。Fig. 2 is a cross-sectional view showing the direction 2-2' in Fig. 1.

第3圖繪示依照本發明第一實施例之電阻器模組的製造流程圖。FIG. 3 is a flow chart showing the manufacture of the resistor module in accordance with the first embodiment of the present invention.

第4A至4D圖繪示第1圖之電阻器模組的製造示意圖。4A to 4D are schematic views showing the manufacture of the resistor module of Fig. 1.

第5A圖繪示依照本發明第二實施例之電阻器模組的上視圖。FIG. 5A is a top view of a resistor module in accordance with a second embodiment of the present invention.

第5B圖繪示第5A圖中方向5B-5B’的剖視圖。Fig. 5B is a cross-sectional view showing the direction 5B-5B' in Fig. 5A.

第6圖繪示依照本發明第三實施例之電阻器模組的剖視圖。Figure 6 is a cross-sectional view showing a resistor module in accordance with a third embodiment of the present invention.

第7圖繪示依照本發明一實施例之電阻器模組的剖視圖。FIG. 7 is a cross-sectional view showing a resistor module in accordance with an embodiment of the present invention.

第8圖繪示第6圖之電阻器模組的製造示意圖。FIG. 8 is a schematic view showing the manufacture of the resistor module of FIG. 6.

第9圖繪示依照本發明另一實施例之電阻器模組的剖視圖。FIG. 9 is a cross-sectional view showing a resistor module in accordance with another embodiment of the present invention.

第10圖繪示依照本發明第四實施例之電阻器模組的剖視圖。Figure 10 is a cross-sectional view showing a resistor module in accordance with a fourth embodiment of the present invention.

第11圖繪示依照本發明第四實施例之電阻器模組的製造流程圖。11 is a flow chart showing the manufacture of a resistor module in accordance with a fourth embodiment of the present invention.

第12A至12D圖繪示第10圖之電阻器模組的製造示意圖。12A to 12D are schematic views showing the manufacture of the resistor module of Fig. 10.

第13圖繪示依照本發明其它實施例之電阻器模組的剖視圖。Figure 13 is a cross-sectional view showing a resistor module in accordance with other embodiments of the present invention.

100...電阻器模組100. . . Resistor module

102...基板102. . . Substrate

104、104’...電阻結構104, 104’. . . Resistance structure

106、106’...第一電阻層106, 106’. . . First resistance layer

108、108’...第二電阻層108, 108’. . . Second resistance layer

W...寬度W. . . width

Claims (18)

一種電阻器模組,包括:一基板;以及複數個電阻結構,形成於該基板上,各該電阻結構包括:一第一電阻層,形成於該基板上;一介電層,形成於該第一電阻層之上表面上;及一第二電阻層,形成該介電層上。A resistor module includes: a substrate; and a plurality of resistor structures formed on the substrate, each of the resistor structures including: a first resistor layer formed on the substrate; a dielectric layer formed on the substrate a surface of the upper surface of the resistor layer; and a second resistor layer formed on the dielectric layer. 如申請專利範圍第1項所述之電阻器模組,其中該第一電阻層與該第二電阻層係電性連接。The resistor module of claim 1, wherein the first resistance layer is electrically connected to the second resistance layer. 如申請專利範圍第2項所述之電阻器模組,其中該介電層具有一第一開孔及一第二開孔,該第一電阻層定義一第一接點及一第二接點,該第一開孔露出該第一接點且該第二開孔露出該第二接點,該第二電阻層透過該第一開孔電性連接於該第一接點。The resistor module of claim 2, wherein the dielectric layer has a first opening and a second opening, the first resistance layer defining a first contact and a second contact The first opening exposes the first contact and the second opening exposes the second contact, and the second resistive layer is electrically connected to the first contact through the first opening. 如申請專利範圍第3項所述之電阻器模組,該第二電阻層包括一第一子電阻層及一第二子電阻層,該第一子電阻層與該第二子電阻層係彼此隔離,且該第一子電阻層透過該第一開孔電性連接於該第一接點而該第二子電阻層透過該第二開孔電性連接於該第二接點。The resistor module of claim 3, wherein the second resistor layer comprises a first sub-resistive layer and a second sub-resistive layer, the first sub-resistive layer and the second sub-resistive layer are connected to each other The first sub-resistive layer is electrically connected to the first contact through the first opening, and the second sub-resistive layer is electrically connected to the second contact through the second opening. 如申請專利範圍第3項所述之電阻器模組,其中該第二電阻層更定義一第三接點,各該電阻結構更包括:一電性觸點(electrical contact),形成於該第三接點上。The resistor module of claim 3, wherein the second resistor layer further defines a third contact, each of the resistor structures further includes: an electrical contact formed on the first Three contacts. 如申請專利範圍第5項所述之電阻器模組,其中該電性觸點係凸塊金屬(Under-Bump Metallizationm,UBM)或鋁墊。The resistor module of claim 5, wherein the electrical contact is an Under-Bump Metallization (UBM) or an aluminum pad. 如申請專利範圍第5項所述之電阻器模組,其中各該電阻結構更包括:一種子層(seed layer),形成於該電性觸點上;以及一凸塊金屬,形成於該種子層上。The resistor module of claim 5, wherein each of the resistor structures further comprises: a seed layer formed on the electrical contact; and a bump metal formed on the seed On the floor. 如申請專利範圍第5項所述之電阻器模組,其中各該電阻結構更包括:一種子層,形成於該電性觸點與該第二電阻層之間。The resistor module of claim 5, wherein each of the resistor structures further comprises: a sub-layer formed between the electrical contact and the second resistive layer. 如申請專利範圍第1項所述之電阻器模組,其中該第二電阻層之至少一部分隔著該介電層重疊於該第一電阻層。The resistor module of claim 1, wherein at least a portion of the second resistive layer overlaps the first resistive layer via the dielectric layer. 如申請專利範圍第1項所述之電阻器模組,其中該第二電阻層更定義一第三接點及一第四接點,該第三接點及該第四接點與該第一電阻層係電性隔離。The resistor module of claim 1, wherein the second resistor layer further defines a third contact and a fourth contact, the third contact and the fourth contact and the first The resistive layer is electrically isolated. 如申請專利範圍第10項所述之電阻器模組,其中各該電阻結構更包括:一銲線(solder wire),電性連接該第一接點與該第三接點。The resistor module of claim 10, wherein each of the resistor structures further comprises: a solder wire electrically connected to the first contact and the third contact. 如申請專利範圍第1項所述之電阻器模組,其中該第一電阻層及該第一電阻層的材質係氮化鉭(TaN)、PbTiO3、二氧化釕(RuO2)、磷化鎳(NiP)、鉻化鎳(NiCr)與NCAlSi中至少一者。The resistor module of claim 1, wherein the first resistive layer and the first resistive layer are made of tantalum nitride (TaN), PbTiO3, ruthenium dioxide (RuO2), and nickel phosphide ( At least one of NiP), nickel chromium (NiCr) and NCAlSi. 一種電阻器模組之製造方法,包括:提供一基板;形成一第一電阻層於該基板上,該第一電阻層定義一第一接點及一第二接點;形成一介電層覆蓋該第一電阻層之上表面,該介電層具有一第一開孔及一第二開孔,該第一開孔露出該第一接點且該第二開孔露出該第二接點;以及形成一第二電阻層於該介電層上,該第二電阻層透過該第一開孔電性連接於該第一接點。A method for manufacturing a resistor module, comprising: providing a substrate; forming a first resistor layer on the substrate, the first resistor layer defining a first contact and a second contact; forming a dielectric layer covering The first resistive layer has a first opening and a second opening, the first opening exposing the first contact and the second opening exposing the second contact; And forming a second resistor layer on the dielectric layer, the second resistor layer being electrically connected to the first contact through the first opening. 如申請專利範圍第13項所述之製造方法,其中於形成該第二電阻層之該步驟中,該第二電阻層包括一第一子電阻層及一第二子電阻層,該第一子電阻層與該第二子電阻層係電性隔離,且該第一子電阻層透過該第一開孔電性連接於該第一接點,而該第二子電阻層透過該第二開孔電性連接於該第二接點。The manufacturing method of claim 13, wherein in the step of forming the second resistive layer, the second resistive layer comprises a first sub-resistive layer and a second sub-resistive layer, the first sub- The second sub-resistive layer is electrically connected to the first sub-resistor layer, and the first sub-resistive layer is electrically connected to the first contact through the first opening, and the second sub-resistive layer passes through the second opening Electrically connected to the second contact. 如申請專利範圍第13項所述之製造方法,其中於形成該第二電阻層之該步驟中,該第二電阻層更定義一第三接點,更包括:形成一電性觸點於該第三接點上。The manufacturing method of claim 13, wherein in the step of forming the second resistive layer, the second resistive layer further defines a third contact, further comprising: forming an electrical contact On the third junction. 如申請專利範圍第15項所述之製造方法,更包括:形成一種子層於該電性觸點上;以及形成一凸塊金屬於該種子層上。The manufacturing method of claim 15, further comprising: forming a sub-layer on the electrical contact; and forming a bump metal on the seed layer. 如申請專利範圍第15項所述之製造方法,其中該電性觸點係凸塊金屬或鋁墊。The manufacturing method of claim 15, wherein the electrical contact is a bump metal or an aluminum pad. 如申請專利範圍第13項所述之製造方法,其中該第二電阻層更定義一第三接點,該製造方法更包括:形成一種子層於該第三接點上;以及形成一電性觸點於該種子層上。The manufacturing method of claim 13, wherein the second resistance layer further defines a third contact, the manufacturing method further comprising: forming a sub-layer on the third contact; and forming an electrical The contacts are on the seed layer.
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Publication number Priority date Publication date Assignee Title
US7106598B2 (en) * 2002-08-21 2006-09-12 Potomac Photonics, Inc. Passive component assembly for multi-layer modular electrical circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7106598B2 (en) * 2002-08-21 2006-09-12 Potomac Photonics, Inc. Passive component assembly for multi-layer modular electrical circuit

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