CN101937748B - Resistor module and manufacture method thereof - Google Patents
Resistor module and manufacture method thereof Download PDFInfo
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- CN101937748B CN101937748B CN 201010240882 CN201010240882A CN101937748B CN 101937748 B CN101937748 B CN 101937748B CN 201010240882 CN201010240882 CN 201010240882 CN 201010240882 A CN201010240882 A CN 201010240882A CN 101937748 B CN101937748 B CN 101937748B
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Abstract
The invention relates to a resistor module and a manufacture method thereof. The resistor module comprises a substrate and a plurality of resistor structures, wherein each resistor structure is formed on the substrate and comprises a first resistance layer, a dielectric layer and a second resistance layer; the first resistance layers are formed on the substrate, and the dielectric layers are formed on the upper surfaces of the first resistance layers; and the second resistance layers are formed on the dielectric layers.
Description
Technical field
The invention relates to a kind of resistor blocks and manufacture method thereof, and particularly relevant for a kind of resistor blocks and manufacture method thereof with sandwich construction.
Background technology
After traditional resistor assembly completes individually again many be individually fixed on the substrate.Yet the volume of traditional resistor device is larger, when the quantity of the required resistor assembly of substrate the more the time, needs the larger area substrate, causes the oversize of final products.And the traditional resistor assembly must insert or be assembled in the substrate in many ground, quite consuming time and consumption cost.
Summary of the invention
The present invention is relevant for a kind of resistor blocks and manufacture method thereof, and resistor blocks has the multilayer resistive layer, and a plurality of resistor assemblies can be provided simultaneously.In addition, by the design of multilayer resistive layer, can increase the electrical path length of resistance, to increase resistance value.
According to an aspect of the present invention, a kind of resistor blocks is proposed.Resistor blocks comprises a substrate and several electric resistance structures.Each electric resistance structure is formed on the substrate and comprises one first resistive layer, a dielectric layer and one second resistive layer.The first resistive layer is formed on the substrate.Dielectric layer is formed on the upper surface of the first resistive layer.The second resistive layer forms on the dielectric layer.
A kind of manufacture method of resistor blocks is proposed according to a further aspect in the invention.Manufacture method may further comprise the steps.One substrate is provided; Form one first resistive layer on substrate, the first resistive layer defines one first contact and one second contact; Form the upper surface that a dielectric layer covers the first resistive layer, dielectric layer has one first perforate and one second perforate, and the first contact is exposed in the first perforate and the second contact is exposed in the second perforate; And, forming one second resistive layer on dielectric layer, the second resistive layer is electrically connected at the first contact by the first perforate.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 illustrates the top view according to the resistor blocks of first embodiment of the invention.
Fig. 2 illustrates the cutaway view of direction 2-2 ' among Fig. 1.
Fig. 3 illustrates the manufacturing flow chart according to the resistor blocks of first embodiment of the invention.
Fig. 4 A to 4D illustrates the manufacturing schematic diagram of the resistor blocks of Fig. 1.
Fig. 5 A illustrates the top view according to the resistor blocks of second embodiment of the invention.
Fig. 5 B illustrates the cutaway view of direction 5B-5B ' among Fig. 5 A.
Fig. 6 illustrates the cutaway view according to the resistor blocks of third embodiment of the invention.
Fig. 7 illustrates the cutaway view according to the resistor blocks of one embodiment of the invention.
Fig. 8 illustrates the manufacturing schematic diagram of the resistor blocks of Fig. 6.
Fig. 9 illustrates the cutaway view according to the resistor blocks of another embodiment of the present invention.
Figure 10 illustrates the cutaway view according to the resistor blocks of fourth embodiment of the invention.
Figure 11 illustrates the manufacturing flow chart according to the resistor blocks of fourth embodiment of the invention.
Figure 12 A to 12D illustrates the manufacturing schematic diagram of the resistor blocks of Figure 10.
Figure 13 illustrates the cutaway view according to the resistor blocks of other embodiment of the present invention.
The primary clustering symbol description
100,200,300,400,500,600,700: resistor blocks
102: substrate
104,104 ', 204,304,604: electric resistance structure
106,106 ', 206,306,606: the first resistive layers
108,108 ', 208,308,608: the second resistive layers
110,210,310,610: the first dielectric layers
112,212,312, perforate in 612: the first
114,214,314, perforate in 614: the second
116,216,316,616: the first contacts
118,218,318,618: the second contacts
120,220,320,620: the three contacts
122,124,126,150,224,226,326,350,624,626,650: upper surface
128,228,628: the second dielectric layers
130,230, three perforates in 630: the
132,232, four perforates in 632: the
134,234,334,434,534,634: the first electrical contact
136,236,336,536,636: the second electrical contact
238,338,638: the four contacts
208a: the first sub-resistive layer
208b: the second sub-resistive layer
308a: the 3rd sub-resistive layer
308b1: the 4th sub-resistive layer
308b2: the 5th sub-resistive layer
344,444,544,644: the three electrical contact
346,546,646: the four electrical contact
448: bonding wire
552,752: Seed Layer
754: the first bump metal
756: the second bump metal
758: the three bump metal
760: the four bump metal
108a a: part
R: resistor blocks definition
S102-S112, S602-614: step
W: width
Embodiment
The first embodiment
Please refer to Fig. 1, it illustrates the top view according to the resistor blocks of first embodiment of the invention.Resistor blocks 100 comprises substrate 102 and several electric resistance structures 104.Substrate 102 for example is wafer (wafer), silica substrate or contains plastics or the semiconductor substrate of resin composition.Electric resistance structure 104 is formed on the substrate 102.
Please refer to Fig. 2, it illustrates the cutaway view of direction 2-2 ' among Fig. 1.Electric resistance structure 104 comprises the first resistive layer 106, the second resistive layer 108, the first dielectric layer 110, the second dielectric layer 128, the first electrical contact (electricalcontact) 134 and the second electrical contact 136.Wherein, the first resistive layer 106 is formed on the substrate 102, the first dielectric layer 110 is formed on the upper surface 124 of the first resistive layer 106, after making the second resistive layer 108 be formed on the upper surface 150 of the first dielectric layer 110, the first resistive layer 106 and the second resistive layer 108 consist of the double-decker that overlaps up and down.
In the present embodiment, the first resistive layer 106 and the second resistive layer 108 are electrically connected.Compared to traditional individual layer electric resistance structure, the double-decker that the electric resistance structure 104 of present embodiment consists of via the first resistive layer 106 and the second resistive layer 108 increases the length of resistive layer, significantly improves the resistance value of electric resistance structure 104.The number of plies of resistive layer of the present invention is not limited to bilayer, and in other enforcement aspect, the number of plies of the resistive layer of resistor blocks also can be above two layers.
As shown in Figures 1 and 2, whole the second resistive layer 108 overlaps across the first dielectric layer 110 and the first resistive layer 106, makes the laying scope of electric resistance structure 104 less, can save the area of substrate 102, and so this is non-in order to limit the present invention.In an enforcement aspect, as shown in Figure 1, in the second resistive layer 108 ' of electric resistance structure 104 ' only a part be overlapped in the first resistive layer 106 ' across the first dielectric layer 110 (the first dielectric layer 110 is not illustrated in Fig. 1).
Please continue with reference to Fig. 1, although the laying scope of electric resistance structure 104 ' is large than electric resistance structure 104, the width W of right the second resistive layer 108 ' is larger, and the resistance value of electric resistance structure 104 ' is reduced.Say further, by the length of resistive layer and the design of width, can design different resistance values.Generally speaking, the length of resistive layer is longer, and resistance value is larger, and the width of resistive layer is wider, and resistance value is less.
In addition, as shown in Figure 1, the scope that several second resistive layers 108 lay out contains the whole upper surface 122 that covers substrate 102 haply, can reduce impact and the interference of electromagnetic interference (electromagnetic interference, EMI).
As shown in Figure 2, the second resistive layer 108 is positioned at different vertical height positions from the first resistive layer 106, and namely the second resistive layer 108 is toward the thickness direction infiltration and development of substrate 102.Thus, under limited substrate area, can form toward the thickness direction of substrate 102 electric resistance structure of a greater number.Approximately between 28 to 32, so this is non-in order to limit the present invention for the quantity of the electric resistance structure 104 of resistor blocks 100, and the quantity of electric resistance structure 104 can be above 32 or less than 28.
The first dielectric layer 110 covers the upper surface 124 of the first resistive layer 106 and has the first perforate 112 and the second perforate 114, upper surface 124 definition the first contact 116 and second contacts 118 of the first resistive layer 106, the first contact 116 is exposed in the first perforate 112, and the second contact 118 is exposed in the second perforate 114.
A part of 108a of upper surface 126 definition the 3rd contact 120, the second resistive layers 108 of the second resistive layer 108 is formed in the first perforate 112 and is electrically connected at the first contact 116, makes the second resistive layer 108 be electrically connected at the first resistive layer 106.This part 108a of the second resistive layer 108 is haply perpendicular to the first resistive layer 106.
The first contact 116, the second contact 118 and the 3rd contact 120 are defined in the lip-deep electric contact region (region) of resistive layer, and bonding wire, electrical contact, connection pad, bump metal, surface-treated layer (surface finish) or other electrical structure can be formed in this electric connection district.
The electrical path length that determining positions the second contact 118 to the 3rd contacts of the first contact 116, the second contact 118 and the 3rd contact 120 are 120 can be designed different resistance values by this.The position of the first contact 116 of present embodiment, the second contact 118 and the 3rd contact 120 is decided by the resistive arrangement value of reality, not limited by the invention process.
The second contact 118 and the 3rd contact 120 can be used as the positive and negative electrode of the structure that the first resistive layer 106 and the second resistive layer 108 consist of.The second contact 118 and the 3rd contact 120 can be electrically connected at an external circuit by bonding wire (solder wire), for example are the control modules of contact panel.
Although the position of the 3rd contact 120 is overlapped in the first resistive layer 106, so this is non-in order to limit the present invention, and the position of the 3rd contact 120 also can not be overlapped in the first resistive layer 106.For instance, in other enforcement aspect, the part of the second resistive layer 108 also can not be overlapped in the first resistive layer 106, and the 3rd contact 120 is defined on this part of the second resistive layer 108, and the position of the 3rd contact 120 like this just is not overlapped in the first resistive layer 106.
The second dielectric layer 128 covers the second resistive layer 108 and has the 3rd perforate 130 and the 4th perforate 132.The second perforate 114 is exposed in the 4th perforate 132 and the 3rd contact 120 is exposed in 118, the three perforates 130 of the second contact.
The first electrical contact 134 be formed in the 3rd perforate 130 and on the 3rd contact 120 being electrically connected at the second resistive layer 108, and in order to the external circuit electrical contact.The second electrical contact 136 is formed in the second perforate 114, in the 4th perforate 132 and on the second contact 118 being electrically connected at the first resistive layer 106, and in order to the external circuit electrical contact.
The first electrical contact 134 and the second electrical contact 136 for example are aluminium pad (pad), and it can provide outside the better electric connection quality, also can protect the second contact 118 and the 3rd contact 120, avoids it to be subject to the destruction of environment.
Although the first electrical contact 134 and the second electrical contact 136 illustrate that as an example of aluminium pad (pad) example so this is non-in order to limit the present invention.In an enforcement aspect, the first electrical contact 134 and the second electrical contact 136 also can be bump metal (Under-Bump Metallization, UBM).
Below with the manufacture method of the resistor blocks of Fig. 3 and Fig. 4 A to the 4D key diagram 1 of arranging in pairs or groups.Fig. 3 illustrates the manufacturing flow chart according to the resistor blocks of first embodiment of the invention, and Fig. 4 A to 4D illustrates the manufacturing schematic diagram of the resistor blocks of Fig. 1.
In step S 102, provide the substrate 102 shown in Fig. 4 A.Substrate 102 definition have several (Fig. 4 A only shows single) resistor blocks definitions R.Be formed in those resistor blocks definitions R the formed structural correspondence of subsequent step.In cutting step, carry out cutting action along the scope of resistor blocks definition R, can cut out a plurality of resistor blocks 100.Say that further the manufacture method of the resistor blocks of present embodiment can once be made several resistor blocks, promote output, so this is non-in order to limit the present invention.In an enforcement aspect, substrate 102 can only define single resistor blocks definition R.
Then, in step S104, shown in Fig. 4 A, form several first resistive layers 106 on the upper surface 122 of substrate 102, and in upper surface 124 definition the first contact 116 and second contacts 118 of the first resistive layer 106.
In this step S104, can use sputter (sputter) mode and form a resistance material on the upper surface 122 of substrate 102.And then use this resistance material of patterning techniques patterning to form those the first resistive layers 106.Wherein, this resistance material is such as being the high resistance materials such as tantalum nitride (TaN), PbTiO3, ruthenic oxide (RuO2), nickel phosphide (NiP), chromaking nickel (NiCr) and NCAlSi.
Above-mentioned patterning techniques for example is lithography process (photolithography), chemical etching (chemicaletching), plasma etching (plasma etching), laser drill (laser drilling), machine drilling (mechanicaldrilling) or laser cutting.
Then, in step S106, shown in Fig. 4 B, form the upper surface 124 that the first dielectric layer 110 covers the first resistive layer 106.The first dielectric layer 110 has the first perforate 112 and the first contact 116 is exposed in the second perforate 114, the first perforates 112, and the second contact 118 is exposed in the second perforate 114.
Be clear expression electric resistance structure, Fig. 4 B to 4D only shows single electric resistance structure.
In this step S106, can use a kind of dielectric material that forms of several coating techniques, dielectric material for example is photoresist.Those coating techniques for example are printing (printing), spin coating (spinning) or spraying (spraying).Afterwards, use above-mentioned this dielectric material of patterning techniques patterning to form the first dielectric layer 110 shown in Fig. 4 B.
Then, in step S108, shown in Fig. 4 C, form the second resistive layer 108 on the first dielectric layer 110, upper surface 126 definition the 3rd contact 120 of the second resistive layer 108.The second resistive layer 108 is electrically connected at the first contact 116 of the first resistive layer 106 by the first perforate 112.
Then, in step S110, shown in Fig. 4 D, form the second dielectric layer 128 and cover the second resistive layer 108.The second dielectric layer 128 has the 3rd perforate 130 and the second perforate 114 and the second contact 118 are exposed in the 4th perforate 132, the four perforates 132, and the 3rd contact 120 is exposed in the 3rd perforate 130.Form the method for the second dielectric layer 128 similar in appearance to the method that forms the first dielectric layer 110, do not repeat them here.
Then, in step S112, application examples is the mode of sputter in this way, form respectively as shown in Figure 2 the first electrical contact 134 and the second electrical contact 136 on the 3rd contact 120 and the second contact 118.
After the step S112, the scope of the resistor blocks definition R of corresponding each resistor blocks 100 is cut the first dielectric layer 110, the second dielectric layer 128 and substrate 102, to form several resistor blocks 100 as shown in Figure 1.
The second embodiment
Please refer to Fig. 5 A and 5B, Fig. 5 A illustrates the top view according to the resistor blocks of second embodiment of the invention, and Fig. 5 B illustrates the cutaway view of direction 5B-5B ' among Fig. 5 A.Continue to use same numeral with the first embodiment something in common among the second embodiment, do not repeat them here.Resistor blocks 100 differences of the resistor blocks 200 of the second embodiment and the first embodiment are that the second resistive layer 208 of electric resistance structure 204 has the 4th contact 238 in the resistor blocks 200, and it can be used as the plus or minus utmost point of the second resistive layer 208.
Shown in Fig. 5 A, resistor blocks 200 comprises substrate 102 and several electric resistance structures 204.Shown in Fig. 5 B, electric resistance structure 204 is formed on the substrate 102.Electric resistance structure 204 comprises the first resistive layer 206, the second resistive layer 208, the first dielectric layer 210, the second dielectric layer 228, the first electrical contact 234 and the second electrical contact 236.The first resistive layer 206 is formed on the substrate 102.The first dielectric layer 210 is formed on the upper surface 224 of the first resistive layer 206.
The second resistive layer 208 comprises the first sub-resistive layer 208a and the second sub-resistive layer 208b, and the first sub-resistive layer 208a and the second sub-resistive layer 208b spatially are isolated from each other.The first sub-resistive layer 208a is electrically connected at the first contact 216 by the first perforate 212 and the second sub-resistive layer 208b is electrically connected at the second contact 218 by the second perforate 214, makes the first sub-resistive layer 208a be electrically connected at the second sub-resistive layer 208b.
The part of the first sub-resistive layer 208a is formed in the first perforate 212 and with the first resistive layer 206 and overlaps up and down, and remainder and the first sub-resistive layer 208a stagger and do not overlap, and the second sub-resistive layer 208b also together.
By above-mentioned the first embodiment and the second embodiment as can be known, trend and the positive and negative electrode position configuration of the first resistive layer 206 and the second resistive layer 208 have multiple variation, and the enforcement aspect of multiple electrical path length and resistance value can be provided.
The second dielectric layer 228 has the 3rd perforate 230 and the 4th perforate 232, the three perforates 230 and the 4th perforate 232 and exposes respectively the 3rd contact 220 and the 4th contact 238.The first electrical contact 234 and the second electrical contact 236 be formed at respectively on the 3rd contact 220 and the 4th contact 238 with the external circuit electrical contact.The first electrical contact 234 and the second electrical contact 236 can be aluminium pad or bump metal, and the first electrical contact 234 and second electrical contact 236 of present embodiment explain as an example of the aluminium pad example.
The manufacture method of the resistor blocks 200 of Fig. 5 A no longer repeats to give unnecessary details at this similar in appearance to the manufacture method of the resistor blocks 100 of the first embodiment.
The 3rd embodiment
Please refer to Fig. 6, it illustrates the cutaway view according to the resistor blocks of third embodiment of the invention.Continue to use same numeral with the first embodiment something in common among the 3rd embodiment, do not repeat them here.Resistor blocks 100 differences of the resistor blocks 300 of the 3rd embodiment and the first embodiment are that the first resistive layer 306 of resistor blocks 300 and the second resistive layer 308 spatially reach electrically and be isolated from each other.
Resistor blocks 300 comprises substrate 102 and several electric resistance structures 304 (Fig. 6 only illustrates single electric resistance structure 304).Electric resistance structure 304 is formed on the substrate 102.Electric resistance structure 304 comprises the first resistive layer 306, the second resistive layer 308, the first dielectric layer 310, the second dielectric layer 328, the first electrical contact 334, the second electrical contact 336, the 3rd electrical contact 344 and the 4th electrical contact 346.
The first resistive layer 306 is formed on the substrate 102 and defines the first contact 316 and the second contact 318, the first dielectric layer 310 is formed on the first resistive layer 306, and the second resistive layer 308 is formed on the first dielectric layer 310 and defines the 3rd contact 320 and the 4th contact 338.The 3rd contact 320 of the second resistive layer 308 and the 4th contact 338 and the first resistive layer 306 electrical isolation.Say that further electric resistance structure 304 has two resistive layers of electrical separation, respectively the first resistive layer 306 and the second resistive layer 308.Wherein, the first contact 316 and the second contact 318 can be used as the positive and negative electrode of the first resistive layer 306, and the 3rd contact 320 and the 4th contact 338 can be used as the positive and negative electrode of the second resistive layer 308.
In addition, please refer to Fig. 7, it illustrates the cutaway view according to the resistor blocks of one embodiment of the invention.The first electrical contact 434 of resistor blocks 400 can be electrically connected at the 3rd electrical contact 444 by bonding wire 448.Thus, the first resistive layer 306 is electrically connected at the second resistive layer 308, the first resistive layer 306 and the second resistive layer 308 are electrically connected and become single resistance.Compared to the first resistive layer 306 and the second resistive layer 308 that separate, by the single resistance that the first resistive layer 306 and the second resistive layer 308 connect into, its electrical path increases, resistance value increases.If wish to get conversely speaking, the less electric resistance structure of resistance value, can according to the resistor blocks of Fig. 6, in electric resistance structure, form the resistive layer that multilayer is electrically separated.
Below with the manufacture method of the resistor blocks of Fig. 3 and Fig. 8 key diagram 6 of arranging in pairs or groups.Fig. 8 illustrates the manufacturing schematic diagram of the resistor blocks of Fig. 6.Make the step S102 to S106 of resistor blocks 300 similar in appearance to the step S102 and the S106 that make resistor blocks 100, be not repeated, below begin explanation from step S108.
In step S108, as shown in Figure 8, form the second resistive layer 308 on the first dielectric layer 310.The second resistive layer 308 comprises the 3rd sub-resistive layer 308a, the 4th sub-resistive layer 308b1 and the 5th sub-resistive layer 308b2.Upper surface 326 definition the 3rd contact 320 and the 4th contacts 338 of the 3rd sub-resistive layer 308a.
The 4th sub-resistive layer 308b1 is formed at the first perforate 312 interior reaching on the first contact 316 of the first dielectric layer 310.The 5th sub-resistive layer 308b2 is formed at the second perforate 314 interior reaching on the second contact 318 of the first dielectric layer 310, and the 4th sub-resistive layer 308b1 and the 5th sub-resistive layer 308b2 are haply perpendicular to the first resistive layer 306.
In this step S108, can use the sputter technology and form above-mentioned resistance material on the upper surface 350 of the first dielectric layer 310.And then use above-mentioned this resistance material of patterning techniques patterning, the 3rd sub-resistive layer 308a, the 4th sub-resistive layer 308b1 and the 5th sub-resistive layer 308b2 that are isolated from each other with formation.
Then, in step S110, the second dielectric layer 328 that forms as shown in Figure 6 covers the second resistive layer 308.
Then, in step S112, formation the first electrical contact 334, the second electrical contact 336, the 3rd electrical contact 344 and the 4th electrical contact 346 as shown in Figure 6 is on the first contact 316, the second contact 318, the 3rd contact 320 and the 4th contact 338 respectively.Then, the scope of the resistor blocks definition of corresponding each resistor blocks 300 is cut the first dielectric layer 310, the second dielectric layer 328 and substrate 102, to form several resistor blocks 300 as shown in Figure 6.
In addition, in another embodiment, please be shown in Figure 9, it illustrates the cutaway view according to the resistor blocks of another embodiment of the present invention, and resistor blocks 500 more comprises Seed Layer (seed layer) 552.After step S110, more may further comprise the steps in the manufacture method of resistor blocks 500: form Seed Layer 552 on the first contact 316, the second contact 318, the 3rd contact 320 and the 4th contact 338 with sputter or plating mode; Then, form the first electrical contact 534, the second electrical contact 536, the 3rd electrical contact 544 and the 4th electrical contact 546 on Seed Layer 552 with plating mode, to form resistor blocks 500 as shown in Figure 9.Wherein, the first electrical contact 534, the second electrical contact 536, the 3rd electrical contact 544 and the 4th electrical contact 546 bump metal.
The 4th embodiment
Please refer to Figure 10, it illustrates the cutaway view according to the resistor blocks of fourth embodiment of the invention.Continue to use same numeral with the 3rd embodiment something in common among the 4th embodiment, do not repeat them here.Resistor blocks 300 differences of the resistor blocks 600 of the 4th embodiment and the 3rd embodiment are that the first electrical contact 634 and second electrical contact 636 of resistor blocks 600 are formed on the first resistive layer 606.
Resistor blocks 600 comprises substrate 102 and several electric resistance structures 604 (Figure 10 only shows single electric resistance structure 604).Electric resistance structure 604 is formed on the substrate 102.Electric resistance structure 604 comprises the first resistive layer 606, the second resistive layer 608, the first dielectric layer 610, the second dielectric layer 628, the first electrical contact 634, the second electrical contact 636, the 3rd electrical contact 644 and the 4th electrical contact 646.
The first electrical contact 634 and the second electrical contact 636 connection pads, it is formed on the first resistive layer 606, and the 3rd electrical contact 644 and the 4th electrical contact 646 connection pads, it is formed on the second resistive layer 608.
The second electrical contact 636 of the first electrical contact 634 of the first dielectric layer 610 cover parts and part, the first electrical contact 634 and the second electrical contact 636 are located between the first dielectric layer 610 and the first resistive layer 606, and the first electrical contact 634 and the second electrical contact 636 more firmly are formed on the first resistive layer 606.
Technical characterictic similar in appearance to the first dielectric layer 610, the 4th electrical contact 646 of the 3rd electrical contact 644 of the second dielectric layer 628 cover parts and part, the 3rd electrical contact 644 and the 4th electrical contact 646 are located between the second resistive layer 608 and the second dielectric layer 628, and the 3rd electrical contact 644 and the 4th electrical contact 646 more firmly are formed on the second resistive layer 608.
Below with the manufacturing schematic diagram of the resistor blocks of Figure 11 and Figure 12 A to 12D that arranges in pairs or groups explanation Figure 10.Figure 11 illustrates the manufacturing flow chart according to the resistor blocks of fourth embodiment of the invention, and Figure 12 A to 12D illustrates the manufacturing schematic diagram of the resistor blocks of Figure 10.The step S602 of Figure 11 and S604 no longer repeat to give unnecessary details at this similar in appearance to step S 102 and the S104 of Fig. 3, below begin explanation from step S606.
In step S606, shown in Figure 12 A, form the first electrical contact 634 and the second electrical contact 636 on first contact 616 and the second contact 618 of the first resistive layer 606.The first contact 616 and the second contact 618 are defined on the upper surface 624 of the first resistive layer 606.
Then, in step S608, shown in Figure 12 B, form the first dielectric layer 610 and cover the first electrical contact 634 of the first resistive layer 606, part and the second electrical contact 636 of part.The first dielectric layer 610 has the first perforate 612 and the second perforate 614, and it exposes respectively the first electrical contact 634 and the second electrical contact 636.
Then, in step S610, shown in Figure 12 C, form the second resistive layer 608 on the upper surface 650 of the first dielectric layer 610.Upper surface 626 definition the 3rd contacts 620 of the second resistive layer 608 and the 4th contact 638, the second resistive layers 608 also electrically separate with the first resistive layer 606.
Then, in step S612, shown in Figure 12 D, form the 3rd electrical contact 644 and the 4th electrical contact 646 on the 3rd contact 620 and the 4th contact 638 of the second resistive layer 608.
Then, in step S614, form the 3rd electrical contact 644 of the second dielectric layer 628 cover parts as shown in figure 10, the 4th electrical contact 646 and second resistive layer 608 of part.The second dielectric layer 628 has the 3rd perforate 630 and the 4th perforate 632, and it exposes respectively the 3rd electrical contact 644 and the 4th electrical contact 646.So far, form the resistor blocks 600 of Figure 10.
In addition, in another embodiment, please refer to Figure 13, it illustrates the cutaway view according to the resistor blocks of other embodiment of the present invention.Compared to resistor blocks 600, resistor blocks 700 more comprises Seed Layer 752, the first bump metal 754, the second bump metal 756, the 3rd bump metal 758 and the 4th bump metal 760.Below with Figure 11 the manufacture method of resistor blocks 700 is described.Behind step S612, the manufacture method of resistor blocks 700 more comprises: form Seed Layer 752 on the first electrical contact 634, the second electrical contact 636, the 3rd electrical contact 644 and the 4th electrical contact 646 with sputter or plating mode.Then, form the first bump metal 754, the second bump metal 756, the 3rd bump metal 758 and the 4th bump metal 760 on Seed Layer 752, to form resistor blocks 700 as shown in figure 13.
The disclosed resistor blocks of the above embodiment of the present invention and manufacture method thereof have multinomial feature, and it is as follows to enumerate the part feature description:
(1). the second resistive layer is positioned at different vertical height positions from the first resistive layer, and namely the second resistive layer can be toward the thickness direction infiltration and development of substrate.Thus, under limited substrate area, can form the electric resistance structure of a greater number.
(2). the scope that several first resistive layers and several the second resistive layers are laid to contains the upper surface that covers substrate haply, has to reduce the effect that EMI disturbs.
(3). the first resistive layer can be electrically connected with the second resistive layer or electrically separate, practical application viewable design demand and deciding.If the first resistive layer and the second resistive layer are electrically connected, then can increase the length of electrical path to improve resistance value; If the first resistive layer and the second resistive layer electrically separate, then can increase the number of resistance.
(4). resistor blocks is finished with semiconductor technology, dwindles significantly the volume of final resistor blocks.
In sum, although the present invention discloses as above with preferred embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (17)
1. resistor blocks comprises:
One substrate; And
Several electric resistance structures are formed on this substrate, and respectively this electric resistance structure comprises:
One first resistive layer is formed on this substrate;
One dielectric layer is formed on the upper surface of this first resistive layer; And
One second resistive layer forms on this dielectric layer
Wherein, this dielectric layer has one first perforate and one second perforate, this first resistive layer defines one first contact and one second contact, and this first contact is exposed in this first perforate and this second contact is exposed in this second perforate, and this second resistive layer is electrically connected at this first contact by this first perforate.
2. resistor blocks as claimed in claim 1, wherein this first resistive layer and this second resistive layer are electrically connected.
3. resistor blocks as claimed in claim 1, this second resistive layer comprises one first sub-resistive layer and one second sub-resistive layer, this first sub-resistive layer and this second sub-resistive layer are isolated from each other, and this first sub-resistive layer is electrically connected at this first contact by this first perforate and this second sub-resistive layer is electrically connected at this second contact by this second perforate.
4. resistor blocks as claimed in claim 1, wherein this second resistive layer more defines one the 3rd contact, and respectively this electric resistance structure more comprises:
One electrical contact is formed on the 3rd contact.
5. resistor blocks as claimed in claim 4, wherein this electrical contact is bump metal or aluminium pad.
6. resistor blocks as claimed in claim 4, wherein respectively this electric resistance structure more comprises:
One Seed Layer is formed on this electrical contact; And
One bump metal is formed on this Seed Layer.
7. resistor blocks as claimed in claim 4, wherein respectively this electric resistance structure more comprises:
One Seed Layer is formed between this electrical contact and this second resistive layer.
8. resistor blocks as claimed in claim 1, wherein at least a portion of this second resistive layer is overlapped in this first resistive layer across this dielectric layer.
9. resistor blocks as claimed in claim 1, wherein this second resistive layer more defines one the 3rd contact and one the 4th contact, the 3rd contact and the 4th contact and this first resistive layer electrical isolation.
10. resistor blocks as claimed in claim 9, wherein respectively this electric resistance structure more comprises:
One bonding wire is electrically connected this first contact and the 3rd contact.
11. resistor blocks as claimed in claim 1, wherein the material of this first resistive layer and this second resistive layer is tantalum nitride TaN, PbTiO
3, ruthenic oxide RuO
2, in nickel phosphide (NiP) and the chromaking nickel (NiCr) at least one.
12. the manufacture method of a resistor blocks comprises:
One substrate is provided;
Form one first resistive layer on this substrate, this first resistive layer defines one first contact and one second contact;
Form the upper surface that a dielectric layer covers this first resistive layer, this dielectric layer has one first perforate and one second perforate, and this first contact is exposed in this first perforate and this second contact is exposed in this second perforate; And
Form one second resistive layer on this dielectric layer, this second resistive layer is electrically connected at this first contact by this first perforate.
13. manufacture method as claimed in claim 12, wherein in this step that forms this second resistive layer, this second resistive layer comprises one first sub-resistive layer and one second sub-resistive layer, this first sub-resistive layer and this second sub-resistive layer electrical isolation, and this first sub-resistive layer is electrically connected at this first contact by this first perforate, and this second sub-resistive layer is electrically connected at this second contact by this second perforate.
14. manufacture method as claimed in claim 12, wherein in this step that forms this second resistive layer, this second resistive layer more defines one the 3rd contact, more comprises:
Form an electrical contact on the 3rd contact.
15. manufacture method as claimed in claim 14 more comprises:
Form a Seed Layer on this electrical contact; And
Form a bump metal on this Seed Layer.
16. manufacture method as claimed in claim 14, wherein this electrical contact is bump metal or aluminium pad.
17. manufacture method as claimed in claim 12, wherein this second resistive layer more defines one the 3rd contact, and this manufacture method more comprises:
Form a Seed Layer on the 3rd contact; And
Form an electrical contact on this Seed Layer.
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| CN 201010240882 CN101937748B (en) | 2010-07-23 | 2010-07-23 | Resistor module and manufacture method thereof |
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| CN 201010240882 CN101937748B (en) | 2010-07-23 | 2010-07-23 | Resistor module and manufacture method thereof |
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| CN101937748B true CN101937748B (en) | 2013-03-20 |
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| CN110364318B (en) * | 2018-03-26 | 2021-08-17 | 国巨电子（中国）有限公司 | High-frequency resistor and method for manufacturing high-frequency resistor |
| CN112652619B (en) * | 2020-12-22 | 2022-08-09 | 长江存储科技有限责任公司 | Gasket and manufacturing method thereof, and packaging structure and manufacturing method thereof |
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| US6194990B1 (en) * | 1999-03-16 | 2001-02-27 | Motorola, Inc. | Printed circuit board with a multilayer integral thin-film metal resistor and method therefor |
| US6212078B1 (en) * | 1999-10-27 | 2001-04-03 | Microcoating Technologies | Nanolaminated thin film circuitry materials |
| CN200983293Y (en) * | 2006-11-02 | 2007-11-28 | 吴维柏 | Discharge resistor special for power capacitor |
| CN101221908B (en) * | 2008-01-29 | 2010-10-13 | 日月光半导体制造股份有限公司 | Substrate technique and structure with projection |
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