KR100800934B1 - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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KR100800934B1
KR100800934B1 KR1020060125558A KR20060125558A KR100800934B1 KR 100800934 B1 KR100800934 B1 KR 100800934B1 KR 1020060125558 A KR1020060125558 A KR 1020060125558A KR 20060125558 A KR20060125558 A KR 20060125558A KR 100800934 B1 KR100800934 B1 KR 100800934B1
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metal
semiconductor device
substrate
via holes
manufacturing
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KR1020060125558A
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Korean (ko)
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곽성호
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

A method for fabricating a semiconductor device is provided to reduce loss of an inductor by bonding an additionally formed inductor to a substrate in which various kinds of transistors are formed. First and second insulation layers(101,102) with different etch selectivity are sequentially formed on a semiconductor substrate. The second insulation layer is selectively removed to form a first via hole with a predetermined interval. A third insulation layer(105) is formed on the resultant structure. The third insulation layer is selectively removed to form a plurality of second via holes whose part corresponds to the first via hole. A metal plug(108) is formed in the first and the second via holes. The semiconductor substrate is eliminated by a CMP process. Various kinds of transistors(109) and a metal interconnection(110) are formed in a lower substrate(200). Part of the metal plug comes in contact with the metal interconnection.

Description

반도체 소자 및 그 제조방법{SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR}Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR}

도 1은 일반적인 인덕터의 평면 구성을 나타낸 예시도,1 is an exemplary view showing a planar configuration of a general inductor;

도 2는 일반적인 인덕터의 단면 구성을 나타낸 예시도,2 is an exemplary view showing a cross-sectional configuration of a general inductor;

도 3은 본 발명에 의한 반도체 소자의 인덕터 단면구성을 나타낸 평면도,3 is a plan view showing a cross-sectional structure of the inductor of the semiconductor device according to the present invention;

도 4는 본 발명에 의한 반도체 소자를 나타낸 단면도,4 is a cross-sectional view showing a semiconductor device according to the present invention;

도 5a 내지 도 5h는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정 단면도,5A to 5H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention;

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 기판 101 : 제 1 절연막100 semiconductor substrate 101 first insulating film

102 : 제 2 절연막 103 : 제 1 감광막102 second insulating film 103 first photosensitive film

104 : 제 1 비아홀 105 : 제 3 절연막104: first via hole 105: third insulating film

106 : 제 2 감광막 107 : 제 2 비아홀106: second photosensitive film 107: second via hole

108 : 금속 플러그 109 : 트랜지스터108: metal plug 109: transistor

110 : 금속배선 200 : 하부기판110: metal wiring 200: lower substrate

본 발명은 반도체 소자 및 그 제조방법에 관한 것으로, 더욱 상세하게는 인덕터의 손실을 줄이도록 한 반도체 소자 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same to reduce the loss of the inductor.

일반적으로, 반도체 소자 중에서 주파수(Radio Frequency : RF) 소자로는 트랜지스터, 인덕터, 커패시터, 저항 등이 사용되는데, 특히 인덕터는 주파수 칩을 구성하는데 필수적으로 사용되지만, 단일 소자로는 주파수 칩의 면적을 가장 많이 차지하며, 주변의 재질, 구조 및 내부 물질에 따른 기생 커패시턴스 및 저항 성분에 때문에 고주파 특성에 많은 제약을 받는다.Generally, transistors, inductors, capacitors, and resistors are used as frequency (RF) devices among semiconductor devices. In particular, inductors are essentially used to construct a frequency chip. It occupies the most and is highly limited by high frequency characteristics due to parasitic capacitance and resistance components depending on the surrounding materials, structures, and internal materials.

일반적으로 인덕터를 제조하기 위해 평면 회절 기하(Planar Spiral Geometries) 방식을 적용하고 있다.Generally, Planar Spiral Geometries are applied to manufacture inductors.

즉, 기판의 최상부 금속을 2차원 평면상에서 절곡시키면서 구현하는데, 대표적으로 사각형(Rectangular Type), 팔각형(Octagonal Type), 원형(Circular Type) 등이 있으며, 이와 같은 다양한 형상의 인덕터는 모양에 따라 인덕턴스를 다소 향상시킬 수는 있으나, 어느 형상의 인덕터든지 고주파 칩 내에서 큰 면적을 차지한다.In other words, the uppermost metal of the substrate is implemented while bending on a two-dimensional plane, and typically includes a rectangular type, an octagonal type, and a circular type. Can be improved somewhat, but any shape inductor occupies a large area in the high frequency chip.

상기 기판의 최상부 금속은 낮은 저항 및 커패시터 특성을 갖기 때문에 외곽의 나선형 권선(Spiral Turns)으로 사용되고, 중앙부는 하부 금속과 연결되어 구성된다. Since the top metal of the substrate has low resistance and capacitor characteristics, it is used as outer spiral turns, and the center part is connected to the bottom metal.

이와 같은 일반적인 인덕터를 첨부한 도면을 참조하여 보다 상세히 설명하면 다음과 같다.When described in more detail with reference to the accompanying drawings, such a general inductor as follows.

도 1은 일반적인 인덕터의 평면 구성을 나타낸 예시도이고, 도 2는 일반적인 인덕터의 단면 구성을 나타낸 예시도이다.1 is an exemplary view showing a planar configuration of a general inductor, Figure 2 is an exemplary view showing a cross-sectional configuration of a general inductor.

도 1 및 도 2에 도시된 바와 같이, 인덕터는 나선형의 권선 구조를 갖는 제 1 금속 배선(10)과, 상기 제 1 금속 배선(10)의 일단에 형성된 비아 콘택(12) 및 상기 비아 콘택(12)과 연결되는 제 2 금속 배선(14)을 포함하여 구성된다.As shown in FIGS. 1 and 2, the inductor includes a first metal wire 10 having a spiral winding structure, a via contact 12 formed at one end of the first metal wire 10, and the via contact ( And a second metal wire 14 connected with the 12.

상기한 바와 같이 구성되는 인덕터는 입력측으로부터 시변 전류가 흐를 때 플레밍의 법칙에 의해 자기장이 형성된다.In the inductor configured as described above, when the time-varying current flows from the input side, a magnetic field is formed by the law of Fleming.

한편, 종래의 반도체 소자에서 인덕터의 손실을 줄이기 위해 기판과의 거리를 크게 하고 기판 사이에 다른 금속배선을 두지 않고 있기 때문에 제조 방법상 손실을 줄이는데 한계가 있었다.On the other hand, in the conventional semiconductor device, in order to reduce the loss of the inductor, the distance from the substrate is increased and there is a limit in reducing the loss in the manufacturing method because no other metal wiring is provided between the substrates.

본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위한 것으로 웨이퍼(wafer) 접합을 통해 인덕터의 손실을 줄이도록 한 반도체 소자 및 그 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which reduce the loss of an inductor through wafer bonding.

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자는 절연물질에 나선형 형태로 입력단과 출력단을 갖고 형성되는 금속 플러그와, 상기 절연물질과 접합되며 상기 금속 플러그의 일부 콘택되는 금속배선 및 각종 트랜지스터를 구비한 기판을 포함하여 이루어짐을 특징으로 한다.The semiconductor device according to the present invention for achieving the above object is a metal plug formed with an input terminal and an output terminal in a spiral form in the insulating material, a metal wiring bonded to the insulating material and a part of the metal plug and various transistors Characterized by including a substrate having a.

또한, 상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제 조방법은 반도체 기판상에 식각 선택비가 다른 제 1, 제 2 절연막을 차례로 형성하는 단계와, 상기 제 2 절연막을 선택적으로 제거하여 일정한 간격을 갖는 제 1 비아홀을 형성하는 단계와, 상기 제 1 비아홀을 포함한 반도체 기판의 전면에 제 3 절연막을 형성하는 단계와, 상기 제 3 절연막을 선택적으로 제거하여 일부는 상기 제 1 비아홀과 대응되는 다수의 제 2 비아홀을 형성하는 단계와, 상기 제 1, 제 2 비아홀 내부에 금속 플러그를 형성하는 단계와, 상기 반도체 기판을 제거하는 단계와, 하부기판에 각종 트랜지스터 및 금속배선을 형성하는 단계와, 상기 금속 플러그의 일부와 상기 금속배선이 콘택되도록 상기 하부기판과 접합하는 단계를 포함하여 형성함을 특징으로 한다.In addition, the method for manufacturing a semiconductor device according to the present invention for achieving the above object is the step of sequentially forming a first, a second insulating film having a different etching selectivity on the semiconductor substrate, and selectively removing the second insulating film Forming a first via hole having a predetermined interval; forming a third insulating film on the entire surface of the semiconductor substrate including the first via hole; and selectively removing the third insulating film to partially remove the first via hole. Forming a plurality of corresponding second via holes, forming metal plugs in the first and second via holes, removing the semiconductor substrate, and forming various transistors and metal wirings on the lower substrate. And bonding the lower substrate so that a portion of the metal plug and the metal wiring are in contact with each other.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자 및 그 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명에 의한 반도체 소자의 인덕터 단면구성을 나타낸 평면도이고, 도 4는 본 발명에 의한 반도체 소자를 나타낸 단면도이다.3 is a plan view showing a cross-sectional structure of the inductor of the semiconductor device according to the present invention, Figure 4 is a cross-sectional view showing a semiconductor device according to the present invention.

도 3 및 도 4에 도시된 바와 같이, 제 1 절연막(101)상에 상기 제 1 절연막(101)과 식각 선택비가 다른 제 2 절연막(102)이 형성되어 있고, 상기 제 2 절연막(102)상에 제 3 절연막(105)이 형성되어 있다.3 and 4, a second insulating film 102 having an etch selectivity different from that of the first insulating film 101 is formed on the first insulating film 101, and on the second insulating film 102. The third insulating film 105 is formed on the substrate.

그리고 상기 제 1, 제 3 절연막(101,105)내에 다수의 제 1, 제 2 비아홀(104,107)들이 형성되어 있고, 상기 제 1, 제 2 비아홀(104,107)의 내부에 금속 플러그(108)가 형성되어 있다.A plurality of first and second via holes 104 and 107 are formed in the first and third insulating films 101 and 105, and metal plugs 108 are formed in the first and second via holes 104 and 107. .

또한, 상기 금속 플러그(108)와 전기적으로 연결되도록 금속배선(110) 및 각 종 트랜지스터(109)가 형성된 하부기판(200)을 구비하고 있다.In addition, the lower substrate 200 is provided with a metal wiring 110 and various transistors 109 to be electrically connected to the metal plug 108.

여기서, 상기 서로 대응되는 제 1, 제 2 비아홀(104,107) 내부에 형성된 금속 플러그(108)는 나선형 형태를 갖고 일측이 입력단이고 타측은 출력단을 갖는다.Here, the metal plugs 108 formed in the first and second via holes 104 and 107 corresponding to each other have a spiral shape, one side of which has an input end and the other side of which has an output end.

따라서 본 발명의 반도체 소자는 동일한 반도체 기판에 각종 트랜지스터 및 금속배선 그리고 인덕터 등을 형성하지 않고, 인덕터는 별도의 기판에 형성한 후 각종 트랜지스터 및 금속배선들이 형성된 기판과 접합하여 이루어져 있다.Therefore, the semiconductor device of the present invention does not form various transistors, metal wirings and inductors on the same semiconductor substrate, and the inductor is formed on a separate substrate and then bonded to the substrate on which the various transistors and metal wirings are formed.

도 5a 내지 도 5h는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정 단면도이다.5A to 5H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도 5a에 도시된 바와 같이, 반도체 기판(100) 상에 제 1 절연막(101)을 형성하고, 상기 제 1 절연막(101)상에 상기 제 1 절연막(101)과 식각 선택비가 다른 제 2 절연막(102)을 형성한다.As shown in FIG. 5A, a first insulating film 101 is formed on the semiconductor substrate 100, and a second insulating film having an etching selectivity different from that of the first insulating film 101 is formed on the first insulating film 101. 102).

이어, 상기 제 2 절연막(102)상에 제 1 감광막을 도포한 후, 노광 및 현상 공정을 실시하여 상기 제 1 감광막을 선택적으로 패터닝하여 제 1 감광막 패턴(103)을 형성한다.Subsequently, after the first photoresist film is coated on the second insulating film 102, exposure and development processes are performed to selectively pattern the first photoresist film to form a first photoresist film pattern 103.

도 5b에 도시된 바와 같이, 상기 제 1 감광막 패턴(103)을 마스크로 이용하여 상기 노출된 제 2 절연막(102)을 선택적으로 제거하여 일정한 간격을 갖는 제 1 비아홀(104)을 형성한다.As shown in FIG. 5B, the exposed second insulating layer 102 may be selectively removed using the first photoresist pattern 103 as a mask to form first via holes 104 having a predetermined interval.

도 5c에 도시된 바와 같이, 상기 제 1 감광막 패턴(103)을 제거하고, 상기 제 1 비아홀(104)을 포함한 반도체 기판(100)의 전면에 제 3 절연막(105)을 형성한다.As illustrated in FIG. 5C, the first photoresist layer pattern 103 is removed and a third insulating layer 105 is formed on the entire surface of the semiconductor substrate 100 including the first via hole 104.

이어, 상기 제 3 절연막(105)상에 제 2 감광막을 도포한 후, 노광 및 현상 공정을 이용하여 선택적으로 패터닝하여 제 2 감광막 패턴(106)을 형성한다.Subsequently, the second photoresist film is coated on the third insulating film 105, and then selectively patterned to form the second photoresist film pattern 106 by using an exposure and development process.

도 5d에 도시된 바와 같이, 상기 제 2 감광막 패턴(106)을 마스크로 이용하여 노출된 제 3 절연막(105)을 선택적으로 제거함과 동시에 제 1 비아홀(104)에 대응되는 제 1 절연막(101)을 선택적으로 제거하여 제 2 비아홀(107)을 형성한다.As shown in FIG. 5D, the exposed first insulating layer 105 is selectively removed using the second photosensitive layer pattern 106 as a mask, and at the same time, the first insulating layer 101 corresponding to the first via hole 104 is formed. Is selectively removed to form a second via hole 107.

여기서, 상기 제 1 비아홀(104)은 상기 제 2 비아홀(107)의 일부 비아홀들과 대응하게 형성되어 있다.Here, the first via hole 104 is formed to correspond to some via holes of the second via hole 107.

도 5e에 도시된 바와 같이, 상기 제 2 감광막 패턴(106)을 제거하고, 상기 제 2 비아홀(107)을 포함한 반도체 기판(100)의 전면에 금속막을 증착한 후 CMP 등을 실시하여 상기 제 1 비아홀(104) 및 제 2 비아홀(107)의 내부에 금속 플러그(108)를 형성한다.As shown in FIG. 5E, the second photoresist layer pattern 106 is removed, a metal film is deposited on the entire surface of the semiconductor substrate 100 including the second via hole 107, and then CMP is performed to perform the CMP. The metal plug 108 is formed in the via hole 104 and the second via hole 107.

도 5f에 도시된 바와 같이, 상기 반도체 기판(100)을 CMP 등과 같은 공정을 이용하여 제거한다.As shown in FIG. 5F, the semiconductor substrate 100 is removed using a process such as CMP.

도 5g에 도시된 바와 같이, 하부기판(200)에 일반적인 반도체 제조 공정을 통해 각종 트랜지스터(109) 및 금속배선(110)들을 형성한다.As illustrated in FIG. 5G, various transistors 109 and metal wires 110 are formed on the lower substrate 200 through a general semiconductor manufacturing process.

도 5h에 도시된 바와 같이, 상기 하부기판(200)에 형성된 금속배선(110)의 일부가 상기 제 1 비아홀(104) 및 제 2 비아홀(107)의 내부에 형성된 금속 플러그(108)와 전기적으로 연결되도록 접합시킨다.As shown in FIG. 5H, a part of the metal wiring 110 formed in the lower substrate 200 is electrically connected to the metal plug 108 formed in the first via hole 104 and the second via hole 107. Bond to connect.

이상에서 설명한 바와 같은 본 발명에 의한 반도체 소자 및 그 제조방법은 다음과 같은 효과가 있다.As described above, the semiconductor device and the method of manufacturing the same according to the present invention have the following effects.

즉, 별도로 형성된 인더턱와 각종 트랜지스터가 형성된 기판을 접합함으로써 인덕터의 손실을 줄일 수 있다.That is, the loss of the inductor can be reduced by bonding the separately formed inductor and the substrate on which the various transistors are formed.

Claims (3)

절연물질에 나선형 형태로 입력단과 출력단을 갖고 형성되는 금속 플러그와,A metal plug formed of an insulating material having a spiral shape with an input end and an output end, 상기 절연물질과 접합되며 상기 금속 플러그의 일부 콘택되는 금속배선 및 각종 트랜지스터를 구비한 기판A substrate having metal transistors and various transistors bonded to the insulating material and partially contacting the metal plug. 을 포함하는 반도체 소자.Semiconductor device comprising a. 반도체 기판상에 식각 선택비가 다른 제 1, 제 2 절연막을 차례로 형성하는 단계와,Sequentially forming first and second insulating layers having different etching selectivity on the semiconductor substrate, 상기 제 2 절연막을 선택적으로 제거하여 일정한 간격을 갖는 제 1 비아홀을 형성하는 단계와,Selectively removing the second insulating layer to form first via holes having a predetermined interval; 상기 제 1 비아홀을 포함한 반도체 기판의 전면에 제 3 절연막을 형성하는 단계와,Forming a third insulating film on an entire surface of the semiconductor substrate including the first via hole; 상기 제 3 절연막을 선택적으로 제거하여 일부는 상기 제 1 비아홀과 대응되는 다수의 제 2 비아홀을 형성하는 단계와,Selectively removing the third insulating layer to form a plurality of second via holes that partially correspond to the first via holes; 상기 제 1, 제 2 비아홀 내부에 금속 플러그를 형성하는 단계와,Forming metal plugs in the first and second via holes; 상기 반도체 기판을 제거하는 단계와,Removing the semiconductor substrate; 하부기판에 각종 트랜지스터 및 금속배선을 형성하는 단계와,Forming various transistors and metal wirings on the lower substrate; 상기 금속 플러그의 일부와 상기 금속배선이 콘택되도록 상기 하부기판과 접합하는 단계Bonding a portion of the metal plug to the lower substrate such that the metal wire contacts the metal plug; 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 2 항에 있어서,The method of claim 2, 상기 반도체 기판은 화학적기계적 연마로 제거하는The semiconductor substrate is removed by chemical mechanical polishing 반도체 소자의 제조방법.Method of manufacturing a semiconductor device.
KR1020060125558A 2006-12-11 2006-12-11 Semiconductor device and manufacturing method therefor KR100800934B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100225847B1 (en) * 1996-10-23 1999-10-15 윤종용 Semiconductor device having dual spiral inductor
KR20030056611A (en) 2001-12-28 2003-07-04 주식회사 하이닉스반도체 Method of manufacturing an inductor and method of manufacturing a transformer using the inductor
KR100466542B1 (en) * 2002-11-13 2005-01-15 한국전자통신연구원 Stacked Variable Inductor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100225847B1 (en) * 1996-10-23 1999-10-15 윤종용 Semiconductor device having dual spiral inductor
KR20030056611A (en) 2001-12-28 2003-07-04 주식회사 하이닉스반도체 Method of manufacturing an inductor and method of manufacturing a transformer using the inductor
KR100466542B1 (en) * 2002-11-13 2005-01-15 한국전자통신연구원 Stacked Variable Inductor

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