TWI463848B - Receiver and integrated am-fm/iq demodulators for gigabit-rate data detection - Google Patents

Description

Receiver and integrated AM-FM/IQ demodulator for Gigabit data detection

The present invention relates generally to data transmission over a wireless radio link, and more particularly to a detector and receiver for providing fast data transmission over a radio link.

Gigabit rate data transmission has been achieved using ASK modulation in the 60 GHz industrial, scientific, medical (ISM) frequency band by a transceiver module consisting of several GaAs integrated circuits (ICs) mounted on a ceramic substrate. . An example of this prior art can be found in the publication "Wireless 1.25 Gb/s Transceiver Module at 60-GHz Band" by K. Ohata et al. One of the goals of the present invention is to provide a single IC receiver or transceiver in a less expensive processing technique that supports a multi-modulation format including ASK modulation.

Product detectors are well known in the literature on detecting ASK or AM signals. Examples of such detectors in the prior art include Solid-State Radio Engineering from Krauss, Bostian, and Raab, and a summary from Radio-Frequency Electronics from Hagen. This disclosure describes an improved product detector that is capable of operating at a gigabit data rate and has a better linearity for millivolt-level IF input signals with high input impedance to avoid detuning its connections. To the IF input circuit, and it is easy to be powered down so that the IF input circuit is not loaded or power is consumed when the receiver is used in other modulation modes.

This disclosure relates to the goal of providing a gigabit rate data transmission over a radio link using a carrier frequency in the millimeter wave range (>30 GHz). More specifically, it describes amplitude modulation (ASK) or other amplitude modulation (AM) detection circuitry that can be easily incorporated into an integrated circuit receiver system to enable the receiver to support complex IQ modulation schemes and Simple, non-coherent switching signal or multi-level keying signal.

This disclosure also describes several novel radio architectures that have the ability to handle frequency modulation (FSK) or other frequency modulation (FM) and AM and complex IQ modulation schemes by adding a frequency discriminator network. These radio architectures support these various modulations by effectively sharing the detector hardware components. First, the architecture supporting quadrature down-conversion and ASK/AM is described. Next, the details of the ASK/AM detector circuit are described. The AM-FM detector architecture is described later, and the last description is most commonly used. AM-FM/IQ demodulator system concept and FSK/FM detector circuit details.

In one aspect, the present invention primarily contemplates a receiver including a first stage down conversion mixer, a mixer for use as a detector, an amplifier in the RF input signal path of the mixer, and a signal input at the mixer LO An amplifier in the path in which the amplifier in the mixer RF input signal path provides a low gain, linear path to the mixer RF input, wherein the amplifier in the mixer LO input signal path provides a high gain path to the mixer LO input, and Both amplifiers have matching delays.

In another aspect, the present invention primarily contemplates an integrated radio receiver device comprising: a first stage down conversion mixer, an optional IF amplifier, an IQ down converter, a first stage down conversion mixer or Select the multiplexer capability of the AM detector and I/Q channel down conversion at the output of the IF amplifier and the detected AM package in the baseband amplification link. The IF amplifier can act as an amplifier and filter. The signal is usually band limited for optimal performance before detection, and this band limitation generally occurs at IF.

In a third aspect, the invention primarily contemplates a receiver comprising a first stage down conversion mixer, a double balanced mixer as a detector, an amplifier in the RF input signal path of the mixer, in the mixer The amplifier in the LO input signal path, wherein the amplifier in the mixer RF input signal path provides a low gain, linear path to the mixer RF input, wherein the amplifier in the mixer LO input signal path provides a high input to the mixer LO Gain path, and both amplifiers have matching delays.

In the fourth aspect, the present invention mainly covers an AM-FM detector, which includes a combiner that combines an AM product detector with a delay line FM detector for FM detection on a delay line. The AM product detector hardware is reused in the device, and only the additional discriminator phase shifting network is used to implement the FM detector.

In a fifth aspect, the invention primarily contemplates an integrated radio receiver device including a first stage down conversion mixer, an optional IF amplifier, an IQ down converter, a first stage down conversion mixer or optional An AM detector at the output of the IF amplifier and an FM detector at the output of the first stage down conversion mixer or optional IF amplifier, wherein the device supports more than one type of modulation scheme.

The scope of the present invention is pointed out with reference to the accompanying drawings,

Figure 1 shows a novel radio architecture incorporating an intermediate frequency down-conversion and a valid ASK/AM detector. The ASK/AM detector output is multiplexed by the I channel down conversion output to enable the existing baseband low pass filter and amplifier to be reused to filter and amplify the detected ASK/AM signal. The integrated AM detector increases the application space of the 60 GHz receiver by providing the ability to detect non-coherent on-off keying signals and other amplitude modulation modulation. These non-coherent modulation formats simplify the radio system design by eliminating the need to demodulate received data for carrier phase recovery or other complex fundamental IQ signals. The ASK/AM format is suitable for highly directional wireless data links that are unaffected by interference or reflected signals. On the other hand, complex fundamental frequency IQ signal processing provides the ability to reject interference and reflect signals, which may be required on omnidirectional wireless data links. Therefore, a receiver capable of detecting two modulation modes has a wide range of applications.

Figures 2 and 3 show a product detector that can be used as the ASK detector in Figure 1, as described in the prior art. Figure 2 is a schematic diagram showing the modulated input signal (12) applied to the two inputs of the mixer (13). Without specifying the implementation details of the mixer, it is impossible to know the transmission function of this configuration, but if the mixer has equal conversion gain for the signals transmitted through the two inputs, the output signal (14) is the square of the input signal. An approximation of one of the required absolute value functions.

Many actual mixer circuits do not have equal conversion gain for signals passing through the two inputs, but require relatively large amplitude signals to pass through an input (LO inputs of Figures 2-4) and provide a relatively high conversion. The gain and a linear response characteristic are transmitted through the other input (RF input of Figure 2-4). Figure 3 shows a more realistic product detector that uses a limiter or limiting amplifier (18) to provide an approximately constant input signal level to the LO input (17) of the mixer. If the LO input of the mixer has a sufficiently large signal level, this circuit provides an approximation that is closer to the desired absolute value function.

Since the circuit of Figure 3 does not provide the ability to time align the mixer RF and LO input signals (16 and 17 respectively), it is unstable at high data rates. If the two input signals of the mixer are not aligned, the output amplitude of the detector is reduced, and the output pulse is widened, thereby reducing the effective bandwidth of the detector. The circuit simulation indicates that it is desirable to align the two signals within 10-20 degrees of the circle with the highest input modulation frequency, which corresponds to 28-56 ps at the 1 GHz modulation frequency. An improved product detector that provides the time alignment capability of the input signal is shown in Figures 4 and 5. The improved product detector also has a high input impedance to avoid detuning the IF input circuit to which it is connected, and it may be susceptible to being powered down so that the IF input circuit is not loaded when the receiver is used in other modulation modes. Or power consumption, all features are beneficial to actually implement the architecture in Figure 1.

Referring to Figure 5, a specific embodiment of the ASK/AM detector includes a double balanced mixer (26) as a detector and an amplifier in the RF and LO input signal paths of the mixer, respectively labeled amplifier 1 ( 27) and amplifier 2 (28). Amplifier 2 (28) provides a relatively high gain path to the mixer's LO-input, while amplifier 1 (27) provides a relatively low gain, linear path to the mixer's RF input. Both amplifiers are designed to have matching delays. This is done by using an amplifier with a similar topology. Resistor R12 (68) reduces the gain and linearizes amplifier 2 (28), which includes Q8-11 (37-40) and R10-14 (66-70), while C5 (optional) (84) helps match the amplifier Delays and bandwidths of 1(27) and 2(28). That is, the negative feedback resistor R12 (68) can increase the bandwidth and reduce the delay of the amplifier 1 (27) due to the negative feedback generated by it, and the inclusion of C5 (84) can increase the delay and reduce the amplifier 1 (27). The bandwidth is matched to amplifier 2 (28) to compensate for R12 (68). In many cases, C5 (84) may be unnecessary and may be sufficient to match the amplifier delay due to topological similarity.

Fig. 4 shows a conventional circuit architecture which has been implemented in Fig. 5, and amplifier 1 (20) of Fig. 4 corresponds to amplifier 1 (27) of Fig. 5, and the like. The detailed circuit of Figure 5 also includes an optional input buffer amplifier (29) to increase the input impedance of the circuit so that it does not load or detune the IF circuit of Figure 1.

The circuit simulation is performed on the entire receiver by an ASK demodulator, a partial block diagram of which is shown in Figure 1. The detailed circuit of the actual simulation includes a low noise amplifier with a gain of 20 dB before the RF input (1) shown in Figure 1. For the 40 dB total gain between the LNA input and the IF amplifier output, the mixer (2) and the IF amplifier (4) each have a gain of 10 dB. The circuit is simulated for an LNA reference signal level of -65 dBm to -35 dBm, which causes the IF signal at the input of the ASK detector to be in the range of 5-500 mV peak. The RF input frequency is 64 GHz and the IF frequency is 9.1 GHz.

The simulation results shown in Figure 6 are for a 1 GHz sinusoidal amplitude modulation of the RF input with a 0.9 modulation index. The lower trace (87) in Figure 6 is the IF waveform (amplitude contrast time), the middle trace (88) is the ASK detector output waveform, and the top trace (89) is low pass filtered and the baseband amplifier The ASK output has been detected after amplification. It can be seen that the circuit of Figure 5 is very close to the absolute value of the input signal, and it regenerates the AM or ASK signal when low pass filtering. The 1 GHz sinusoidal modulation is approximately equal to the 2Gb/s rate switch (2-bit ASK) keying.

The simulation results shown in Figure 7 are for an entire receiver with an integrated product detector using a 4-bit quasi-ASK input at a 2G symbol/s rate, which is equal to a data rate of 4 Gb/s. The lower trace (90) is the RF input waveform (amplitude contrast time) showing the four amplitude levels, the second trace at the bottom (91) is the IF waveform, and the third trace at the bottom (92) is the ASK detector output. The waveform, and the top trace (94) is the demodulated ASK output after amplification and low pass filtering by the baseband amplifier, which exhibits four distinct demodulation levels.

There are a large number of prior art for AM/ASK detectors, as exemplified by the above numerous references. Most of the patented circuits are based on diodes, such as U.S. Patent No. 3,691,465 to McFadyen, U.S. Patent No. 4,000,472 to Eastland, U.S. Patent No. 4,250,457 to Hofmann, U.S. Patent No. 4,320,346 to Healey, Sauer U.S. Patent No. 4, 359, 693, U.S. Patent No. 4,492,926 to Kusakabe. Other detectors use components other than the diodes to achieve the corrections, including U.S. Patent No. 3,673,505 to Limberg, U.S. Patent No. 3,965,435 to Krit, and U.S. Patent No. 4,320,346 to Healey. Among product detectors (i.e., mixers or multiplier-based detectors), include US Patent No. 3,705,355 to Palmer, US Patent No. 3,792,364 to Ananias, and US Patent No. 6,360,000 to Tayloe. A patent using the matched delay circuit shown in Figures 4-5 of the present invention has not been found.

The concept of this disclosure can be extended to also include detecting the FSK/FM signal by adding a discriminator phase shifting network, as shown in FIG. The FSK/FM detector (94) was built using the same components as the earlier ASK/AM detector. The phase shifting network H(f) (98) is designed to have a 90° phase shift at the IF carrier frequency. This circuit is well known in the literature and is given a different name: a delay line FM detector or a quadrature FM demodulator.

Figure 9 shows how this delay line FM detector can be combined with an AM product detector into a radio architecture that demodulates ASK/AM or FSK/FM signals. Referring to Figure 9, the switch Sw1 (104) is closed and the switches Sw2 (105) and Sw3 (106) are turned on to configure the detector as an AM product detector as shown in FIG. Close Sw2 (105) and Sw3 (106) and turn on Sw1 (104) to configure the detector as a delay line FM detector, as shown in Figure 8.

Figure 10 shows a more detailed embodiment of the AM-FM detector architecture including the modified AM product detector described in Figures 4 and 5. In Fig. 10, two amplifiers for aligning the input signals of Fig. 4 (Amp1 (20) and Amp2 (21)) are referred to as "linear amps" (113) (corresponding to Fig. 4). Ampl (20)) and "Limiting Amplifier" (118) (corresponding to Amp2 (21) in Figure 4) are clearly shown here. Similarly, it is possible to implement one of the discriminator phase shift networks H(f) (117) of 9 GHz IF. Referring to Fig. 10, the switch Sw1 (114) is closed and the switches Sw2 (115) and Sw3 (116) are turned on to configure the detector as an AM product detector as shown in FIG. Close Sw2 (115) and Sw3 (116) and turn on Sw1 (114) to configure the detector as a delay line FM detector, as shown in Figure 8.

Figure 11 shows the most common receiver architecture described. It supports three different modulations: complex IQ modulation, ASK/AM and FSK/FM. The architecture provides IQ demodulation by closing switches SwI (124) and SwQ (127) (and other switches are turned on). AM demodulation is provided as SwAM (125) is closed (and other switches are open). FM demodulation is provided by closing SwFM (126) (and other switches are turned on). Simultaneous demodulation of AM and FM is provided by closing SwAM (125) and SwFM (127) (and other switches are turned on), which potentially increases the non-coherent data rate by either factor. Although not explicitly shown, it should be understood that the improved ASK/AM detector of Figure 4 can be used in Figure 11 by providing an amplifier with matching delay in the ASK/AM mixer signal path. For simultaneous AM and FM demodulation, the AM detector should be as unaffected by the frequency as possible to limit the FM leakage to its detected output level, and the FM detector should be as unaffected by the amplitude as possible to leak the AM. Limited to its detection output level.

Figure 12 shows a specific, transistor level embodiment of the FM detector, which is actually part of the receiver architecture of Figure 11. This common type of FM detector is given a different name: a delay line FM detector or a quadrature FM demodulator or an FM limiter-discriminator, and is well known in the literature. The modified circuit uses a three-stage limiting amplifier (137), each of which has a gain that depends on the amplitude. The gain dependent on the amplitude provides a relatively high gain for the low amplitude input signal and a lower gain for the higher amplitude input signal. This gain depending on the amplitude provides a progressively larger limiting characteristic for the higher amplitude input signal, which minimizes the asymmetric second order distortion product present in the output signal while still providing effective for lower amplitude input signals. limit. Any asymmetry or second order distortion of the output signal results in an amplitude dependent DC offset at the output of the limiter which results in poor amplitude modulation signal rejection and a lower signal to noise ratio. Therefore, the improved limiting amplifier maintains a high signal-to-noise ratio in the presence of AM, which is extremely important in systems that use AM and FM simultaneous modulation, as shown in Figure 11.

Figure 13 reveals the details of the limiting amplifier. Each amplifier stage has two pairs of input transistors, a pair of resistor negative feedback (Q1 (139), Q3 (141) and R3 (149)), and another pair of resistors with non-negative feedback (Q2 (140), Q4 ( 142)). The non-negative feedback pair provides a high gain for the smaller input signal until the input signal amplitude reaches a point where the pair of differential input currents saturate. Before the negative feedback pair saturates, the negative feedback pair will provide a lower gain and will accept a larger signal. Therefore, the overall limiting characteristic of the amplifier is gradually increased, providing a lower DC offset and a lesser second-order distortion product at the output.

Figure 14 shows a specific circuit embodiment for the discriminator filter of Figure 12. It is designed to have a 90 degree phase shift at the center frequency of 8.9 GHz and provide a linear phase shift of the input frequency with respect to this center frequency, which ranges up to ±2 GHz. This is the actual differential on the theoretical network shown in Figure 10, a specific embodiment on the wafer.

All patents, patent applications, patent publications, and other publications, which are hereby incorporated by reference herein in its entirety herein in its entirety herein in its entirety,

Although the present invention has been described with reference to the drawings, it is understood that the invention is not limited to the specific embodiments, and may be practiced herein without departing from the scope and spirit of the invention Various other changes and modifications are made by the skilled artisan to the invention.

1. . . RF input

2. . . mixer

4. . . IF amplifier

12. . . Modulated input signal

13. . . mixer

14. . . Output signal

16. . . LO input signal

17. . . LO input signal

18. . . Limiting amplifier

20. . . Amplifier 1

26. . . Double balanced mixer

27. . . Amplifier 1

28. . . Amplifier 2

29. . . Input buffer amplifier

37-40. . . Transistor Q8-Q11

66-70. . . Resistance 10-14

84. . . Capacitor C5

87. . . Lower trace

88. . . Intermediate trace

89. . . Top trace

90. . . Lower trace

91. . . Bottom second trace

92. . . Third trace at the bottom

93. . . Top trace

94. . . FSK/FM detector

98. . . Phase shift network

104. . . Switch Sw1

105. . . Switch Sw2

106. . . Switch Sw3

113. . . Linear amplifier

114. . . Switch Sw1

115. . . Switch Sw2

116. . . Switch Sw3

117. . . Discriminator phase shift network

118. . . Limiting amplifier

124. . . Switch SwI

125. . . Switch SwAM

126. . . Switch SwFM

127. . . Switch SwQ

137. . . Three-stage limiting amplifier

139. . . Transistor Q1

140. . . Transistor Q2

141. . . Transistor Q3

142. . . Transistor Q4

149. . . Resistor R3

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of the overall system of the presently preferred embodiment of the present invention.

Figure 2 shows one of the product detectors found in the prior art.

Figure 3 is another product detector that can be found in the prior art.

Figure 4 is a specific embodiment of a product detector of a presently preferred embodiment of the present invention.

Figure 5 is a circuit embodiment of a product detector of the presently preferred embodiment of the present invention.

Figure 6 is a screenshot of a simulation result of a receiver of a specific embodiment of the present invention.

Figure 7 is a screenshot of a simulation result of a receiver of another embodiment of the present invention.

Figure 8 is a block diagram of the entire system of another presently preferred embodiment of the present invention.

Figure 9 is a specific embodiment of a product detector of another presently preferred embodiment of the present invention.

Figure 10 is a more detailed embodiment of one of the product detectors of Figure 9.

Figure 11 is a block diagram of the entire system of another presently preferred embodiment of the present invention.

Figure 12 is a circuit specific embodiment of a specific embodiment of Figure 11.

Figure 13 is a more detailed diagram of one of the amplifiers of Figure 12.

Figure 14 is a more detailed circuit embodiment of one of the discrimination filters of Figure 12.

1. . . RF input

2. . . First mixer

3. . . First local oscillator

4. . . IF amplifier

5. . . ASK detection

6. . . Multiplexer

7. . . Second local oscillator

8. . . Second mixer

9. . . Baseband filter and amplifier

10. . . Demodulated ASK output or I channel baseband output

11. . . Q channel fundamental frequency output

Claims (17)

A receiver comprising: a first stage down conversion mixer; a double balanced mixer for use as a detector; an amplifier in the RF input signal path of the mixer; and an LO input at the mixer An amplifier in the signal path; wherein the amplifier in the RF input signal path of the mixer provides a low gain, linear path to the RF input of the mixer; wherein the amplifier is in the LO input signal path of the mixer A high gain path is provided to the LO input of the mixer; both amplifiers have matching delays. A receiver comprising: a first stage down conversion mixer; a mixer for detecting the detector; an amplifier in the RF input signal path of the mixer; and an input signal path in the LO of the mixer An amplifier in which the amplifier in the RF input signal path of the mixer provides a low gain, linear path to the RF input of the mixer; wherein the amplifier in the LO input signal path of the mixer is The mixer's LO input provides a high gain path; both amplifiers have matching delays. The receiver of claim 2, wherein the mixer is a double balanced mixer. The receiver of claim 2, wherein the mixer is combined with the I-channel mixer. The receiver of claim 2, wherein the mixer is The Q channel mixer combination. The receiver of claim 3, wherein the mixer is combined with the I-channel mixer. The receiver of claim 3, wherein the mixer is combined with the Q channel mixer. An integrated radio receiver apparatus for receiving complex IQ modulation, ASK/AM modulation, and FSK/FM modulation signals, the radio receiver apparatus comprising: a first stage down conversion mixer (122); an AM a detector, the AM detector is coupled to the output of the first stage down conversion mixer, providing a demodulated ASK/AM output from the received ASK/AM modulation signal; and an FM detector The FM detector is coupled to the output of the first stage down conversion mixer to provide a demodulated FSK/FM output from the received FSK/FM modulation signal; characterized in that the apparatus further comprises a An IQ down converter coupled to the output of the first stage downconverter and providing demodulated I and Q channel outputs from the received complex IQ modulated signal; The output of the detector can be multiplexed into a baseband amplifier and filter by the I channel or the Q channel output. The receiver device of claim 8, wherein the output of the FM detector is multiplexed into a baseband amplifier and filter by the I channel or the Q channel output. The receiver device according to claim 9, wherein the AM detection The detector provides AM demodulation and the FM detector provides FM demodulation to synchronous reception of ASK/AM and FSK/FM signals. The receiver device of claim 8, wherein the baseband amplifier is a three-stage limiting amplifier. The receiver device of claim 11, wherein the baseband amplifier comprises: a first pair of input transistors (Q1, Q3), the first pair of input transistors being connected to corresponding positive and negative differentials Input; a second pair of input transistors (Q2, Q4), the second pair of input transistors being coupled to the corresponding positive and negative differential inputs; wherein the first pair of input transistors are resistively (R3) Negative feedback to provide a low gain, linear path from the differential inputs of the amplifier to the differential output of the amplifier; and the second pair of input transistors are not resistively negatively feedback, such that from the amplifier The differential input provides a high gain path to the differential output of the amplifier. The receiver device of claim 8, further comprising: an identification filter (129) having a phase shift of 90 degrees, the filter being a differential filter and located at the IF frequency of the receiver At the center. A receiver comprising: a first stage down conversion mixer (2); a detector comprising: a second mixer (24, 26); an amplifier (21, 28), the amplifier (21, 28) In the LO input signal path of the second mixer, the amplifier in the LO input signal path of the second mixer provides a high gain path to the LO input of the mixer; wherein the detector further An amplifier (20, 27) is included in the RF input signal path of the second mixer, and the amplifier in the RF input signal path of the second mixer provides a low gain, linearity to the RF input of the mixer The path; and the amplifiers both have matching delays. The receiver of claim 14, wherein the second mixer (24, 26) is a double balanced mixer. The receiver of claim 14 or 15, wherein the second mixer (24, 26) is combined with an output from an I-channel mixer. The receiver of claim 14 or 15, wherein the second mixer (24, 26) is combined with an output from a Q channel mixer.