JPS5765012A - Linear detector - Google Patents

Linear detector

Info

Publication number
JPS5765012A
JPS5765012A JP14027180A JP14027180A JPS5765012A JP S5765012 A JPS5765012 A JP S5765012A JP 14027180 A JP14027180 A JP 14027180A JP 14027180 A JP14027180 A JP 14027180A JP S5765012 A JPS5765012 A JP S5765012A
Authority
JP
Japan
Prior art keywords
signal
terminal
mixer
hybrid
transmitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14027180A
Other languages
Japanese (ja)
Inventor
Tokihiro Mishiro
Kazuichi Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14027180A priority Critical patent/JPS5765012A/en
Publication of JPS5765012A publication Critical patent/JPS5765012A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

PURPOSE:To achieve linear detection with good linearity and temperature stability, by dividing an input signal into two, transmitting them directly or via an amplitude limiter to a double balanced mixer, and transmitting the output via an LPF. CONSTITUTION:A signal to be detected inputted to a terminal 21 is divided into two at a hybrid 22. This split signal is inputted to an AC signal terminal of a double balanced mixer 23. Another signal split at the hybrid 22 is connected to a local signal terminal of the mixer 23 via an amplitude limiter 24. Detected signal outputted at a DC terminal of the mixer 23 is smoothed at an LPF25 and outputted to a terminal 26. Thus, a linear detection with good linearity to the input amplitude of a wide range and with good temperature stability can be realized.
JP14027180A 1980-10-07 1980-10-07 Linear detector Pending JPS5765012A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14027180A JPS5765012A (en) 1980-10-07 1980-10-07 Linear detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14027180A JPS5765012A (en) 1980-10-07 1980-10-07 Linear detector

Publications (1)

Publication Number Publication Date
JPS5765012A true JPS5765012A (en) 1982-04-20

Family

ID=15264885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14027180A Pending JPS5765012A (en) 1980-10-07 1980-10-07 Linear detector

Country Status (1)

Country Link
JP (1) JPS5765012A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007088127A2 (en) * 2006-01-31 2007-08-09 International Business Machines Corporation Receiver and integrated am-fm/iq demodulators for gigabit-rate data detection

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5131122A (en) * 1974-09-11 1976-03-17 Hitachi Ltd EIZODOKI KENPASOCHI
JPS5668006A (en) * 1979-11-06 1981-06-08 Sony Corp Am synchronous detecting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5131122A (en) * 1974-09-11 1976-03-17 Hitachi Ltd EIZODOKI KENPASOCHI
JPS5668006A (en) * 1979-11-06 1981-06-08 Sony Corp Am synchronous detecting circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007088127A2 (en) * 2006-01-31 2007-08-09 International Business Machines Corporation Receiver and integrated am-fm/iq demodulators for gigabit-rate data detection
WO2007088127A3 (en) * 2006-01-31 2007-09-27 Ibm Receiver and integrated am-fm/iq demodulators for gigabit-rate data detection

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