TWI462161B - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- TWI462161B TWI462161B TW100147697A TW100147697A TWI462161B TW I462161 B TWI462161 B TW I462161B TW 100147697 A TW100147697 A TW 100147697A TW 100147697 A TW100147697 A TW 100147697A TW I462161 B TWI462161 B TW I462161B
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- 239000004065 semiconductor Substances 0.000 title claims description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 10
- 239000002253 acid Substances 0.000 claims description 4
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 239000003054 catalyst Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 206010070834 Sensitisation Diseases 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008313 sensitization Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Description
本發明關於有場電極構造的半導體裝置的製造方法。The present invention relates to a method of fabricating a semiconductor device having a field electrode structure.
在專利文獻1中，揭露了在半導體層的表面的一部分形成絕緣膜，並在半導體層以及絕緣膜的表面上一體地形成金屬層的半導體裝置的製造方法。在該半導體裝置的製造方法中，執行用以使絕緣膜為所希望的形狀的曝光以及顯像處理，以及用於使金屬層為所希望的形狀的曝光以及顯像處理(以後稱為金屬膜用曝光處理)。而且，金屬層中半導體層上的部分發揮作為閘電極的作用，絕緣膜上的部分發揮作為場電極的作用。Patent Document 1 discloses a method of manufacturing a semiconductor device in which an insulating film is formed on a part of a surface of a semiconductor layer, and a metal layer is integrally formed on a surface of the semiconductor layer and the insulating film. In the method of manufacturing a semiconductor device, exposure and development processing for making an insulating film into a desired shape, and exposure and development processing for forming a metal layer into a desired shape (hereinafter referred to as a metal film) are performed. Use exposure processing). Further, a portion of the metal layer on the semiconductor layer functions as a gate electrode, and a portion on the insulating film functions as a field electrode.
[專利文獻][Patent Literature]
[專利文獻1]日本特開2005-093864號公報[Patent Document 1] Japanese Patent Laid-Open Publication No. 2005-093864
[專利文獻2]日本特開2007-005379號公報[Patent Document 2] Japanese Patent Laid-Open Publication No. 2007-005379
[專利文獻3]日本特開平08-148508號公報[Patent Document 3] Japanese Laid-Open Patent Publication No. 08-148508
為了形成場電極，在絕緣膜上形成開口，在該開口以及絕緣膜的表面上形成金屬層。絕緣膜上的金屬層的場電極形成於相對於開口中心特定的位置為佳。可是因為金屬膜用曝光處理的誤差，相對於開口中心的場電極構造的位置有時會有誤差。因此，半導體裝置的特性有良莠不齊的狀況發生。In order to form the field electrode, an opening is formed on the insulating film, and a metal layer is formed on the opening and the surface of the insulating film. The field electrode of the metal layer on the insulating film is preferably formed at a position specific to the center of the opening. However, there is a case in which there is an error in the position of the field electrode structure with respect to the center of the opening due to an error in exposure processing of the metal film. Therefore, the characteristics of the semiconductor device are inconsistent.
本發明，係為了解決如上述般的課題，其目的在於提供半導體裝置的製造方法，其能夠相對於絕緣膜的開口中心沒有誤差地形成場電極構造。The present invention has been made to solve the above problems, and an object of the invention is to provide a method of manufacturing a semiconductor device capable of forming a field electrode structure with no error with respect to an opening center of an insulating film.
本案發明之半導體裝置之製造方法，其特徵在於包括：在半導體層的表面上形成絕緣膜的步驟；在前述絕緣膜的表面上形成有開口的光阻的步驟；使得和該光阻橋接反應的圖案收縮劑附著於光阻，在該光阻的內周形成硬化層的步驟；把上述光阻以及上述硬化層作為遮罩以蝕刻上述絕緣膜的步驟；去除上述硬化層的步驟；在前述半導體層、前述絕緣膜以及前述光阻的表面上形成金屬層的步驟；以及藉由剝離(lift-off)法去除前述光阻以及前述光阻表面的前述金屬層的步驟。A method of manufacturing a semiconductor device according to the present invention, comprising: a step of forming an insulating film on a surface of the semiconductor layer; a step of forming an open photoresist on a surface of the insulating film; and reacting with the photoresist a pattern shrinking agent attached to the photoresist, forming a hardened layer on the inner circumference of the photoresist; a step of etching the insulating film by using the photoresist and the hardened layer as a mask; a step of removing the hardened layer; and the semiconductor a step of forming a metal layer on the surface of the layer, the insulating film, and the photoresist; and removing the photoresist and the metal layer of the photoresist surface by a lift-off method.
依據本發明，不進行金屬膜用曝光處理，就能夠相對於絕緣膜的開口中心沒有誤差地形成場電極構造。According to the present invention, the field electrode structure can be formed without error with respect to the opening center of the insulating film without performing the exposure treatment for the metal film.
第1圖為表示有關本發明的實施的形態1的半導體裝置的製造方法的流程圖。順著第1圖說明有關本發明的實施的形態1的半導體裝置的製造方法。首先，在半導體層的表面上形成絕緣膜(步驟10)。參照第2圖說明步驟10。第2圖是表示在半導體層32的表面上形成絕緣膜34的圖。半導體層32在基板30的表面上形成。基板30用SiC形成，半導體層32是GaN/用AlGaN形成。然後，在半導體層32的表面上用SiN形成絕緣膜34。Fig. 1 is a flowchart showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. A method of manufacturing a semiconductor device according to a first aspect of the present invention will be described with reference to FIG. First, an insulating film is formed on the surface of the semiconductor layer (step 10). Step 10 will be described with reference to FIG. FIG. 2 is a view showing formation of an insulating film 34 on the surface of the semiconductor layer 32. The semiconductor layer 32 is formed on the surface of the substrate 30. The substrate 30 is formed of SiC, and the semiconductor layer 32 is made of GaN/AlGaN. Then, an insulating film 34 is formed of SiN on the surface of the semiconductor layer 32.
接著在絕緣膜34的表面上形成光阻(步驟12)。參照第3圖說明步驟12。第3圖是表示在絕緣膜34的表面上形成光阻36的圖。光阻36包含因為感光而變酸性的材料。A photoresist is then formed on the surface of the insulating film 34 (step 12). Step 12 will be explained with reference to FIG. FIG. 3 is a view showing formation of the photoresist 36 on the surface of the insulating film 34. The photoresist 36 contains a material that becomes acidic due to sensitization.
接著，在光阻36形成開口(步驟14)。參照第4圖說明步驟14。第4圖是表示在光阻形成開口的圖。在步驟14中，對光阻中於本步驟之後應該開口的部分施以曝光、顯像處理，以形成有開口的光阻36a(之後稱之為光阻36a)。雖用顯像處理去除光阻的感光部分，但在光阻36a的內周部殘存有限的酸成分。Next, an opening is formed in the photoresist 36 (step 14). Step 14 will be explained with reference to FIG. Fig. 4 is a view showing an opening formed in a photoresist. In step 14, an exposure and development process is applied to a portion of the photoresist which should be opened after this step to form an open photoresist 36a (hereinafter referred to as a photoresist 36a). Although the photosensitive portion of the photoresist is removed by the development process, a limited acid component remains in the inner peripheral portion of the photoresist 36a.
接著，藉由RELACS(Resolution Enhanced Lithography Asisted by Chemical Shrink)處理形成硬化層(步驟16)。參照第5圖說明步驟16。第5圖是表示藉由RELACS處理形成硬化層38a以及38b的圖。硬化層38a以及38b係藉由將光阻36a的酸成分作為觸媒，讓橋接反應的圖案收縮劑附著在光阻36a而形成。橋接反應係藉由加熱處理而發生。藉由在光阻36a的內周形成硬化層38a以及38b，開口幅(絕緣膜34露出的寬度)僅有比光阻36a的開口寬度收縮硬化層38a以及38b的分量。Next, a hardened layer is formed by RELACS (Resolution Enhanced Lithography Asisted by Chemical Shrink) (step 16). Step 16 is explained with reference to FIG. Fig. 5 is a view showing formation of hardened layers 38a and 38b by RELACS processing. The hardened layers 38a and 38b are formed by adhering the pattern shrinkage agent of the bridge reaction to the photoresist 36a by using the acid component of the photoresist 36a as a catalyst. The bridging reaction occurs by heat treatment. By forming the hardened layers 38a and 38b on the inner circumference of the photoresist 36a, the opening width (the width at which the insulating film 34 is exposed) shrinks only the components of the hardened layers 38a and 38b more than the opening width of the photoresist 36a.
繼之，蝕刻絕緣膜34(步驟18)。參照第6圖說明步驟18。第6圖是表示已蝕刻絕緣膜的圖。係以光阻36a、及硬化層38a以及38b作為遮罩，對絕緣膜進行蝕刻。此蝕刻係以用氟自由基的乾蝕刻、氟酸系濕蝕刻、或將兩者並用實施。藉由此蝕刻形成有開口的絕緣膜34a。Next, the insulating film 34 is etched (step 18). Step 18 is explained with reference to FIG. Fig. 6 is a view showing the etching of the insulating film. The insulating film is etched by using the photoresist 36a and the hardened layers 38a and 38b as masks. This etching is performed by dry etching using a fluorine radical, wet etching by a hydrofluoric acid, or both. An insulating film 34a having an opening is formed by etching therefrom.
繼之，去除硬化層(步驟20)。參照第7圖說明步驟20。第7圖是表示去除硬化層的圖。硬化層係藉由強鹼性藥液去除。藉由將硬化層去除，而使得位於硬化層下的「有開口的絕緣膜34a」的一部分露出於表面。Following this, the hardened layer is removed (step 20). Step 20 will be described with reference to FIG. Fig. 7 is a view showing the removal of the hardened layer. The hardened layer is removed by a strong alkaline solution. A part of the "opening insulating film 34a" located under the hardened layer is exposed on the surface by removing the hardened layer.
接著形成金屬層(步驟22)。參照第8圖說明步驟22。第8圖是表示形成金屬層40的圖。金屬層40形成在半導體層32、有開口的絕緣膜34a以及光阻36a的表面上。A metal layer is then formed (step 22). Step 22 will be explained with reference to FIG. Fig. 8 is a view showing the formation of the metal layer 40. The metal layer 40 is formed on the surface of the semiconductor layer 32, the insulating film 34a having an opening, and the photoresist 36a.
接著，使用剝離法形成具有場電極構造的閘電極(步驟24)。參照第9圖說明步驟24。第9圖是表示用剝離法形成具有場電極構造的閘電極40a的圖。用剝離法去除光阻36a以及其表面的金屬層，在半導體層32和有開口的絕緣膜34a的表面上殘留金屬層。殘留的金屬層變為具有場電極構造的閘電極40a。再者，場電極構造是留在有開口的絕緣膜34a的表面上的金屬層。有關本發明的實施的形態1的半導體裝置的製造方法具有上述的程序。Next, a gate electrode having a field electrode structure is formed using a lift-off method (step 24). Step 24 will be described with reference to FIG. Fig. 9 is a view showing formation of a gate electrode 40a having a field electrode structure by a lift-off method. The photoresist 36a and the metal layer on the surface thereof are removed by a lift-off method, and a metal layer remains on the surface of the semiconductor layer 32 and the open insulating film 34a. The residual metal layer becomes the gate electrode 40a having the field electrode configuration. Further, the field electrode structure is a metal layer remaining on the surface of the insulating film 34a having an opening. A method of manufacturing a semiconductor device according to a first aspect of the present invention has the above-described program.
根據本發明的實施的形態1的半導體裝置的製造方法，在形成硬化層38a以及38b並使開口寬幅收縮的狀態下蝕刻絕緣膜，將硬化層38a以及38b去除使開口寬幅變大的狀態下形成具有場電極構造的閘電極40a。因此不需要金屬膜用曝光處理，能夠相對於絕緣膜的開口中心沒有誤差地形成場電極構造。另外，因為不需要金屬膜用曝光處理，所以能簡化程序。According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, the insulating film is etched in a state where the hardened layers 38a and 38b are formed and the opening is widely contracted, and the hardened layers 38a and 38b are removed to increase the width of the opening. A gate electrode 40a having a field electrode configuration is formed underneath. Therefore, it is not necessary to expose the metal film, and the field electrode structure can be formed without error with respect to the opening center of the insulating film. In addition, since the exposure process of the metal film is not required, the program can be simplified.
第10圖是表示有關本發明的實施的形態1的半導體裝置的製造方法的變形例的圖。如圖所示，可以使絕緣膜為由有開口的絕緣膜34a及SiOx形成的絕緣膜33的積層構造。也可以像這樣將2種以上的膜層積形成絕緣膜。FIG. 10 is a view showing a modification of the method of manufacturing the semiconductor device according to the first embodiment of the present invention. As shown in the figure, the insulating film can have a laminated structure of an insulating film 34a having an opening and an insulating film 33 made of SiOx. Alternatively, two or more types of films may be laminated to form an insulating film.
第11圖是表示有關本發明的實施的形態2的半導體裝置的製造方法的流程圖。在此流程圖中，標示以和第1圖相同的符號的步驟如同上述所以省略其說明。Fig. 11 is a flowchart showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention. In the flowchart, the steps of designating the same reference numerals as in the first embodiment are as described above, and thus the description thereof will be omitted.
首先在半導體層的表面上形成第1絕緣膜以及第2絕緣膜(步驟10a)。參照第12圖說明步驟10a。第12圖是表示在半導體層32的表面上形成第1絕緣膜50，並在第1絕緣膜50的表面上形成第2絕緣膜52的圖。第1絕緣膜50用SiN形成，而第2絕緣膜52用SiOx形成。繼之，當步驟12、14以及16結束時，以光阻54和硬化層56a以及56b作為遮罩，蝕刻第1絕緣膜50以及第2絕緣膜52(步驟18a)。參照第13圖說明步驟18a。第13圖是表示藉由蝕刻形成有開口的第1絕緣膜50a(以後稱之為第1絕緣膜50a)及有開口的第2絕緣膜52a(以後稱為第2絕緣膜52a)的圖。First, a first insulating film and a second insulating film are formed on the surface of the semiconductor layer (step 10a). Step 10a will be described with reference to Fig. 12. FIG. 12 is a view showing that the first insulating film 50 is formed on the surface of the semiconductor layer 32, and the second insulating film 52 is formed on the surface of the first insulating film 50. The first insulating film 50 is formed of SiN, and the second insulating film 52 is formed of SiOx. Then, when steps 12, 14 and 16 are completed, the first insulating film 50 and the second insulating film 52 are etched by using the photoresist 54 and the hardened layers 56a and 56b as masks (step 18a). Step 18a will be described with reference to Fig. 13. Fig. 13 is a view showing a first insulating film 50a (hereinafter referred to as a first insulating film 50a) having an opening formed by etching and a second insulating film 52a (hereinafter referred to as a second insulating film 52a) having an opening.
接著，選擇性蝕刻第2絕緣膜52a(步驟19)。參照第14圖說明步驟19。第14圖是表示選擇性蝕刻第2絕緣膜52a的圖。第2絕緣膜52a的蝕刻係以用氟自由基的乾蝕刻、氟酸系濕蝕刻、或將兩者並用實施。藉由此蝕刻使得第2絕緣膜52b的開口寬幅大於第1絕緣膜50a的開口寬幅。此外，第2絕緣膜52b的開口寬幅比光阻54的開口寬幅狹窄。Next, the second insulating film 52a is selectively etched (step 19). Step 19 will be explained with reference to Fig. 14. Fig. 14 is a view showing selective etching of the second insulating film 52a. The etching of the second insulating film 52a is performed by dry etching using a fluorine radical, wet etching by a hydrofluoric acid, or both. By this etching, the opening width of the second insulating film 52b is made larger than the opening width of the first insulating film 50a. Further, the opening width of the second insulating film 52b is narrower than the opening of the photoresist 54.
繼之執行步驟20、22以及24形成具有多段形狀的場電極構造的閘電極。第15圖是表示具有多段形狀的場電極構造的閘電極60的圖。場電極構造係由在第1絕緣膜50a上的部分和在第2絕緣膜52b上的部分而形成多段形狀。像這樣地把場電極構造作為多段形狀，就能提高半導體裝置的耐壓性。Subsequent steps 20, 22, and 24 are performed to form a gate electrode having a multi-segment field electrode configuration. Fig. 15 is a view showing a gate electrode 60 having a field electrode structure having a multi-stage shape. The field electrode structure is formed in a plurality of stages by a portion on the first insulating film 50a and a portion on the second insulating film 52b. By forming the field electrode structure as a multi-stage shape in this manner, the withstand voltage of the semiconductor device can be improved.
如上述，依據本發明的實施形態2的半導體裝置的製造方法，藉由使第2絕緣膜52為可以相對於第1絕緣膜50進行選擇性蝕刻的材料，能夠形成具有多段形狀的場電極構造的閘電極60。另外，在對第2絕緣膜52a執行選擇性蝕刻的時候，並不蝕刻第1絕緣膜50a，所以能控制閘開口部的側面蝕刻。As described above, according to the method of manufacturing the semiconductor device of the second embodiment of the present invention, the second insulating film 52 can be selectively etched with respect to the first insulating film 50, whereby a field electrode structure having a plurality of stages can be formed. The gate electrode 60. Further, when the selective etching is performed on the second insulating film 52a, the first insulating film 50a is not etched, so that the side etching of the gate opening can be controlled.
本發明的實施形態2的半導體裝置的製造方法，其特徵在於，使用複數種的膜作為絕緣膜並將場電極構造作成多段形狀。因此，只要能夠進行選擇性蝕刻，絕緣膜的種類有2種以上即可。In the method of manufacturing a semiconductor device according to the second embodiment of the present invention, a plurality of types of films are used as the insulating film, and the field electrode structure is formed into a plurality of stages. Therefore, as long as selective etching can be performed, two or more types of insulating films may be used.
另外，也可以在去除硬化層以後進行選擇性蝕刻，也可以執行複數回選擇蝕刻來調整絕緣膜的開口幅。Alternatively, selective etching may be performed after the hardened layer is removed, or a plurality of selective etching may be performed to adjust the opening width of the insulating film.
30．．．基板30. . . Substrate
32．．．半導體層32. . . Semiconductor layer
34．．．絕緣膜34. . . Insulating film
36．．．光阻36. . . Photoresist
38a、38b．．．硬化層38a, 38b. . . Hardened layer
40．．．金屬層40. . . Metal layer
40a．．．具有場電極構造的閘電極40a. . . Gate electrode with field electrode configuration
第1圖為表示有關本發明的實施的形態1的半導體裝置的製造方法的流程圖。Fig. 1 is a flowchart showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
第2圖為表示在半導體層的表面上形成絕緣膜的圖。Fig. 2 is a view showing formation of an insulating film on the surface of a semiconductor layer.
第3圖為表示在絕緣膜的表面上形成光阻的圖。Fig. 3 is a view showing formation of a photoresist on the surface of an insulating film.
第4圖為表示在光阻上形成開口的圖。Fig. 4 is a view showing the formation of an opening in the photoresist.
第5圖為表示根據RELACS處理形成硬化層的圖。Fig. 5 is a view showing formation of a hardened layer by RELACS treatment.
第6圖為表示蝕刻絕緣膜的圖。Fig. 6 is a view showing an etching insulating film.
第7圖為表示去除硬化層的圖。Fig. 7 is a view showing the removal of the hardened layer.
第8圖為表示形成金屬層的圖。Fig. 8 is a view showing the formation of a metal layer.
第9圖為表示用剝離法形成具有場電極構造的閘電極的圖。Fig. 9 is a view showing a gate electrode having a field electrode structure formed by a lift-off method.
第10圖為表示有關本發明的實施的形態1的半導體裝置的製造方法的變形例的圖。FIG. 10 is a view showing a modification of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
第11圖為表示有關本發明的實施的形態2的半導體裝置的製造方法的流程圖。Fig. 11 is a flow chart showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
第12圖為表示在半導體層的表面上形成第1絕緣膜，在第1絕緣膜的表面上形成第2絕緣膜的圖。Fig. 12 is a view showing that a first insulating film is formed on the surface of the semiconductor layer, and a second insulating film is formed on the surface of the first insulating film.
第13圖為表示藉由蝕刻有開口的第1絕緣膜和有開口的第2絕緣膜的圖。Fig. 13 is a view showing a first insulating film having an opening and a second insulating film having an opening.
第14圖為表示選擇性蝕刻第2絕緣膜的圖。Fig. 14 is a view showing selective etching of the second insulating film.
第15圖為表示具有多段形狀的場電極構造的閘電極的圖。Fig. 15 is a view showing a gate electrode having a field electrode structure having a multi-stage shape.
10～24．．．步驟10~24. . . step
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| US9525052B2 (en) * | 2007-01-10 | 2016-12-20 | Infineon Technologies Americas Corp. | Active area shaping of III-nitride devices utilizing a field plate defined by a dielectric body |
| WO2008086001A2 (en) | 2007-01-10 | 2008-07-17 | International Rectifier Corporation | Active area shaping for iii-nitride device and process for its manufacture |
| US9318592B2 (en) * | 2007-01-10 | 2016-04-19 | Infineon Technologies Americas Corp. | Active area shaping of III-nitride devices utilizing a source-side field plate and a wider drain-side field plate |
| US8946779B2 (en) * | 2013-02-26 | 2015-02-03 | Freescale Semiconductor, Inc. | MISHFET and Schottky device integration |
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| CN105448704B (en) * | 2014-09-30 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | Lithographic method |
| CN104701154A (en) * | 2015-03-11 | 2015-06-10 | 北京工业大学 | Preparation method for sub-half-micron T-shaped gate via chemical shrinkage method |
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