TWI459435B - Active matrix substrate manufacturing method and the structure thereof - Google Patents

Description

Active device array substrate manufacturing method and structure thereof

The present invention relates to an active device array substrate manufacturing method and structure thereof for use in a liquid crystal display device, and more particularly to an active device array substrate manufacturing method and structure thereof for uniformly coating an alignment film.

Generally, a wide viewing angle technology-in-Plane-Switching (IPS) pixel film is etched, and the edge is formed with a tilt angle as shown in FIG. 1 of the pixel electrode layer 10, after the alignment film is coated. Friction and alignment will be carried out along the direction of the source line (Source Line), but often due to the electrode tilt angle and the height difference of the electrode, the alignment film is unevenly coated and the brush rubbing alignment is poor, resulting in an abnormal alignment liquid crystal. Light leakage.

Referring to Fig. 2a for explaining the cause of uneven coating of the alignment film, the pixel electrode layer 28 protrudes from the upper surface of the protective film 24. When the film 26 is to be coated, the pixel electrode layer 28 faces the coater. One side (A area) will form a thin film due to the large force, as shown in Figure 2b. The traditional solution to the problem of light leakage in LCD TVs is to use high-density brushes and slow alignment, but the results are not good. Another Japanese company, Hitachi, proposed to replace the protective layer with a thick organic insulating film or a photosensitive pressure film to flatten the thin film transistor array substrate, but the actual results still cannot completely avoid the height difference and tilt angle of the pixel electrode layer. The phenomenon of liquid crystal leakage caused by abnormal alignment.

In order to solve the above problems, an object of the present invention is to provide a method of manufacturing an active device array substrate. By designing a pattern of different light transmittances by using a multi-transmittance type mask to embed the pixel electrode layer in the protective layer, the mask process can be reduced to reduce the manufacturing cost, and the lift off process can be eliminated. The mask process can be shortened to increase productivity.

One of the objects of the present invention is to provide an active device array substrate. The pixel electrode layer is placed in the protective layer in a thin film transistor array substrate, and the surface of the alignment film is flattened when the alignment film is coated to avoid liquid crystal light leakage.

In order to achieve the above object, an active device array substrate manufacturing method according to an embodiment of the present invention includes: providing a substrate; forming a plurality of gate wirings on the substrate; forming a gate insulating layer on the substrate and covering the gate wiring; forming a protection Laminating on the gate insulating layer; forming a first photoresist layer on the protective layer and etching the first photoresist layer and the underlying protective layer on the mask pattern on the multi-transmission mask to form at least one recess; Wherein the groove is located in the protective layer and the depth of the groove is smaller than the thickness of the protective layer; forming a pixel electrode layer in the groove, wherein the top surface of the pixel electrode and the surface of the protective layer outside the groove are flat Forming a surface structure; removing the first photoresist layer; and forming an alignment film layer on the protective layer and covering the pixel electrode layer.

In order to achieve the above object, an active device array substrate manufacturing method according to an embodiment of the present invention includes: providing a substrate; forming a plurality of gate wirings on the substrate; forming a gate insulating layer on the substrate and covering the gate wiring; forming a protection Laminating on the gate insulating layer; forming a first photoresist layer on the protective layer and etching the first photoresist layer and the underlying protective layer on the mask pattern on the multi-transmission mask to form at least one recess; Wherein the groove is located in the protective layer and the depth of the groove is smaller than the thickness of the protective layer; the first photoresist layer is removed; the pixel electrode layer is formed on the protective layer and the groove, wherein the top surface of the pixel electrode is Forming a planarized surface structure with the protective layer outside the groove; laying a second photoresist layer to be retained And removing a portion of the pixel electrode layer; removing the second photoresist layer; and forming an alignment film layer on the protective layer and covering the conductive film.

Furthermore, an active device array substrate according to an embodiment of the invention includes: a substrate; a plurality of gate wirings are disposed on the substrate; a gate insulating layer is disposed on the substrate and covers the gate wiring; and a protective layer is disposed on the gate insulating layer And having at least one groove; a pixel electrode layer is disposed in the groove; and an alignment film layer is disposed on the protective layer and covering the pixel electrode layer.

FIG. 3 is a cross-sectional view showing a pixel structure of an active device array substrate on an IPS according to an embodiment of the present invention. In this embodiment, a plurality of pixels having a wide viewing angle technology-transverse electric field switching (IPS) are provided on a substrate of a liquid crystal display, and the substrate is a glass substrate, and has a plurality of gate wirings and a plurality of source wirings. The intersection is disposed on the glass substrate. A gate insulator (GI) 32 is disposed on the glass substrate (not shown) in each pixel to protect the gate wiring from forming an electrical barrier, and the gate insulating layer 32 has a protective layer (passivation insulator). 34, the protective layer 34 is provided with a recess 39. The pixel electrode layer 38 is disposed in the recess 39 and forms a flat surface with the protective layer 34. A uniform alignment film 36 can be coated to inject the liquid crystal molecules. The material of the alignment film 36 comprises a polyimide (PI) liquid film.

In one embodiment, the protective layer 34 is made of tantalum nitride (SiNx) and is provided with a source electrode and a drain electrode. Further, the protective layer 34 has a recess 39 having a depth of about 1000 Å, which can be disposed. A pixel electrode layer 38 made of chromium (Cr) or indium tin oxide (ITO) is used as a pixel.

Fig. 4 is a view showing a method of manufacturing an active device array substrate in which an alignment film (PI) is uniformly coated according to an embodiment of the present invention. Please also refer to Figure 5a. Step S41 provides a substrate module. The lowermost layer of the substrate module is a glass substrate 51. A gate insulating layer 52 is formed on the glass substrate 51, and the gate wiring on the glass substrate 51 is covered. The gate insulating layer 52 is provided with a protective layer 53; in step S42, a photoresist layer is formed, and the photoresist layer 54 is disposed on the protective layer 53; in step S43, the light 58 passes through a multi-transmittance mask 55. The mask pattern is exposed to the photoresist layer 54 and developed to remove portions of the photoresist layer 54 and to pattern the gate insulating layer 52 and the protective layer 53, as shown in FIGS. 5b and 5c. Step S44: etching the protective layer 53 to form a recess 59 having a depth as shown in FIG. 5d; then, step S45 is performed to peel off the photoresist layer 54 as shown in FIG. 5e; and step S46 is to deposit the pixel electrode layer by sputtering. 56 is formed on the protective layer 53 as shown in FIG. 5f; step S47 forms another photoresist layer 57 and is exposed, developed and etched, and the remaining photoresist layer 57 is as shown in FIG. 5g; step S48 will be exposed. The pixel electrode layer 56 removes and peels off the photoresist layer 57. As shown in FIGS. 5h and 5i, the pixel electrode layer 56' in the recess 59 has the same height as the upper surface of the protective layer 53, that is, the pixel. The electrode layer 56' and the protective layer 53 constitute a flat surface; and finally, in step S49, the alignment film layer is uniformly coated on the flat surface.

According to the above, one of the features of the present invention is that the conductive film is sputtered in a groove having a depth of about 1000 Å, that is, a pixel electrode is formed in the protective layer, so that the surface of the protective layer and the pixel electrode layer is flat, and finally coated. After the alignment film layer is on the plane, the alignment film can be uniformly formed on a plane. Wherein, the material of the pixel electrode layer comprises a material of chromium (Cr) or indium tin oxide as a pixel electrode, a material of the protective layer comprises tantalum nitride (SiNx), and a material of the alignment film layer comprises polyamidamine ( Polyimide, PI) liquid film.

FIG. 6 is a schematic diagram showing the structure of a jumper in a pixel according to an embodiment of the invention. The contact window 60 of the flat surface structure is located in each pixel on the substrate, and the manufacturing flow diagram of the section line AA' is as shown in FIGS. 7a to 7h, and the first metal layer and the second metal are included in the pixel. a layer, wherein the first metal layer is a common electrode 61 and a gate electrode 61', the second metal layer is a source electrode (data line) 62, and the pixel electrode layer 63 and the common electrode 61 have a contact window 60, a pixel The electrode layer 63' has a contact window 60' with the source electrode 62. 7A is a substrate module, the lowermost layer of the substrate module is a glass substrate 71, a gate insulating layer 72 is formed on the glass substrate 71, and a protective layer 73 is formed on the gate insulating layer 72. A photoresist layer 74 is formed on the protective layer 73, and then the light 70 passes through a mask pattern etched photoresist layer 74 on the transmittance mask 75 to expose the gate electrode 78 and the source electrode 79. As shown in FIG. 7b; in FIG. 7c, the photoresist layer 74 is continuously etched to expose the protective layer 73; and in FIG. 7d, the etching protection layer 73 is formed to form a recess 789 having a specific depth; FIG. 7e Shown is the stripping of the photoresist, followed by sputtering of the pixel electrode layer 76 on the surface of the protective layer 73 as shown in Figure 7f; Figure 7g shows the photoresist layer 77 applied to the area to be retained, and finally The pixel electrode layer removal and the photoresist stripping at other portions form a flat surface with the pixel electrode layer 76' on the surface of the B region protective layer 73 as shown in Fig. 7h.

In the above process, the gate insulating layer 72 is provided with a gate electrode 78. When the photoresist layer 74 is etched, the gate insulating layer 72 is simultaneously etched to expose the gate electrode 78; and the protective layer 73 is provided with the source electrode 79. When the photoresist layer 74 is etched, the protective layer 73 is simultaneously etched to expose the source electrode 79.

In one embodiment, the multi-transmission mask 75 can be a halftone mask (HTM) having two transmittances or more, and a gray dimming mask having different transmittances by using a slit to diffract the image. (Gray Tone Mask, GTM), or one of a group of Stacked Layers Masks (SLMs).

Fig. 8 is a view showing a method of manufacturing a substrate structure in which an alignment film (PI) is uniformly coated according to another embodiment of the present invention. Step S81 provides a substrate module. As shown in FIG. 9a, the lowermost layer of the substrate module is a glass substrate 91. A gate insulating layer 92 is formed on the glass substrate 91, and the gate wiring on the glass substrate 91 is covered. A protective layer 93 is formed on the gate insulating layer 92; a photoresist layer 94 is formed on the protective layer 93 in step S82; and a light mask pattern on the mask 95 is etched in a multi-transmission rate mask 95 in step S83. The resist layer 94 exposes the protective layer 93 as shown in FIGS. 9b and 9c; in step S84, the protective layer 93 is formed to form a recess 989 having a specific depth as shown in FIG. 9d; and in step S85, the pixel electrode layer is formed. 96 is sputtered on the surface as shown in Fig. 9e; step S86 lifts the photoresist layer and removes the pixel layer of the other portion, as shown in Fig. 9f. Inside, the surface of the protective layer 93 forms a flat surface with the pixel electrode layer 96'; at the end of step S87, the alignment film layer is uniformly coated on the flat surface.

In addition, the gate insulating layer 92 is provided with a gate electrode 98. When the photoresist layer 94 is etched, the gate insulating layer 92 is simultaneously etched to expose the gate electrode 98; and the protective layer 93 is provided with a source electrode 99, and the photoresist layer is etched. At 94 o'clock, the protective layer 93 is simultaneously etched to expose the source electrode 99.

In one embodiment, the multi-transmission mask 95 can be a halftone mask (HTM) having two transmittances or more, and a gray dimming mask (GTM) having different transmittances by using a slit to diffract the image. Or one of a group of multi-layer stacked photomasks (SLMs).

According to the method described above, the insulating layer is provided with a gate electrode. In the step of etching the photoresist layer, the gate insulating layer is simultaneously etched to expose the gate electrode; and the protective layer is provided with a source electrode and a drain electrode. In the step of etching the photoresist layer, the gate insulating layer is also etched to expose the gate electrode.

In summary, the present invention utilizes a multi-light transmittance mask to design a pattern having a different transmittance so that the protective layer has a groove that can accommodate a pixel electrode layer or a common electrode, and the pixel layer is placed. The protective layer is used to create a flat surface, thereby avoiding the occurrence of light leakage caused by the alignment abnormal region.

The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention.

10, 28, 38, 56, 56', 63, pixel electrode layers 63', 76, 76', 96, 96' ‧ ‧ ‧ pixel layer

24‧‧‧Protective film

26, 36‧‧‧ alignment film

32, 52, 72, 92‧‧‧ gate insulation

34, 53, 73, 93‧‧ ‧ protective layer

39, 59, 789, 989 ‧ ‧ grooves

51, 71, 91‧‧‧ glass substrates

54, 57, 74, 77, 94‧‧‧ photoresist layer

55, 75, 95‧‧‧Multi-transmission mask

58, 70‧‧‧ rays

60, 60’ ‧ ‧ contact window

61‧‧‧Common electrode

62, 79, 99‧‧‧ source electrode

61', 78, 98‧‧‧ gate electrodes

A‧‧‧ pixel electrodes facing one side of the coater

B, C‧‧‧ The surface of the protective layer and the flat surface formed by the conductive film

S41~S49‧‧‧ steps of the substrate structure manufacturing method according to the embodiment of the present invention

S81~S87‧‧‧ steps of the method for manufacturing a substrate structure according to an embodiment of the present invention

Fig. 1 is a structural diagram of a pixel electrode layer of a conventional wide viewing angle technique.

Fig. 2a and Fig. 2b are schematic diagrams showing the uneven coating of the alignment film.

3 is a cross-sectional view showing a pixel structure of an active device array substrate according to an embodiment of the present invention.

4 is a flow chart showing a method of fabricating an active device array substrate according to an embodiment of the invention.

5a to 5i are schematic views showing a manufacturing process of an active device array substrate according to an embodiment of the present invention.

FIG. 6 is a schematic diagram showing the structure of a jumper in a pixel according to an embodiment of the invention.

7a to 7h are schematic views showing a manufacturing process of an active device array substrate according to an embodiment of the present invention.

FIG. 8 is a flow chart showing a method of fabricating an active device array substrate according to another embodiment of the present invention.

9a to 9f are schematic views showing a manufacturing process of an active device array substrate according to an embodiment of the present invention.

S41~S49. . . Each step of the substrate structure manufacturing method according to an embodiment of the present invention

Claims (12)

A method for manufacturing an active device array substrate, comprising: providing a substrate; forming a plurality of gate wirings on the substrate; forming a gate insulating layer on the substrate and covering the gate wirings; forming a protective layer on the gate insulating Forming a first photoresist layer on the protective layer and etching the first photoresist layer and the protective layer under the photomask pattern on the multi-transmission mask to form at least one recess, wherein The recess is located in the protective layer and the depth of the recess is smaller than the thickness of the protective layer; forming a pixel electrode layer in the recess, wherein a top surface of the pixel electrode layer is outside the recess The surface of the protective layer exhibits a planarized surface structure; the first photoresist layer is removed; and an alignment film layer is formed on the protective layer and covers the pixel electrode layer. The method of manufacturing an active device array substrate according to claim 1, wherein the etching the first photoresist layer further comprises etching the gate insulating layer to expose any of the gate wirings. The method for manufacturing an active device array substrate according to claim 1, wherein the multi-transmission mask is selected from a halftone mask (HTM) having two transmittances or more, and a slit using a slit. It is now one of a group of gray dimmers (GTM) and multi-layer stacked photomasks (SLMs) that create different transmittances. The method for manufacturing an active device array substrate according to claim 1, wherein the forming the pixel electrode layer in the recess further comprises: forming the pixel electrode layer by mask etching using a second photoresist layer. In the recess; and removing the second photoresist layer. The method of manufacturing an active device array substrate according to claim 1, wherein the material of the pixel electrode layer comprises chromium or indium tin oxide. The method for manufacturing an active device array substrate according to claim 1, wherein the material of the protective layer comprises tantalum nitride. The method for manufacturing an active device array substrate according to claim 1, wherein the material of the alignment film layer comprises a polyimide film. An active device array substrate includes: a substrate; a plurality of gate wirings disposed on the substrate; a gate insulating layer disposed on the substrate and covering the gate wirings; a protective layer disposed on the gate insulating layer And having at least one groove, wherein the groove is located in the protective layer and the depth of the groove is smaller than the thickness of the protective layer; a pixel electrode layer is disposed in the groove, wherein the pixel is The top surface of the electrode layer and the surface of the protective layer outside the groove exhibit a planarized surface structure; and an alignment film layer disposed on the protective layer and covering the pixel electrode layer. The active device array substrate according to claim 8, wherein the substrate is a glass substrate. The active device array substrate according to claim 8, wherein the material of the pixel electrode layer comprises chromium or indium tin oxide. The active device array substrate according to claim 8, wherein the material of the protective layer comprises tantalum nitride. The active device array substrate according to claim 8, wherein the material of the alignment film layer comprises a polyimide film.