TWI457826B - 處理器之配置及用於微碼仿真記憶體之快取之方法 - Google Patents

處理器之配置及用於微碼仿真記憶體之快取之方法 Download PDF

Info

Publication number
TWI457826B
TWI457826B TW097119629A TW97119629A TWI457826B TW I457826 B TWI457826 B TW I457826B TW 097119629 A TW097119629 A TW 097119629A TW 97119629 A TW97119629 A TW 97119629A TW I457826 B TWI457826 B TW I457826B
Authority
TW
Taiwan
Prior art keywords
microcode
cache
order cache
instruction
processor
Prior art date
Application number
TW097119629A
Other languages
English (en)
Chinese (zh)
Other versions
TW200905555A (en
Inventor
Gary Lauterbach
Bruce R Holloway
Michael Gerard Butler
Sean Lie
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200905555A publication Critical patent/TW200905555A/zh
Application granted granted Critical
Publication of TWI457826B publication Critical patent/TWI457826B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW097119629A 2007-05-29 2008-05-28 處理器之配置及用於微碼仿真記憶體之快取之方法 TWI457826B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/754,589 US7734873B2 (en) 2007-05-29 2007-05-29 Caching of microcode emulation memory

Publications (2)

Publication Number Publication Date
TW200905555A TW200905555A (en) 2009-02-01
TWI457826B true TWI457826B (zh) 2014-10-21

Family

ID=39708011

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097119629A TWI457826B (zh) 2007-05-29 2008-05-28 處理器之配置及用於微碼仿真記憶體之快取之方法

Country Status (8)

Country Link
US (1) US7734873B2 (https=)
JP (1) JP5496085B2 (https=)
KR (1) KR101503865B1 (https=)
CN (1) CN101707881B (https=)
DE (1) DE112008001473B4 (https=)
GB (1) GB2462556B (https=)
TW (1) TWI457826B (https=)
WO (1) WO2008153799A1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8296528B2 (en) * 2008-11-03 2012-10-23 Intel Corporation Methods and systems for microcode patching
US20120017039A1 (en) * 2010-07-16 2012-01-19 Plx Technology, Inc. Caching using virtual memory
US9529729B2 (en) * 2010-11-16 2016-12-27 International Business Machines Corporation Location of memory management translations in an emulated processor
WO2012156850A1 (en) * 2011-05-19 2012-11-22 International Business Machines Corporation Managing the translation look-aside buffer (tlb) of an emulated machine
CN106469020B (zh) * 2015-08-19 2019-08-09 旺宏电子股份有限公司 高速缓存元件与控制方法及其应用系统
US10884751B2 (en) 2018-07-13 2021-01-05 Advanced Micro Devices, Inc. Method and apparatus for virtualizing the micro-op cache
US11016763B2 (en) 2019-03-08 2021-05-25 Advanced Micro Devices, Inc. Implementing a micro-operation cache with compaction
US11720360B2 (en) * 2020-09-11 2023-08-08 Apple Inc. DSB operation with excluded region
CN119025052B (zh) * 2024-10-29 2025-02-28 上海芯力基半导体有限公司 一种处理器及其内存读取方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132927A (en) * 1990-10-09 1992-07-21 Tandem Computers Incorporated System for cache space allocation using selective addressing
US5826052A (en) * 1994-04-29 1998-10-20 Advanced Micro Devices, Inc. Method and apparatus for concurrent access to multiple physical caches
US20020069328A1 (en) * 2000-08-21 2002-06-06 Gerard Chauvel TLB with resource ID field
US6754765B1 (en) * 2001-05-14 2004-06-22 Integrated Memory Logic, Inc. Flash memory controller with updateable microcode
US20060095807A1 (en) * 2004-09-28 2006-05-04 Intel Corporation Method and apparatus for varying energy per instruction according to the amount of available parallelism

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4901235A (en) 1983-10-28 1990-02-13 Data General Corporation Data processing system having unique multilevel microcode architecture
JPH0738175B2 (ja) * 1987-10-20 1995-04-26 富士通株式会社 仮想記憶装置のデータ保護検査方法
US5278973A (en) 1989-03-27 1994-01-11 Unisys Corporation Dual operating system computer
WO1993006549A1 (en) 1991-09-19 1993-04-01 Chips And Technologies, Inc. A system for performing input and output operations to and from a processor
US5905997A (en) 1994-04-29 1999-05-18 Amd Inc. Set-associative cache memory utilizing a single bank of physical memory
JP3177117B2 (ja) 1994-05-11 2001-06-18 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 複数のノード内の制御コードを更新する方法および装置
JPH07311752A (ja) 1994-05-11 1995-11-28 Internatl Business Mach Corp <Ibm> 分散データ処理システム及び初期プログラムロード方法
US5926642A (en) 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5864689A (en) 1995-12-05 1999-01-26 Advanced Micro Devices, Inc. Microprocessor configured to selectively invoke a microcode DSP function or a program subroutine in response to a target address value of branch instruction
US5950012A (en) * 1996-03-08 1999-09-07 Texas Instruments Incorporated Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes
US5796972A (en) 1997-01-14 1998-08-18 Unisys Corporation Method and apparatus for performing microcode paging during instruction execution in an instruction processor
US6141740A (en) 1997-03-03 2000-10-31 Advanced Micro Devices, Inc. Apparatus and method for microcode patching for generating a next address
US5889978A (en) 1997-04-18 1999-03-30 Intel Corporation Emulation of interrupt control mechanism in a multiprocessor system
WO1999060480A1 (en) 1998-05-15 1999-11-25 Richard Rubinstein Shared, reconfigurable cache memory execution subsystem
JP2000194602A (ja) * 1998-12-28 2000-07-14 Nec Corp 情報処理装置、マイクロプロセッサ及び外部キャッシュメモリの制御方法
US6745306B1 (en) * 1999-07-29 2004-06-01 Microsoft Corporation Method and system for restricting the load of physical address translations of virtual addresses
US6457100B1 (en) * 1999-09-15 2002-09-24 International Business Machines Corporation Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls
US6397301B1 (en) * 1999-12-29 2002-05-28 Intel Corporation Preventing access to secure area of a cache
US6643800B1 (en) 2000-02-02 2003-11-04 Hewlett-Packard Development Company, L.P. Method and apparatus for testing microarchitectural features by using tests written in microcode
US6804772B2 (en) * 2000-06-12 2004-10-12 Broadcom Corporation Dynamic field patchable microarchitecture
US7346757B2 (en) * 2002-10-08 2008-03-18 Rmi Corporation Advanced processor translation lookaside buffer management in a multithreaded system
US7797492B2 (en) * 2004-02-20 2010-09-14 Anoop Mukker Method and apparatus for dedicating cache entries to certain streams for performance optimization
US7370243B1 (en) * 2004-06-30 2008-05-06 Sun Microsystems, Inc. Precise error handling in a fine grain multithreaded multicore processor
JP2006209527A (ja) 2005-01-28 2006-08-10 Nokia Corp コンピュータシステム
US7095342B1 (en) 2005-03-31 2006-08-22 Intel Corporation Compressing microcode
US7827390B2 (en) * 2007-04-10 2010-11-02 Via Technologies, Inc. Microprocessor with private microcode RAM
US7681020B2 (en) * 2007-04-18 2010-03-16 International Business Machines Corporation Context switching and synchronization

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132927A (en) * 1990-10-09 1992-07-21 Tandem Computers Incorporated System for cache space allocation using selective addressing
US5826052A (en) * 1994-04-29 1998-10-20 Advanced Micro Devices, Inc. Method and apparatus for concurrent access to multiple physical caches
US20020069328A1 (en) * 2000-08-21 2002-06-06 Gerard Chauvel TLB with resource ID field
US6754765B1 (en) * 2001-05-14 2004-06-22 Integrated Memory Logic, Inc. Flash memory controller with updateable microcode
US20060095807A1 (en) * 2004-09-28 2006-05-04 Intel Corporation Method and apparatus for varying energy per instruction according to the amount of available parallelism
TW200632742A (en) * 2004-09-28 2006-09-16 Intel Corp Method and apparatus for varying energy per instruction according to the amount of available parallelism

Also Published As

Publication number Publication date
DE112008001473B4 (de) 2021-08-26
GB2462556B (en) 2012-05-30
US7734873B2 (en) 2010-06-08
JP2010529534A (ja) 2010-08-26
GB0920954D0 (en) 2010-01-13
US20080301364A1 (en) 2008-12-04
CN101707881A (zh) 2010-05-12
CN101707881B (zh) 2016-06-15
GB2462556A (en) 2010-02-17
KR20100022483A (ko) 2010-03-02
WO2008153799A1 (en) 2008-12-18
TW200905555A (en) 2009-02-01
DE112008001473T5 (de) 2010-07-01
KR101503865B1 (ko) 2015-03-24
JP5496085B2 (ja) 2014-05-21

Similar Documents

Publication Publication Date Title
TWI457826B (zh) 處理器之配置及用於微碼仿真記憶體之快取之方法
TWI522802B (zh) 確保微處理器之快取記憶體層級之資料一致性的裝置與方法
US7797503B2 (en) Configurable memory system and method for providing atomic counting operations in a memory device
JP4040623B2 (ja) 階層型キャッシュメモリを制御するための方法ならびに装置
US11144458B2 (en) Apparatus and method for performing cache maintenance over a virtual page
TWI526829B (zh) 電腦系統、用於存取儲存裝置之方法及電腦可讀儲存媒體
US12332790B2 (en) Multi-level cache security
US5070502A (en) Defect tolerant set associative cache
JP2016534431A (ja) ロード／記憶ユニット及びデータキャッシュの順序付け及びバンド幅の向上
JP2001142779A (ja) 改善されたメモリ管理ユニット及びキャッシュメモリを有するマイクロプロセッサを用いたデータ処理方法
JP2001147857A (ja) 改善されたメモリ管理ユニット及びキャッシュメモリを有するマイクロプロセッサを用いたデータ処理方法
JP2001202287A (ja) 改善されたメモリ管理ユニット及びキャッシュメモリを有するマイクロプロセッサを用いたデータ処理方法
JPWO2010035425A1 (ja) キャッシュメモリ、その制御方法及びメモリシステム
CN107771322B (zh) 可编程集成电路中存储器资源的管理
JP2001142780A (ja) 改善されたメモリ管理ユニット及びキャッシュメモリを有するマイクロプロセッサを用いたデータ処理方法
CN115098409B (zh) 进行阶层式高速缓存系统回存且无效的处理器以及方法
US8108621B2 (en) Data cache with modified bit array
US20150058574A1 (en) Increasing The Efficiency of Memory Resources In a Processor
US9886212B2 (en) Mechanism for copying data in memory
US8108624B2 (en) Data cache with modified bit array

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent