TWI453914B - Semiconductor device and manufacturing method of the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device such as an IC or an LSI, and more particularly to an accumulation type MOS transistor.

The above-mentioned semiconductor device is described in Japanese Patent Application Laid-Open No. 2005-349857 (Patent Document 1). Patent Document 1 proposes a semiconductor device including a circuit having at least one pair of transistors of different conductivity types, at least one of the pair of transistors including at least a semiconductor layer provided on the SOI substrate, covering the semiconductor layer a gate insulating film of at least a portion of a surface of the semiconductor layer and a gate electrode formed on the gate insulating film to form a normally-off type of accumulation, the semiconductor In the device, the material of the gate electrode and the impurity concentration of the semiconductor layer are appropriately selected such that the thickness of the depletion layer formed on the semiconductor layer is greater than the thickness of the semiconductor layer by the difference in work function between the gate electrode and the semiconductor layer .

Further, Patent Document 1 discloses that in order to make the current driving capability of the p-channel transistor and the n-channel transistor constituting the CMOS transistor equal, the current of the p-channel transistor can be driven by using the (110) plane of the 矽. Improve ability. According to this configuration, the switching speeds of the n-channel transistor and the p-channel transistor can be substantially equal, and the occupied areas of the electrodes formed on the channel region are substantially equal.

[Patent Document 1] Japanese Invention Patent Application No. 2005-349857

Patent Document 1 discloses that an accumulation type MOS transistor is normally closed by a difference in work function between a gate electrode and an SOI layer. For example, when containing the polysilicon gate electrode is formed of boron 10 ²⁰ cm ^-3 or more, P + polysilicon work function of about 5.15 eV, and if the impurity concentration of the SOI layer based 10 ¹⁷ cm ^-3 of n-type silicon layer, which The work function is about 4.25 eV, thus producing a work function difference of about 0.9 eV. At this time, the thickness of the depletion layer is about 90 nm. Assuming that the thickness of the SOI layer is 45 nm, the SOI layer is completely depleted and a normally-off transistor can be obtained.

However, this configuration has a disadvantage that the material that can be used for the gate electrode is limited. For example, if Ta is to be used as a material for the gate electrode, since the work function is 4.6 eV, the difference from the work function of the SOI layer is small, which is difficult to apply. In addition, in the cumulative MOS transistor, when the electro-crystalline system is On, in addition to the current in the build-up layer, a substrate current flows through the entire SOI layer, so that the current drive capability of the transistor is improved. It is necessary to increase the impurity concentration in the SOI layer. The higher the impurity concentration of the SOI layer, the larger the substrate current of the entire SOI layer and the lower the 1/f noise. Thus, for the cumulative MOS transistor, it is preferable to make the SOI layer have a high impurity concentration. However, if the impurity concentration of the SOI layer is increased by one digit, the thickness of the depletion layer becomes 1/4 to 1. /7. Therefore, the film thickness of the SOI layer must be thinned, which in turn reduces the substrate current of the SOI layer as a whole, and as a result, the material of the gate electrode is changed to be larger than the work function difference between the SOI layer and the SOI layer. This causes the threshold voltage of the transistor to increase so that it is difficult to drive under a low power supply voltage.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device which can reduce a threshold voltage and can be miniaturized.

A specific object of the present invention is to provide an accumulation type semiconductor device which can be a normally-off type semiconductor device even if a gate electrode having a small difference in work function from the SOI layer is used.

Another object of the present invention is to provide an accumulation type semiconductor device which does not require an increase in the threshold voltage to be a normally-off type even if the impurity concentration of the SOI layer is increased.

Another object of the present invention is to provide a novel method for controlling the thickness of a depletion layer of an SOI layer, in addition to a work function difference between a gate electrode and an SOI layer.

Another object of the present invention is to provide a method of fabricating a semiconductor device capable of reducing a threshold voltage.

According to a first embodiment of the present invention, there is provided a semiconductor device formed of a substrate, the substrate comprising at least a first semiconductor region, an embedded insulating layer formed on the first semiconductor region, and the embedded insulating layer a second semiconductor region, wherein at least a portion of the second semiconductor region is a channel region having a gate insulating film and a gate electrode thereon, wherein the thickness of the embedded insulating layer and the first semiconductor region are The impurity concentration is used to control the thickness of the depletion layer of the aforementioned channel region.

According to a second embodiment of the present invention, there is provided a semiconductor device comprising a threshold voltage which depends on a thickness of the embedded insulating layer and an impurity concentration of the first semiconductor region.

According to a third embodiment of the present invention, a semiconductor device includes a source region and a drain region electrically connected to the channel region, wherein at least a portion of the gate electrode is provided by the channel region The material of different work functions is composed, and the thickness of the depletion layer of the channel region is determined by the difference in work function between the gate electrode and the channel region, the impurity concentration of the first semiconductor region, and the thickness of the embedded insulating layer. Adjustment. At this time, the impurity concentration of the second semiconductor region is preferably 10 ¹⁷ cm ^-3 or more, more preferably 2 × 10 ¹⁷ cm ^-3 or more.

According to a fourth aspect of the present invention, a semiconductor device is provided, wherein the threshold voltage is smaller than a threshold voltage determined by a difference in work function between the gate electrode and the channel region.

According to a fifth embodiment of the present invention, there is provided a semiconductor device, wherein the first semiconductor region and the second semiconductor region are mutually opposite conductivity type germanium.

According to a sixth aspect of the present invention, a semiconductor device is provided, wherein the channel region, the source region, and the drain region are of a cumulative type of the same conductivity type.

According to a seventh embodiment of the present invention, a normally-off type semiconductor device is provided.

According to an eighth aspect of the present invention, a semiconductor device in which the thickness of the embedded insulating layer is 20 nm or less and which satisfies the following formula is preferable.

0.56T _SOI <T _BOX <1.17T _SOI

Here, T _BOX indicates the embedded insulating layer EOT (Effective Oxide Thickness, namely in terms of a SiO ₂ film thickness), T _SOI of the thickness of the second semiconductor region is represented.

According to a ninth embodiment of the present invention, there is provided a method of fabricating a semiconductor device formed on a substrate having an embedded oxide layer and having a gate electrode and a threshold voltage, wherein the impurity of the substrate is adjusted Concentration to control the aforementioned threshold voltage.

According to a tenth embodiment of the present invention, a method of fabricating a semiconductor device in which an impurity concentration of the substrate is adjusted by ion implantation is provided.

According to another embodiment of the present invention, there is provided a semiconductor device including a gate electrode formed on one of main faces of a semiconductor layer having two main faces via a gate insulating film, in the semiconductor layer The other main surface includes a conductive layer disposed via the embedded insulating layer, wherein at least a portion of the semiconductor layer is a channel region, and the embedded insulating layer has a thickness of 20 nm or less, and the gate electrode is A difference in work function between the material and the semiconductor layer, and a difference in work function between the conductive layer and the semiconductor layer, such that the thickness of the depletion layer of the channel region is greater than the thickness of the semiconductor layer.

According to the present invention, there is provided a semiconductor device which is characterized in that a film thickness of an insulating layer is thinned, a thickness of a depletion layer in a channel region is thinned, and a novel semiconductor device controlled by an impurity concentration of a semiconductor region on a substrate side is provided. . In particular, in the MOSFET of the accumulation type, by adjusting the impurity concentration of the substrate, even if the effect is not controlled by the difference in work function between the gate electrode and the channel region, or by multiplying the effect, the threshold voltage can be increased without increasing the threshold voltage. Normally closed type. An advantage of the present invention is that a semiconductor device having a low threshold voltage and being miniaturized can be provided. That is, according to the present invention, a semiconductor device having a high speed and a low power supply voltage can be constructed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

Referring to Fig. 1, there is shown an accumulation type MOS transistor and an inversion MOS transistor to which the present invention is applicable. Figure 1 (a), (b) show n and p channels respectively. Cumulative MOS transistors (NMOS transistors and PMOS transistors), and (c) and (d) in Fig. 1 show n and p channel/inversion MOS transistors, respectively.

In the NMOS transistor shown in FIG. 1(a), an embedded insulating layer (BOX) is formed in a surface region of a p-type germanium substrate, and an n-type SOI is formed on the embedded insulating layer (BOX) (Silicon On Insulator) layer. Also, the n-type SOI layer forms a source region, a drain region, and a channel region. Among them, the source region and the drain region have a higher impurity concentration than the channel region. Further, the source region and the drain region are connected to the source S and the drain D, respectively. Here, a gate insulating film is formed on the channel region, and a gate electrode of a p-type polysilicon is provided on the gate insulating film.

On the other hand, in the PMOS transistor shown in FIG. 1(b), an embedded insulating layer (BOX) is formed on the n-type germanium substrate, and a source region is formed on the embedded insulating layer (BOX). The p-type SOI layer in the drain region and the channel region, the source region and the drain region have a higher impurity concentration than the channel region. Further, a gate electrode of an n-type polysilicon is provided over the channel region via a gate insulating film. Figures 1 (c) and (d) are also shown.

When the gate voltage Vg is zero in the NMOS transistor and the PMOS transistor shown in FIGS. 1(a) and (b), the depletion layer is diffused throughout the SOI layer, and the actuation system is: when the gate voltage Vg is pressurized. The depletion layer is shrunk to the upper side of the channel region, and when the gate voltage Vg is higher, the current is saved in addition to the substrate current.

2(a) to (d) show the operation principle of the above-described cumulative NMOS transistor. First, as shown in FIG. 2(a), when the gate voltage Vg is zero, a depletion-layer spreads over the entire SOI layer. Next, as shown in FIG. 2(b), after the gate voltage Vg is applied, the depletion layer is shrunk to the upper side of the channel region, and the substrate current Ibulk is flown. In addition, when the gate voltage Vg increases, as shown in FIGS. 2(c) and (d), the saving current Iacc also starts to flow.

Taking the NMOS as an example and referring to FIG. 3(a) and (b) in detail, the above phenomenon is described in detail, and the SOI structure is employed to make the depletion layer generated by the difference in work function between the gate electrode and the SOI layer. When the thickness is larger than the thickness of the SOI layer, a MOS transistor having a cumulative structure as shown in Fig. 3(a) and a normally-off type can be realized. Here, in the NMOS transistor shown in the figure, P ⁺ polysilicon (work function is 5.2 eV) is used for the gate electrode, and in the p channel transistor, n ⁺ polysilicon (work function is 4.1 eV) is used. At the gate electrode, thereby creating a difference in work function with the SOI layer.

In order to make the depletion layer thicker than the SOI layer, and to achieve the off state when the gate voltage Vg is zero (that is, the normally off state), it is necessary to change the work function of the gate electrode compared to the work function of the SOI layer. Big. However, according to this method, the above problems occur, and in particular, increasing the impurity concentration of the SOI layer has the disadvantage of increasing the threshold voltage. In other words, according to the manufacturing method of the conventional accumulation type NMOS transistor, only a transistor having a relatively high threshold voltage can be manufactured. As a result, not only can the transistor be miniaturized, but also the integrated circuit can be reduced in voltage. Also, the gate electrode cannot use Ta (4.6 eV) whose work function difference is small.

The inventor of the present invention produces an MOS transistor (particularly an NMOS transistor) as shown in FIGS. 1(a) and (b), which is a reverse conductivity type of a tantalum substrate and an SOI layer, and is embedded in an insulating layer (BOX). An accumulated NMOS transistor having a thickness of 100 nm was tested. The structure of the NMOS transistor used in this experiment is the same as that disclosed in Patent Document 1. In addition, the NMOS transistor used in the experiment has an effective channel length (Leff) of 45 nm, a channel width of 1 μm, an impurity concentration of 2 × 10 ¹⁷ cm ^-3 in the channel region, and 1 × as a germanium substrate. 10 ¹⁵ cm ^-3 p-type germanium substrate.

The thickness of the gate insulating film was EOT = 1 nm, and p ⁺ polysilicon (having a work function of 5.1 eV) was used as the gate electrode. As a result, it has been found that if the thickness of the SOI layer is reduced to about 17 nm or less, the threshold voltage of the NMOS transistor can be controlled even when the impurity concentration of the germanium substrate is constant (for example, 1 × 10 ¹⁵ cm ^-3 ).

Further, it has been found that if the thickness of the SOI layer is reduced to the extent of 1/3 (15 nm) of the effective channel length Leff, the short channel effect can be effectively controlled. That is, by controlling the thickness of the SOI layer, the threshold voltage of the accumulation type NMOS transistor can be changed to 0.4 to 0.5V.

However, the threshold voltage of the NMOS transistor constructed as described above depends only on the difference in work function between the gate electrode and the SOI layer, and therefore, the threshold voltage cannot be lowered to the extent that it can be applied to a low voltage power source. In other words, for an accumulation type NMOS transistor using an embedded insulating layer (BOX) of about 100 nm, even if the impurity concentration of the germanium substrate is changed, the threshold voltage depending on the work function difference cannot be changed, and Ta is used. With a work function of 4.6 eV as a gate electrode, a normally-off transistor cannot be realized.

That is, as in the case of the previously proposed transistor, in the case of having an embedded insulating layer (BOX) of about 100 nm, as shown in FIG. 4, since the thickness of the embedded insulating layer is large, the SOI layer is formed only on the gate electrode side. control.

In contrast, the inventors of the present invention have found a phenomenon in which the potential of the SOI layer can be controlled from the substrate (Base Substrate) side by reducing the thickness of the embedded insulating layer (BOX) as shown in FIG.

That is, the thickness (T _BOX ) of the embedded insulating layer (BOX) is reduced to less than 20 nm, and the support substrate, that is, the germanium substrate, is implanted with ions from the surface thereof (the side constituting the gate electrode thereafter), and is caused to cause 矽An NMOS transistor in which the impurity concentration (NBase) of the substrate is changed, and then a drain voltage (Vd) of 1 V is applied to the transistor, and a change in the drain current is detected. As a result, it is found that the impurity concentration (NBase) of the substrate depends on The threshold voltage of the NMOS transistor also changes accordingly.

As shown in FIG. 5, the SOI layer and the substrate are reverse-conducting type, so that the embedded insulating layer (BOX) is thinned, whereby the difference in work function between the substrate and the SOI layer causes the SOI layer to be depleted, and as a result, as the Ta gate electrode Even if a gate electrode having a small difference in work function from the SOI layer is used, a normally-off state can be realized, and high speed and low power supply voltage can be realized. According to this configuration, the threshold voltage is effectively controlled by adjusting the thickness of the embedded insulating layer (BOX) and/or the impurity concentration of the SOI layer, and the threshold voltage is finely adjusted by controlling the concentration of the supporting substrate. Further, as the substrate material, a conductive material having a large work function difference to the SOI layer can also be used.

Here, when the substrate is a predetermined impurity concentration (NBase) and the impurity (impurity) is introduced by ion implantation, the impurity concentration N(x) in the depth direction (x) of the substrate is expressed by the following formula (1). ) can be obtained.

Here, the Q system is injected, R _P is the projection distance, and ΔR ² _P is the standard deviation.

In the above formula, the maximum value of the concentration can be expressed by the following number 2, and N(x) needs to be controlled within the range of 0.2N _MAX ~ 0.5 N _MAX .

Ion implantation conditions so the device, △ R _P can be approximated 0.3R _P, therefore, the relationship can be obtained 0.36R _P <x <0.46R _P's. Since _{(0.36 / 0.64) T SOI <} T BOX <(0.46 / 0.54) T SOI, and therefore may be derived 0.56T _SOI <T _BOX <0.85T _SOI of formula. Here, T _BOX indicates the embedded insulating layer EOT (Effective Oxide Thickness, namely in terms of film thickness is SIO _2), T _SOI represents the thickness of the SOI layer.

Fig. 6 shows the characteristics of the gate voltage (Vg) - the drain current (Id) (A) of the cumulative NMOS transistor in which the SOI layer is formed on the (100) plane of the germanium substrate. Here, the effective channel length (Leff) and the channel width (W) of the transistor are 45 nm and 1 μm, respectively, the gate insulating film has an SiO ₂ equivalent thickness (EOT) of 1 nm, and the SOI layer thickness (TSOI) is 15 nm. And in the SOI layer, the impurity concentration (Nsub) of the channel region is 2 × 10 ¹⁷ cm ^-3 . In addition, FIG. 6 also shows the characteristics when 钽 (Ta) whose work function (WF) is 4.6 V is used as a gate electrode, and a drain voltage Vd of 1 V is applied to the drain.

In Fig. 6, under the above conditions, the thickness (TBOX) of the embedded insulating layer and the impurity concentration (NBase) of the germanium supporting substrate were changed. That is, the curve C1 represents the characteristic of the gate voltage-drain current in the case where NBase is 1 × 10 ¹⁸ cm ^-3 and TBOX is 12 nm, and the curve C2 represents 1 × 10 ¹⁸ cm ^-3 in NBase. And the characteristics of the gate voltage - the drain current in the case where the TBOX is 15 nm.

Further, the curve C3 indicates the characteristics of the gate voltage - the drain current in the case where the NBase is 1 × 10 ¹⁸ cm ^-3 and the TBOX is 20 nm. Similarly, the curves C4 and C5 indicate that the TBOX is 20 nm and the N Base is 1 respectively. The characteristics of the gate voltage - the drain current in the case of × 10 ¹⁷ cm ^-3 and 1 × 10 ¹⁶ cm ^-3 .

It is known from the curves C1 to C5 that the gate voltage-drain current characteristic is also obtained in the range in which the thickness (TBOX) of the embedded insulating layer is 20 nm or less with the impurity concentration (NBase) of the germanium substrate supporting the substrate. Variety. As a result, in the case of using the Ta gate electrode, the normally-off type can also be realized. Further, depending on the thickness of the embedded insulating layer (TBOX), the gate voltage-drain current characteristic and the threshold voltage (the gate voltage when the current is 1 μA is defined as the threshold voltage by the constant current method) are controlled to 0.05 to 0.2. Within the scope of V. Further, it is known from the curves C1 and C5 that when the embedded insulating layer (TBOX) is 20 nm or less, the threshold voltage of the NMOS transistor can be changed depending on the impurity concentration (NBase) of the substrate, and it is known from C1 to C3. The thickness (TBOX) of the embedded insulating layer is varied so that the threshold voltage can be varied. In addition, the threshold voltage can be finely adjusted by adjusting the concentration of the support substrate.

On the other hand, when the thickness (TBOX) of the embedded insulating layer is 20 nm, as shown by the curves C3 to C5, the threshold voltage is finely adjusted depending on the impurity concentration (NBase) of the substrate, but if it is thicker than the above thickness , no longer depends on the concentration of impurities in the substrate.

In summary, as described above, the threshold voltage is finely adjusted by adjusting the impurity concentration (NBase) of the germanium substrate.

In addition, as shown in FIG. 7, the gate voltage-throwth current characteristic when the impurity concentration (Nsub) of the SOI layer and the thickness (TBOX) of the embedded insulating layer are changed in a state where the impurity concentration (NBase) of the germanium substrate is constant is shown. Here, the object accumulation type NMOS transistor has an effective channel length (Leff) of 45 nm and 1 μm and a channel width (W) as shown in FIG. 6, and has a SiO ₂ conversion thickness of a gate insulating film of 1 nm ( EOT), 15 nm SOI layer thickness (TSOI). Further, the impurity concentration (NBase) of the germanium substrate was 1 × 10 ¹⁸ cm ^-3 , and tantalum (Ta) whose work function (WF) was 4.6 V was used as a gate electrode. In Fig. 7, a drain voltage Vd of 1 V is applied to the drain.

The curves C6 and C7 shown in Fig. 7 show the characteristics when the thickness of the insulating layer (TBOX) is 12 nm, and the curves C8 and C9 indicate the characteristics when the thickness of the insulating layer (TBOX) is 15 nm. Further, curves C6 and C8 indicate characteristics when the impurity concentration (Nsub) of the SOI layer is 5 × 10 ¹⁷ cm ^-3 , and curves C7 and C9 indicate that the impurity concentration (Nsub) of the SOI layer is 2 × 10 ¹⁷ cm ^{-3 .} Characteristics of time.

Comparing the curves C6 and C7 with the curves C8 and C9, it is found that when the thickness of the embedded insulating layer (TBOX) is constant, the higher the impurity concentration (Nsub) of the SOI layer, the lower the lower gate voltage Vg. Large bungee current Id. On the other hand, when the impurity concentration (Nsub) of the SOI layer is constant, the thicker the thickness of the embedded insulating layer (TBOX), the larger the current.

Therefore, the threshold voltage can be controlled by adjusting the impurity concentration (Nsub) of the SOI layer or adjusting the thickness of the embedded insulating layer (TBOX).

Next, a specific example of the semiconductor device according to the present invention will be described with reference to FIG. In the semiconductor device shown in the drawing, an accumulation type NMOS transistor in which an SOI layer 22 formed by interposing an insulating layer 24 is interposed on a P-type germanium substrate 20 is used, in which a thickness is formed on the surface of the P-type germanium substrate 20 (TBOX). ) is an embedded insulating layer 24 composed of SiO ₂ of 12 nm. Further, in the P-type germanium substrate 20, ions are implanted to dope impurities via the embedded insulating layer 24, and the surface impurity concentration (Nbase) thereof is adjusted to 1 × 10 ¹⁸ cm ^-3 . That is, the semiconductor device shown in the figure is manufactured by additionally adding a step of implanting ions via the embedded insulating layer 24.

On the other hand, the SOI layer 22 is an N-type layer of a reverse conductivity type with a germanium substrate 20 having a thickness (TSOI) of 15 nm, and a source region 221, a drain region 222, and a channel region 223 are formed on the SOI layer 22. . The impurity concentration (Nsub) of the channel region 223 is 2×10 ¹⁷ cm ⁻³ , and the source region 221 and the drain region 222 have an impurity concentration higher than that of the channel region 223 . Further, the effective length (Leff) and width (W) of the channel region 223 are 45 nm and 1 μm, respectively.

Further, a gate insulating film 26 having an SiO ₂ equivalent thickness (EOT) of 1 nm is formed on the channel region 223, and the gate insulating film 26 is provided with a gate electrode 28 which has a work function (WF) of 4.6. Formed by the Ta material of V. The length (L) of the gate electrode 28 is 0.045 nm, and the width (W) is 1 μm. Further, the embedded insulating layer 24 may be composed of other materials such as Si ₃ N _{4 having an} EOT of 12 nm.

The cumulative NMOS transistor shown in FIG. 8 exhibits a gate voltage-drain current characteristic as shown by a curve C1 in FIG. 6, and therefore, a work function (WF) can be used to form a gate electrode with a lower Ta to form a gate electrode. 28, the result is that a transistor with a lower threshold voltage is obtained. Thus, the NMOS transistor shown in the figure can also be applied to a circuit having a low voltage source.

The embodiment described above is described only for the accumulation type NMOS transistor, but can also be applied to the accumulation type PMOS transistor.

In addition, if the present invention is applied to the n- and P-channel inversion MOS transistors shown in FIGS. 1(c) and (d), by controlling the thickness of the BOX layer, the impurity concentration of the substrate, and the impurity concentration of the SOI layer, The depletion layer of the channel region of the SOI layer is controlled from below to adjust the threshold voltage. That is, the substrate bias effect caused by the substrate impurity concentration can be utilized.

Industrial use possibility

In the present invention, only a single accumulation type MOS transistor is described, and different accumulation type MOS transistors whose conductivity type is opposite may be combined to form a CMOS. The present invention is also applicable to an inverse MOS transistor. Or in a combination of an accumulation type MOS transistor and an inverse type MOS transistor, the present invention is applied to one or both of them.

20. . . P-type germanium substrate

twenty two. . . SOI layer

twenty four. . . Embedded insulation

26. . . Gate insulating film

28. . . Gate electrode

221. . . Source area

222. . . Bungee area

223. . . Channel area

1(a), (b), (c), and (d) are schematic views showing the structural cross sections of the NMOS and PMOS transistors to which the present invention is applied, respectively.

(a), (b), (c) and (d) of Fig. 2 illustrate the principle of operation of the NMOS transistor according to the present invention.

(a) and (b) of Fig. 3 illustrate the relationship between the energy band structure and the cross section in the cumulative NMOS transistor.

Figure 4 illustrates an energy band configuration diagram in a conventional transistor.

Fig. 5 is a view showing the energy band structure of the transistor of the present invention.

Fig. 6 is a graph showing changes in gate voltage (Vg) - drain current (Id) characteristics when the thickness of the embedded insulating layer (TBOX) and the impurity concentration in the germanium substrate are changed.

Fig. 7 is a graph showing changes in gate voltage (Vg) - drain current (Id) characteristics when the impurity concentration (Nsub) in the SOI layer and the thickness (TBOX) of the embedded insulating layer are changed.

Figure 8 is a cross-sectional view showing the configuration of a cumulative NMOS transistor in accordance with an embodiment of the present invention.

20. . . P-type germanium substrate

twenty two. . . SOI layer

twenty four. . . Embedded insulation

26. . . Gate insulating film

28. . . Gate electrode

221. . . Source area

222. . . Bungee area

223. . . Channel area

Claims (8)

A semiconductor device formed by a substrate including at least a first semiconductor region, an embedded insulating layer formed over the first semiconductor region, and a second semiconductor region formed over the embedded insulating layer, At least a portion of the second semiconductor region is a channel region, and has a gate insulating film and a gate electrode on the channel region, wherein when the thickness of the embedded insulating layer is 20 nm or less, at least An impurity concentration of the first semiconductor region to control a threshold voltage of the transistor; a thickness of the depletion layer having the channel region depends on a thickness of the embedded insulating layer and an impurity concentration of the first semiconductor region; the semiconductor device is often Off type. The semiconductor device of claim 1, further comprising a source region and a drain region electrically connected to the channel region, wherein at least a portion of the gate electrode is used to have a different work function from the channel region The material is formed, and the thickness of the depletion layer in the channel region is determined by adjusting a difference in work function between the gate electrode and the channel region, an impurity concentration of the first semiconductor region, and a thickness of the embedded insulating layer. . The semiconductor device of claim 2, wherein the threshold voltage is less than a threshold voltage determined by a difference in work function between the gate electrode and the channel region. The semiconductor device of claim 1, wherein the first semiconductor region and the second semiconductor region are opposite conductivity types. The semiconductor device of claim 4, wherein the channel region, the source region, and the drain region are of a cumulative type of the same conductivity type. The patent application range of the semiconductor device, Paragraph 1, wherein the impurity concentration of the second semiconductor region of not less than 1 × 10 ¹⁷ cm ^-3. The semiconductor device of claim 1, wherein the thickness of the embedded insulating layer satisfies the following formula: 0.56T _SOI <T _BOX <0.85T _SOI , wherein T _BOX refers to the EOT, T _SOI embedded in the insulating layer. Means the thickness of the second semiconductor region. The semiconductor device according to claim 7, wherein when the power supply voltage is applied to the drain region and the gate electrode is 0 V, the source region side end portion of the channel region is depleted in the thickness direction as a whole.