TWI453617B - System and method for layout of a circuit - Google Patents

Description

Circuit wiring system and method

The present invention relates to a wiring system and method, and more particularly to a circuit wiring system and method.

With the development of electronic science and technology, Printed Circuit Board (PCB) has become an indispensable part of various electrical equipment (such as computers). Since the ultra-high frequency microwave signal is transmitted in the circuit of the PCB, in order to ensure the reliability of the PCB during use, the characteristic impedance of the signal trace must be detected at the factory. The characteristic impedance refers to the impedance of the electronic signal trace infinitely long, and the unit is ohm.

In the past, the traditional detection method requires the staff to confirm the status of the test equipment one by one before the test. The test parameters need to be manually input one by one. Because of the wide range of detection and many functions, it is often too busy to be tested, not only labor intensity, but also labor intensity. The work efficiency is low, and human error is easy to occur, and the detected data is not easy to manage.

In view of the above, it is necessary to provide a circuit wiring system and method to achieve optimal circuit wiring.

A circuit cabling system running on a computer, the computer providing a graphical user interface for displaying a circuit wiring diagram of a circuit board to be tested, the circuit wiring diagram having the absolute coordinates of all components on the circuit board to be tested Value, the system includes: a database connected to the computer for storing circuit design specifications and circuit wiring result reports; an execution module for finding all high frequencies of the pulse width modulation controller on the circuit board to be tested a calculation module for calculating an absolute coordinate value of a common source pin of the FET and a capacitance pin connecting the FET when the component to which the high frequency pin is connected is a field effect transistor Absolute coordinate value, calculate the straight line distance between the common source pin and the capacitor pin of the FET, and also calculate the common source pin of the FET according to the trace between the FET and the capacitor The distance between the line and the capacitor pin; the judging module is used to judge whether the capacitance value of the capacitor matches when the straight line distance and the line trace distance meet the circuit design specifications in the data library. Circuit design specifications; and the execution module is further configured described wiring where the results are reported to the wiring circuit according to the determination result.

A circuit wiring method, the method comprising the steps of: providing a graphical user interface, displaying a circuit wiring diagram of a circuit board to be tested, and marking an absolute coordinate value of all components on the circuit board to be tested; providing a database, a storage circuit design specification And circuit wiring result report; find all high frequency pins of the pulse width modulation controller on the circuit board to be tested; when the high frequency pin connected component is a field effect transistor, according to the common source of the effect transistor The absolute coordinate value of the pin and the absolute coordinate value of the capacitor pin connected to the FET, calculate the straight line distance between the common source pin and the capacitor pin of the FET; according to the line between the FET and the capacitor Trace the line to calculate the line trace distance between the common source pin and the capacitor pin of the FET; when the straight line distance and the line trace distance meet the circuit design specification, determine the capacitance value of the capacitor Whether the circuit design specification is met; and the circuit wiring condition is described in the circuit wiring result report according to the judgment result.

Compared with the prior art, the circuit wiring system and method quickly and conveniently design a circuit board, which saves a lot of working time and improves work efficiency.

1 and 2 are operational environment diagrams of a preferred embodiment of the circuit wiring system of the present invention. The circuit wiring system 100 runs on a computer 1, which is connected to a database 2. In this embodiment, the computer 1 provides a graphical user interface (GUI) 101 for displaying the circuit layout of the circuit board 102 to be tested stored in the database 2.

The circuit board 102 to be tested is mounted with a plurality of DC-DC converters 103. Each DC-DC converter 103 includes a pulse width modulation (PWM) controller 104 and a plurality. Element 105 (only one is shown in Figure 1). The PWM controller 104 has a plurality of pins (not shown) including, but not limited to, a high side pin and a low side pin. Wait. Each pin of the PWM controller 104 is connected to the pin of an element 105 via a line (net), and the element 105 is also connected to the other element 105 via the net. The component 105 includes a capacitor, a resistor, a metal oxide semiconductor field effect transistor (abbreviation: field effect transistor), and the like. Each FET has a driver side that acts as a power supply input to the FET, where each common source includes a driver pin.

In addition, the database 2 is also used to store the coordinate values of all the components 105 on the circuit board 102 to be tested, and the coordinate values are absolute coordinate values. The GUI 101 labels the absolute coordinate values of each of the elements 105 on the displayed circuit layout map based on the contents stored in the database 2. If the user enters a coordinate value on the GUI 101, the circuit wiring system 100 can find the component 105 corresponding to the input coordinate value from the circuit layout. The data base 2 also stores a circuit design specification and a circuit wiring result report of the circuit board 102 to be tested. The circuit design specification describes the range of distance between the common source pin of the FET in the circuit design and the capacitor pin connected to the FET, and the capacitance range of each capacitor. The circuit wiring result report is used to record whether the wiring of each line is successful after the wiring is completed.

As shown in FIG. 3, it is a functional module diagram of the circuit wiring system 100 in FIG. The circuit cabling system 100 includes an execution module 10, a determination module 12, a generation module 14, a calculation module 16, and a storage module 18. The module is a software program segment having a specific function, and the software is stored in a computer readable storage medium or other storage device, and can be executed by a computer or other computing device including a processor, thereby completing a series of processes for circuit wiring.

The execution module 10 is used to find all the high frequency pins of the PWM controller 104 and number the high frequency pins that are found. The execution module 10 starts to find the first component 105 to which the Xth high frequency pin is connected according to the number. In the preferred embodiment, the initial value of X is 0.

The determining module 12 is configured to determine whether the first component 105 connected to the Xth high frequency pin is a FET. If the first component 105 to which the X-th high-frequency pin is connected is not a FET, the execution module 10 searches for the second component 105 to which the first component 105 is connected, and the determining module 12 determines the connection. Whether the second component 105 is a field effect transistor, if the second component 105 is not a field effect transistor, the execution module 10 searches for the third component 105 connected to the second component 105, and so on, until all are found Field effect tube.

The generating module 14 is configured to establish a relative Cartesian coordinate system when the found component 105 is a FET, and use the geometric center position of the FET as a coordinate origin, and record the common source pin of the FET in the relative Relative coordinate values in a Cartesian coordinate system.

The calculation module 16 is configured to calculate the common source pin according to the relative coordinate value of the common source pin and the absolute coordinate value of the geometric center position of the FET (hereinafter referred to as: the absolute coordinate value of the FET) Absolute coordinate value. As shown in FIG. 6, the lower left corner of the circuit board 102 to be tested is the coordinate origin (0, 0) of the absolute coordinate system, and the absolute coordinate value of the field effect transistor a on the circuit board 102 to be tested is (x0, y0). The generating module 14 establishes a relative rectangular coordinate system with the (x0, y0) point as a coordinate origin, and the relative coordinate value of the common source pin b on the FET a is (x1, y1). The calculation module 16 calculates an absolute coordinate value of the common source pin b (x1+x0, y1+y0).

The execution module 10 is also used to find all capacitors connected to the common source of the FET.

The generating module 14 is further configured to establish a relative Cartesian coordinate system with the center position of each capacitor sought as a coordinate origin, and record the relative coordinate values of the pins of each capacitor in the relative Cartesian coordinate system.

The calculation module 16 is further configured to calculate an absolute coordinate value of the capacitor pin according to a relative coordinate value of the capacitor pin and an absolute coordinate value of the capacitor, and the calculation method is similar to the absolute value of the common source pin. Coordinate value calculation method. The calculation module 16 is further configured to calculate a straight line between the common source pin and the capacitor pin of the FET according to the absolute coordinate value of the common source pin of the FET and the absolute coordinate value of the capacitor pin. Segment distance. The calculation module 16 is further configured to calculate a line trace distance between the common source pin and the capacitor pin of the FET according to the trace of the line between the FET and the capacitor.

The storage module 18 is configured to store a straight line segment distance and a line trace distance between the common source pin and the capacitor pin of the calculated FET.

The determining module 12 is further configured to determine whether a straight line segment distance between the common source pin and the capacitor pin of the stored FET and the line trace distance meet the circuit design specification. If the straight line segment distance between the common source pin and the capacitor pin of the FET and the line trace distance meet the circuit design specification, the determining module 12 is further configured to determine each of the FETs connected Whether the capacitance value of the capacitor meets the circuit design specifications.

The execution module 10 is further configured to record that the circuit routing is successful in the circuit wiring result report when the capacitance value of the capacitor meets a design specification. On the contrary, the execution module 10 records that the circuit wiring fails in the circuit wiring result report.

4 and 5 are flow charts of a preferred embodiment of the circuit wiring method of the present invention.

In step S30, the execution module 10 searches all the high frequency pins of the PWM controller 104 and numbers the searched high frequency pins.

In step S31, the execution module 10 searches for the component 105 connected to the Xth high frequency pin according to the number. In the preferred embodiment, the initial value of X is 0.

In step S32, the determining module 12 determines whether the found component 105 is a FET. If the found component 105 is not a field effect transistor, the process proceeds to step S33. If the found component 105 is a field effect transistor, then step S34 is reached.

In step S33, the execution module 10 searches for other components connected to the component 105, and proceeds to step S32.

In step S34, the generating module 14 uses the center of the FET as a coordinate origin to establish a relative rectangular coordinate system, and records the relative coordinate value of the common source pin of the FET in the relative Cartesian coordinate system.

In step S35, the calculation module 16 calculates the absolute coordinate value of the common source pin according to the relative coordinate value of the common source pin and the absolute coordinate value of the FET, and the calculation method is as shown in FIG. 5 .

In step S36, the execution module 10 searches for all the capacitances of the common source connection of the FET.

In step S37, the generating module 14 uses the center position of each capacitor sought as a coordinate origin to establish a relative rectangular coordinate system, and records the relative coordinate values of the pins of each capacitor in the relative Cartesian coordinate system.

Step S38, the calculation module 16 calculates an absolute coordinate value of the capacitor pin according to a relative coordinate value of the capacitor pin and an absolute coordinate value of the capacitor.

Step S39, the calculation module 16 calculates a line trace distance between the common source pin and the capacitor pin of the FET according to the trace of the line between the FET and the capacitor, and according to the FET The absolute coordinate value of the common source pin and the absolute coordinate value of the capacitor pin calculate the straight line distance between the common source pin and the capacitor pin of the FET.

In step S40, the storage module 18 stores the calculated straight line distance between the common source pin and the capacitor pin of the FET and the line trace distance, and between the common source pin and the capacitor pin of the FET. The straight line distance.

In step S41, the determining module 12 determines whether the straight line distance between the common source pin and the capacitor pin of the stored FET and the line trace distance meet the circuit design specification. If the straight line segment distance between the common source pin and the capacitor pin of the FET and the line trace distance meet the circuit design specification, the process proceeds to step S42. If the straight line segment distance between the common source pin and the capacitor pin of the FET and the line trace distance do not conform to the circuit design specification, the process proceeds to step S44.

In step S42, the determining module 12 determines whether the capacitance value of each capacitor connected to the FET complies with the circuit design specification. If the capacitance value of each capacitor connected to the FET is in accordance with the circuit design specification, the process proceeds to step S43. If the capacitance value of the capacitor connected to the FET does not conform to the circuit design specification, the process proceeds to step S44.

In step S43, the execution module 10 records the circuit wiring success in the circuit wiring result report.

In step S44, the execution module 10 records the circuit wiring failure in the circuit wiring result report.

It should be noted that the above embodiments are only intended to illustrate the technical solutions of the present invention and are not intended to be limiting, and the present invention will be described in detail with reference to the preferred embodiments thereof The technical solutions are modified or equivalently substituted without departing from the spirit and scope of the technical solutions of the present invention.

1‧‧‧ computer

2‧‧‧Database

100‧‧‧Circuit wiring system

101‧‧‧ graphical user interface

102‧‧‧Device board to be tested

103‧‧‧DC-DC converter

104‧‧‧ Pulse width modulation controller

105‧‧‧ components

10‧‧‧Execution module

12‧‧‧Judgement module

14‧‧‧Generation module

16‧‧‧Computation Module

18‧‧‧ storage module

1 and 2 are diagrams showing an operating environment of a preferred embodiment of the circuit wiring system of the present invention.

3 is a functional block diagram of the circuit cabling system 100 of FIG.

4 and 5 are flow charts of a preferred embodiment of the circuit wiring method of the present invention.

6 is a schematic diagram showing the relative coordinate values of the common source pins of the field effect transistor of the present invention.

10‧‧‧Execution module

12‧‧‧Judgement module

14‧‧‧Generation module

16‧‧‧Computation Module

18‧‧‧ storage module

Claims (10)

A circuit cabling system running on a computer, the computer providing a graphical user interface for displaying a circuit wiring diagram of a circuit board to be tested, the circuit wiring diagram having the absolute coordinates of all components on the circuit board to be tested Value, the system includes:
a database connected to the computer for storing circuit design specifications and circuit wiring result reports;
An execution module for finding all high frequency pins of the pulse width modulation controller on the circuit board to be tested;
a calculation module, configured to: when the component connected to the high frequency pin is a field effect transistor, according to an absolute coordinate value of the common source pin of the FET and an absolute coordinate value of a capacitor pin connected to the FET Calculate the straight line distance between the common source pin and the capacitor pin of the FET. It is also used to calculate the common source pin and capacitor lead of the FET according to the trace between the FET and the capacitor. The distance between the lines of the feet;
The determining module is configured to determine whether the capacitance value of the capacitor meets the circuit design specification when the straight line segment distance and the line trace distance meet the circuit design specification in the database; and the execution module is further used for The circuit wiring is described in the circuit wiring result report based on the judgment result. The circuit wiring system of claim 1, wherein the execution module is further configured to: when the component connected to the high frequency pin is not a field effect transistor, look for a component to which the component is connected. The circuit cabling system of claim 1, wherein the system further comprises:
Generating a module for establishing a relative Cartesian coordinate system with the center point of the FET as a coordinate origin, and recording a relative coordinate value of the common source pin of the FET in a relative Cartesian coordinate system;
The calculation module is further configured to calculate an absolute coordinate value of the common source pin according to a relative coordinate value of the common source pin and an absolute coordinate value of the FET;
The generating module is further configured to use a center position of each capacitor connected by the FET as a coordinate origin, respectively establish a relative rectangular coordinate system, and record relative coordinates of the pins of each capacitor in the relative Cartesian coordinate system. And the computing module is further configured to calculate an absolute coordinate value of the capacitor pin according to a relative coordinate value of each capacitor pin and an absolute coordinate value of the capacitor. The circuit cabling system of claim 1, wherein the execution module is further configured to: when the capacitance value of the capacitor meets a circuit design specification, record the circuit wiring success in the circuit wiring result report; When the capacitance value of the capacitor does not conform to the circuit design specification, the circuit wiring failure is described in the circuit wiring result report. The circuit wiring system according to claim 1, wherein the execution module is further configured to record the circuit wiring in the circuit wiring result report when a straight line segment distance and a line trace distance do not meet a circuit design specification. failure. A circuit wiring method, the method comprising the following steps:
(a) providing a graphical user interface, displaying the circuit layout of the circuit board to be tested and marking the absolute coordinate values of all components on the circuit board to be tested;
(b) Provide a database, storage circuit design specifications and circuit wiring results report;
(c) Find all high frequency pins of the pulse width modulation controller on the circuit board to be tested;
(d) When the component to which the high frequency pin is connected is a field effect transistor, the field effect is calculated according to the absolute coordinate value of the common source pin of the effect transistor and the absolute coordinate value of the capacitance pin connected to the FET The straight line distance between the common source pin and the capacitor pin of the tube;
(e) calculating a line trace distance between the common source pin and the capacitor pin of the FET according to the trace of the line between the FET and the capacitor;
(f) when the straight line segment distance and the line trace distance meet the circuit design specification, determine whether the capacitance value of the capacitor conforms to the circuit design specification; and (g) record the circuit in the circuit wiring result report according to the judgment result Wiring situation. The circuit wiring method according to claim 6, wherein the method further comprises: when the component to which the high frequency pin is connected is not a field effect transistor, look for a component to which the component is connected. The circuit wiring method according to claim 6, wherein the method further comprises: before step (d):
Establishing a relative Cartesian coordinate system with the center point of the FET as the coordinate origin, and recording the relative coordinate value of the common source pin of the FET in a relatively Cartesian coordinate system;
Calculating an absolute coordinate value of the common source pin according to a relative coordinate value of the common source pin and an absolute coordinate value of the FET;
The center position of each capacitor connected by the FET is a coordinate origin, respectively establishing a relative Cartesian coordinate system, and recording the relative coordinate values of the pins of each capacitor in the relative Cartesian coordinate system; and according to each capacitance pin Calculate the absolute coordinate value of the capacitor pin by the relative coordinate value and the absolute coordinate value of the capacitor. The circuit wiring method according to claim 6, wherein the method further comprises:
When the capacitance value of the capacitor conforms to the circuit design specification, the circuit wiring is successfully recorded in the circuit wiring result report; and when the capacitance value of the capacitor does not conform to the circuit design specification, in the circuit wiring result report It is stated that the circuit wiring failed. The circuit wiring method according to claim 6, wherein the method further comprises: when the straight line segment distance and the line trace distance do not conform to the circuit design specification, the circuit wiring failure is recorded in the circuit wiring result report.