TWI452691B - Semiconductor structure and method for making the same, and method for forming epitaxial semi-finished product - Google Patents

Description

Semiconductor structure, manufacturing method thereof and manufacturing method of epitaxial semi-finished product

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure, a method of fabricating the same, and a method of fabricating an epitaxial semi-finished product.

Referring to FIG. 1 , a conventional epitaxial device having photovoltaic characteristics includes an epitaxial substrate 111 composed of gallium arsenide (GaAs) as a main material and which is easy to epitaxially grow a thin film, and is formed by epitaxy. An epitaxial film 112 on the epitaxial substrate 111, and an electrode 113 formed on a top surface of the epitaxial film 112, the electrode 113 can transfer externally supplied electric energy to the epitaxial film 112. The mode of action of converting electrical energy into light energy or converting light energy into electrical energy.

For example, as a solar cell, light is absorbed by the top surface of the epitaxial film 112 away from the epitaxial substrate 111, and a photoelectric effect is generated in the epitaxial film 112 to convert light energy into electric energy. Since the epitaxial film 112 needs to absorb light energy and transmit electric energy as much as possible in the process of photoelectric conversion, the epitaxial substrate 111 dissipates waste heat energy. Therefore, the epitaxial substrate 111 of the epitaxial element needs to have The light that has penetrated the epitaxial film 112 and reaches the epitaxial substrate 111 is reflected to the epitaxial film 112 for absorption by the epitaxial film 112, and the excess heat is dissipated; in reality, the arsenic is used. Although the epitaxial substrate 111 made of gallium (GaAs) is easily grown by the epitaxial film 112, it is a material that does not easily dissipate heat.

Referring to FIG. 2 , the current epitaxial film is mostly separated from the epitaxial substrate 111 and connected to a permanent substrate 121 . The current epitaxial element includes a permanent substrate 121 composed of a material having a heat dissipation effect, an epitaxial film 122 formed on the permanent substrate 121, and a sandwich between the permanent substrate 121 and the epitaxial film 122. The polymer glue 123 which closely bonds the two, and an electrode 124 formed on a part of the exposed surface of the epitaxial film 122 and capable of transmitting electric energy to the outside.

The light is irradiated from the top surface of the epitaxial film 122, and part of the light is directly absorbed by the epitaxial film 122, and part of the light passes through the epitaxial film 122 to the polymer gel 123 and the permanent substrate 121, and is utilized. The difference in refractive index between the polymer paste 123 and the epitaxial film 122 forms a total reflection effect, and the light is reflected to the epitaxial film 122, and the remaining light is absorbed by the epitaxial film 122 by the reflection of the permanent substrate 121. However, since the refractive index of the polymer gel 123 is easily affected by external environmental factors such as temperature and humidity, the total light reflection effect through the polymer gel 123 is unstable, and the polymer gel 123 is a poor heat conductive material. Even if the permanent substrate 121 is composed of a material having good heat dissipation effect, the heat of the epitaxial film 122 cannot be efficiently transmitted to the permanent substrate 121 via the polymer gel 123 to achieve a desired heat dissipation effect.

The inventors of the present invention have developed an epitaxial element which can be obtained without a polymer glue in order to solve the problem of poor heat dissipation and high environmental resistance of the polymer paste connecting the permanent substrate 121 and the epitaxial film 122.

Referring to FIG. 3, the epitaxial element includes an epitaxial film 131, a permanent substrate 132 directly formed on the bottom surface of the epitaxial film 131 and having a heat dissipation effect on a metal as a main material, and a top surface formed on the epitaxial film 131. Surface electrode 133.

Referring to FIG. 4 and FIG. 5, the epitaxial element is prepared by first preparing an epitaxial substrate 134, and then sequentially forming an epitaxial substrate on the epitaxial substrate 134 for etching in a subsequent process. The second layer body 135, and a first layer body 136 which can produce a photoelectric conversion effect, wherein the etching rate ratio between the second layer body 135 and the first layer body 136 is high. Continuing on the top surface of the first layer body 136, a top surface covering a portion of the first layer body 136 is formed by, for example, sputtering or thermal evaporation, and is arranged in a plurality of intervals to define each epitaxial element. The epitaxial film 131 is bottomed on the bottom layer 137 of the block 138, and the first layer body 136 exposed outside the underlying layer 137 is etched to become a semiconductor structure as shown in FIGS. 4 and 5. Referring to FIG. 3, the underlying layer 137 is used as a seed to be plated up to a plurality of spaces and formed on the top surface of the first layer body 136 and defined as the epitaxial film 131, thereby becoming a permanent substrate. 132.

Then, the second layer body 135 is completely etched by wet etching, and the epitaxial substrate 134 is separated from the first layer body 136. At this time, the epitaxial film 131 formed by the first layer body 136, and The permanent substrate 132 formed by the plating of the underlayer 137 is formed into a plurality of independent epitaxial semi-finished products (not shown). In order to gather the epitaxial semi-finished products without fail, a blue tape is adhered to the top surface of the permanent substrate 132 to etch each epitaxial semi-finished product before etching the second layer body 135.

Finally, the blue gel on the top surface of the permanent substrate 132 of the epitaxial semi-finished product is removed, and an electrode 133 is formed on the top surface of the epitaxial film 131 to form an epitaxial element as shown in FIG. That is, in many conventional epitaxial elements, the epitaxial film 131 is separated from the epitaxial substrate 134 and then connected to the permanent substrate 132.

If the epitaxial element fabricated in the above manner is in an ideal state, the underlying layer 137 in the semiconductor structure during fabrication is a metal material having heat dissipation characteristics, and the permanent substrate 132 is formed by electroplating. The underlying layer 137 is directly thickened, and the conventional permanent substrate 132 is additionally fixed by polymer bonding to the epitaxial film 131, which can reduce the heat dissipation of the polymer paste and cause waste heat energy of the epitaxial element. The bottleneck that cannot be dissipated.

However, the inventors have found that the underlying block 138 of the underlying layer 137 is independently formed on the top surface of the first layer body 136 when forming the semiconductor structure in an actual process, regardless of the underlying layer. The state of 137 or the thickening of the underlayer 137 to the permanent substrate 132 is easy due to uneven application of force, or poor adhesion between the spacers 138 and the epitaxial film 131. The periphery of the bottom block 138 (or permanent substrate 132) begins to deform and warp. Therefore, the epitaxial element fabricated by the semiconductor structure is susceptible to incomplete bonding between the permanent substrate 132 and the epitaxial film 131, resulting in an overall component yield being low, and the epitaxial element is accumulated in the operation. The waste heat of the epitaxial film 131 is also difficult to dissipate from the permanent substrate 132, thereby reducing the heat dissipation effect of the permanent substrate 132, resulting in a decrease in reliability and service life of the epitaxial element.

In addition, the use of blue glue to fix each of the individual epitaxial semi-finished products, and then to remove the blue gel before forming the electrode 133, also causes waste of consumable resources, and the attachment and removal of the blue glue also increases the cycle time.

Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor structure that enhances the yield of the epitaxial element without warping the underlayer during the process.

Secondly, another object of the present invention is to provide a semiconductor structure having a bottom layer that does not warp and which enhances the yield of the epitaxial element.

Furthermore, another object of the present invention is to provide a method for fabricating an epitaxial semi-finished product with improved yield.

Therefore, the method for fabricating the semiconductor structure of the present invention comprises an epitaxial substrate preparation step, an epitaxial layer unit forming step, and a bottom layer forming step.

The substrate preparation step for epitaxy is to prepare an epitaxial substrate.

The epitaxial layer unit forming step is to form an epitaxial layer unit by epitaxial-first layer body on the epitaxial substrate.

The underlayer forming step is to form an underlayer on the first layer body defining a plurality of etched trace patterns, the underlayer comprising a plurality of bottom regions spaced apart from each other and regularly arranged, and a plurality of connection regions, each connection a region connecting corners of the adjacent regions adjacent to each other, the top surface of the epitaxial layer unit and the bottom region of the underlying layer and the connection region collectively defining a plurality of predetermined divisions of the epitaxial layer unit to correspond to the plurality The etching channel of the epitaxial film of the bottom region.

In addition, the semiconductor structure of the present invention comprises a substrate for epitaxy, and a body.

The main body includes an epitaxial layer unit and a bottom layer, the epitaxial layer unit has a first layer body formed upward from the epitaxial substrate, and the bottom layer is formed on the top surface of the first layer body. And comprising a plurality of spaced apart and regularly arranged bottom regions, and a plurality of connecting regions, each connecting region connecting corners of adjacent bottom regions, the top surface of the epitaxial layer unit and the bottom region of the bottom layer Cooperating with the connection region defines a plurality of etched tracks which are predetermined to divide the epitaxial layer unit into a plurality of epitaxial films respectively corresponding to the underlying regions.

Finally, the method for fabricating the epitaxial semi-finished product of the present invention comprises a semiconductor structure process and a molding separation process.

The semiconductor structure process includes an epitaxial substrate preparation step for preparing an epitaxial substrate, and an epitaxial layer unit forming step, wherein the epitaxial substrate preparation step is to prepare an epitaxial substrate, the epitaxial layer The unit forming step sequentially forms a second layer body and a first layer body on the epitaxial substrate to form an epitaxial layer unit, and the underlayer forming step is the first Forming an underlayer on the layer body defining a plurality of etched trace patterns, the underlayer comprising a plurality of bottom regions spaced apart from each other and regularly arranged, and a plurality of connection regions, each of the connection regions connecting the corners of the adjacent regions adjacent to each other The top surface of the epitaxial layer unit and the bottom region of the underlying layer and the connection region together define a plurality of etched tracks that are predetermined to divide the epitaxial layer unit into a plurality of epitaxial films respectively corresponding to the underlying regions.

The molding separation process includes an etching enhancement track forming step, an electroplating thickening layer forming step, and an epitaxial substrate separating step, wherein the etching reinforcing track forming step is to remove the semiconductor structure correspondingly exposed to the underlying layer An outer first layer structure, wherein the first layer structure under the underlayer that is not removed, the top surface of the second layer, and the bottom region of the bottom layer are jointly defined with the connection region a predetermined step of dividing the epitaxial layer unit into an etch enhancement track respectively corresponding to the epitaxial films of the underlying regions, the etching enhancement track having a depth greater than the etching track, the plating thickening layer forming step of the underlying layer Forming a plating thickening layer having a thermal conductive property, the substrate separating step of the epitaxial layer is to remove the second layer body, and separating the epitaxial crystal plate from the first layer body of the epitaxial layer unit. Most of the epitaxial semi-finished products.

The effect of the invention is that the corner joint of the bottom layer adjacent to the bottom layer is pinned by the connecting layer of the bottom layer to avoid the warp of the isosceles, and is attached to the bottom of the epitaxial layer flatly The layer is used to improve the heat dissipation effect and yield of the epitaxial element formed by the semiconductor structure.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.

Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 3, FIG. 6, and FIG. 7, a preferred embodiment of the method for fabricating an epitaxial semi-finished product of the present invention sequentially includes a semiconductor structure process 21 and a molding and separation process 22, wherein the semiconductor structure process 21 is sequentially followed. An epitaxial substrate preparation step 211, an epitaxial layer unit formation step 212, and an underlayer formation step 213 are performed, and the semiconductor structure 3 as shown in FIG. 7 is first formed, and the molding separation process 22 is sequentially included. An etching enhancement track forming step 221, an electroplating thickening layer forming step 222, and an epitaxial substrate separating step 223, to produce an epitaxial semi-finished product 4 as shown in FIG. 13, and then cooperating with the epitaxial semi-finished product 4 performing a step of dividing and forming the electrode 23, thereby forming an epitaxial element as shown in FIG. 3, which can solve the underlying layer warpage of the permanent substrate which occurs when the epitaxial element is currently produced, resulting in yield and heat dissipation. Poor effect.

Referring to FIGS. 6 and 8, when the semiconductor structure process 21 is performed, the epitaxial substrate preparation step 211 is performed to prepare an epitaxial substrate 31 made of gallium arsenide (GaAs) as a main material.

Then, the epitaxial layer unit forming step 212 is performed, and a second layer body 324 is sequentially formed on the epitaxial substrate 31 in an epitaxial manner, and a first layer body 323, the first layer and the second layer body 323. 324 is collectively defined as an epitaxial layer unit 321, and the ratio of etching selectivity between the second layer body 324 and the first layer body 323 is high; taking hydrofluoric acid (HF) as an etching liquid as an example, the second layer The etching rate of the body 324 is much larger than the etching rate of the first layer body 323.

Referring to FIG. 6 and FIG. 7 , the bottom layer forming step 213 is continued. First, a bottom preparation layer (not shown) is formed on the top surface of the first layer body 323 by deposition, and then processed by a yellow light lithography process. The bottom surface of the preparation layer defines a region where the underlayer 325 is to be formed, and then a portion of the underlying layer is removed to form a primer layer 325, thereby fabricating the semiconductor structure 3.

Referring to FIG. 7, the underlying layer 325 of the semiconductor structure has a plurality of regularly arranged base regions 327 formed on the top surface of the first layer body 323 and having a square shape, and a plurality of connection regions 328 each having a base portion 329 and four extensions 330. The base portion 329 is located at the center of the four adjacent bottom regions 327, and the four extension portions 330 of each of the connection regions 328 are respectively connected to the corners of the four adjacent bottom regions 327, and the adjacent two extending portions 330 are vertically predetermined. The angle is sandwiched. At this time, the top surface of the first layer body 323 exposed outside the bottom layer 325, the bottom regions 327, and the connection regions 328 define a plurality of etching tracks 33. The first layer body 323 is predetermined to be divided into a plurality of epitaxial films 131 (Fig. 3) respectively corresponding to the underlying regions 327.

The semiconductor structure 3 obtained at this time includes an epitaxial substrate 31 and a main body 32 formed on the epitaxial substrate 31.

The epitaxial substrate 31 is made of gallium arsenide (GaAs) as a main material, and a semiconductor material can be epitaxially formed on the epitaxial substrate 31, and a thin film is formed between the thin film and the epitaxial substrate 31. Matching, leveling, and good quality.

The body 32 includes an epitaxial layer unit 321 and a bottom layer 325. The epitaxial layer unit 321 has a second layer body 324 formed on the epitaxial substrate 31, and a first layer body 323 formed on the second layer body 324 in an epitaxial manner. The layer body 323 is composed of a gallium arsenide compound as a main material, and has photoelectric semiconductor characteristics in which light energy is converted into electric energy and electric energy is converted into light energy. The ratio of the etching selectivity between the second layer body 324 and the first layer body 323 is high, that is, the etching rate of the second layer body 324 for the etching liquid is much larger than the etching rate of the first layer body 323 for the etching liquid.

The first layer body 323 and the epitaxial substrate can be removed by removing the second layer body 324 as a sacrificial layer by the high etching selectivity of the second layer body 324 and the first layer body 323. 31 completely separated.

The underlayer 325 is formed on the first layer body 323, and is mainly made of metal and has heat dissipation characteristics. The underlayer 325 has a plurality of bottom regions 327 which are regularly arranged at intervals and are square, and A plurality of connection areas 328. The distance between the base regions 327 is equal. Each of the joint regions 328 has a base 329 at the geometric center of the four adjacent base regions 327, and four extension portions 330 respectively connecting the corners of the four adjacent base regions 327. Since the distances between the base regions 327 are equal, and the base portion 329 is located at the geometric center of the base regions 327, the extension portions 330 are all equal in length, and the two extension portions 330 of each of the bottom regions 327 are A predetermined clamping angle of 90° is interposed.

The top surface of the first layer body 323 of the epitaxial layer unit 321 cooperates with the bottom region 327 and the connection region 328 of the underlying layer 325 to define a plurality of etching tracks 33, and the etching channels 33 of the epitaxial layer unit 321 The first layer body 323 is predetermined to be divided into a plurality of epitaxial films 131 corresponding to the underlying regions 327 (Fig. 3). Since each of the connection regions 328 connects the adjacent bottom regions 327 by two or two vertical extensions 330, the defined etching lanes 33 are symmetrical hexagons.

In addition, the connecting portion 328 of the bottom layer 325 is connected to the corners of the adjacent bottom regions 327 by the extending portion 330, so that the bottom portion 327 formed on the first layer body 323 is formed by the extending portion 330 and The base 329 fixed between the adjacent four bottom regions 327 forms a corner that can symmetrically pin the corners of the base regions 327 to avoid warping away from the first layer body 323 to reach the epitaxial layer unit 321 The degree of adhesion to the underlayer 325 is a preferred effect.

It should be noted that, depending on the technology of the epitaxial element to be formed, the epitaxial layer unit 321 may include a plurality of first layer bodies 323, and is not the focus of the present invention here, so only the first layer body 323 is used. In summary.

Referring to FIG. 9, in particular, the bottom regions 327 may also be rectangular, and the distance between each of the rectangles is equal, and the extensions 330 of the bottom regions 327 adjacent to each other may be equal. Long and symmetrical, and two adjacent extensions 330 are sandwiched by a predetermined angle, such that the etched tracks 33 are hexagonal, and the extension 330 and the base 329 of the connection region 328 have and the connection region 328 The extension 330 and the base 329 have a pinning force that prevents the corners of the base region 327 from warping.

Referring to FIG. 6, after the semiconductor structure 3 (FIG. 7) is fabricated, the molding separation process 22 is performed to fabricate an epitaxial semi-finished product. Referring to FIG. 7 and FIG. 10, the etching enhancement track forming step 221 is first performed, and the underlying layer 325 is used as a hard mask for etching the epitaxial layer unit 321 exposed outside the underlying layer 325. Etching from the top surface of the first layer body 323 exposed outside the underlayer 325 to the remaining portion of the epitaxial substrate 31 to the remaining portion of the epitaxial layer unit 321 exposed outside the underlying layer 325 by dry etching The second layer body 324. The top surface of the exposed second layer body 324, the first layer body 323, and the underlying layer 325 define a plurality of etched reinforcement tracks 34 that are deeper than the etched track 33.

Referring to Figures 6, 10, and 11, then, the plating thickening layer forming step 222 is performed, in which the filling reinforcement 35 is filled with a filling material 35 to overflow the etching reinforcement track 34, and the overflowing filling material 35 is covered. The top surface of the underlying layer 325 around the etched reinforcement track 34 has a width of about 30 μm, and the filler 35 may be selected from the group consisting of photoresist, cerium oxide, and a combination thereof, as a material. In the example, the filler 35 is a photoresist, but should not be limited to photoresist. Referring to Figures 6, 12, thereafter, a top surface of the underlying layer 325 that is not covered by the filler 35 is electroplated to form an electroplated thickened layer 41 having high thermal conductivity characteristics, and the fill 35 is removed. The plating thickening layer 41 may also be made of a magnetic material, and the plating thickening layer 41 and the underlying layer 325 form a permanent substrate unit 40. After the plating thickening layer 41 is formed, a chemical solution is used, for example, Acetone removes the fill 35.

Referring to FIGS. 6 , 12 , and 13 , an epitaxial substrate separation step 223 is further performed, and the permanent substrate unit 40 , the epitaxial layer unit 321 , and the epitaxial substrate 31 are entirely immersed in, for example, a hydrofluoric acid liquid. The etchant has a higher ratio of etching selectivity to the etchant than the first layer 323, so that the etchant located in the etch pad 34 and the outer peripheral surface of the second layer 324 are transmitted. The etching solution etches the second layer body 324, and completely separates the second layer body 324 from the first layer body 323 of the epitaxial layer unit 321 , and then continues to adhere thereto by using an etching solution or a different chemical solution. The second layer body 324 on the epitaxial substrate 31 is completely etched to obtain a complete epitaxial substrate 31. The first layer body 323, the bottom layer 325 and the plating thickening layer 41 are combined to obtain a plurality of epitaxial semi-finished products 4; it is to be noted that if the plating thickening layer 41 has magnetic properties, the external plating may be provided by the external plating. The magnetic force on the thickening layer 41 attracts the plating thickening layer 41 to move the epitaxial semi-finished products 4 away from the epitaxial substrate 31, and since the epitaxial substrate 31 is not damaged, the epitaxial crystal can be cleaned. After the sweat stains and fine particles on the surface of the substrate 31, the semiconductor structure 3 (shown in FIG. 7) is produced by recycling and re-using the same epitaxial substrate 31.

After a plurality of epitaxial semiconductors 4 connected to each other in a structure corresponding to the connection region 328 of the permanent substrate unit 40 are obtained, the step of dividing and forming the electrodes 23 is further performed, and the permanent substrate unit is divided along the etching enhancement track 34. A structure corresponding to the connection region 328 of 40 can obtain a plurality of independent epitaxial semi-finished products 4. Referring to Figures 3, 7, and 13, wherein each of the individual epitaxial semiconductors 4 has an epitaxial film 131 and a permanent substrate 132. The permanent substrate 132 has a bottom region 327 and a portion of the plating thickening layer 41 formed on the top surface of the bottom region 327. Finally, the epitaxial film 131 of the epitaxial semi-finished products 4 is respectively plated with a predetermined electrode 133 opposite to the surface of the permanent substrate 132 to obtain an epitaxial element as shown in FIG.

It can be seen from the above description that the present invention mainly utilizes the connection region 328 of the underlayer 325 to form the permanent substrate unit 40 uniformly connected to the epitaxial layer unit 321 without warping or lifting, thereby effectively improving the overall process. Yield. In the epitaxial substrate separation step 223, the epitaxial semi-finished products 4 to be formed into epitaxial elements are not separately positioned by blue glue, and the epitaxial layers can be directly connected and fixed by the connection regions 328. The bottom portion 327 of the semi-finished product 4.

Referring to FIGS. 6 and 14, it is to be noted that the method for fabricating the preferred embodiment can repeat the epitaxial layer cell formation step 212 to sequentially form a plurality of epitaxial layer cells 321 on the epitaxial substrate 31. The underlayer formation step 213 is continued on the topmost epitaxial layer unit 321 . Referring to FIG. 15, the molding separation process 22 is further performed, and the epitaxial semi-finished product 4 (FIG. 13) formed by the topmost epitaxial layer unit 321 is separated from the epitaxial substrate 31 by the etching solution. Obtaining the epitaxial semi-finished product 4 (as shown in FIG. 13) obtained by the topmost epitaxial layer unit 321 , and completely removing the second layer body 324 of the topmost epitaxial layer unit 321 by using a chemical solution, and retaining the time a first layer body 323 of the epitaxial layer unit 321 of one layer and completely exposed; the underlying layer forming step 213, the etching enhancement track forming step 221, the plating thickening layer forming step 222, and the The epitaxial substrate separation step 223 is performed until the epitaxial layer unit 321 connected to the epitaxial substrate 31 is separated from the epitaxial substrate 31, and finally, the surface of the epitaxial substrate 31 is cleaned by a chemical etching solution and a liquid such as water. The remaining second layer body 324, the fine particles and the dirt are stained, and the epitaxial substrate 31 is returned to the unused state, and the epitaxial substrate 31 can be further recovered and reused.

In summary, the semiconductor structure of the present invention utilizes the extensions 330 of the connection regions 328 to be symmetrically connected to the corners of the base regions 327 such that the underlayer 325 and the underlying layer 325 are formed. The plating thickening layer 41 is not warped and deformed. In addition, the permanent substrate 132 of the epitaxial element formed by the epitaxial semi-finished product 4 which is continuously formed by the semiconductor structure 3 of the present invention is not warped, and the heat dissipation property of the permanent substrate 132 is improved, and the epitaxial film 131 is promoted by the epitaxial film 131. The generated waste heat energy can be smoothly dissipated through the permanent substrate 132 which is affixed to the epitaxial film 131 and is not warped, and the component is prevented from being overheated.

In addition, the present invention also provides a method for fabricating the semiconductor structure 3 and the epitaxial semi-finished product 4, thereby avoiding the waste of the blue-glue resources that the epitaxial semi-finished products 4 need to be fixed by the blue glue, so that the object of the present invention can be achieved.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

131. . . Epitaxial film

132. . . Permanent substrate

133. . . electrode

twenty one. . . Semiconductor structure process

211. . . Epitaxial substrate preparation step

212. . . Epitaxial layer unit formation step

213. . . Bottom layer formation step

twenty two. . . Molding separation process

221. . . Etched reinforcement path forming step

222. . . Electroplating thickening layer forming step

223. . . Epitaxial substrate separation step

twenty three. . . Segmentation and formation of electrodes

3. . . Semiconductor structure

31. . . Epitaxial substrate

32. . . main body

321. . . Epitaxial layer unit

323. . . First layer

324. . . Second layer

325. . . Bottom layer

327. . . Bottom area

328. . . Connection area

329. . . Base

330. . . Extension

33. . . Etch

34. . . Etched reinforcement

35. . . Filling

4. . . Epitaxial semi-finished products

40. . . Permanent substrate unit

41. . . Electroplated thickening layer

Figure 1 is a schematic view showing a conventional epitaxial element;

2 is a schematic view showing an epitaxial element having a polymer gel;

3 is a schematic view showing an epitaxial element with good heat dissipation effect;

Figure 4 is a perspective view showing the current semiconductor structure;

Figure 5 is a cross-sectional view showing the current semiconductor structure;

6 is a flow chart for explaining the flow of the epitaxial element production process by the method for fabricating the epitaxial semi-finished product of the present invention;

Figure 7 is a perspective view showing a semiconductor structure of the present invention;

Figure 8 is a schematic view showing an epitaxial layer unit formed on the top surface of the epitaxial substrate;

Figure 9 is a perspective view showing the bottom surface of the semiconductor structure of the present invention may be rectangular;

Figure 10 is a schematic view showing a second layer top surface, a first layer body, and a bottom layer defining a plurality of etched reinforcement tracks;

Figure 11 is a schematic view showing filling of a filler in the etched reinforcement tracks;

Figure 12 is a schematic view showing a plating-plating thickening layer on the top surface of the underlying layer;

Figure 13 is a schematic view showing a substrate for epitaxy separated from a plurality of epitaxial semi-finished products;

Figure 14 is a schematic view showing formation of a plurality of epitaxial layer units on the substrate for epitaxy;

Figure 15 is a schematic view showing the formation of the etch-enhanced track in the topmost epitaxial layer unit.

3. . . Semiconductor structure

31. . . Epitaxial substrate

32. . . main body

321. . . Epitaxial layer unit

323. . . First layer

324. . . Second layer

325. . . Bottom layer

327. . . Bottom area

328. . . Connection area

329. . . Base

330. . . Extension

33. . . Etch

Claims (11)

A semiconductor structure comprising: an epitaxial substrate; and a body comprising an epitaxial layer unit and a bottom layer, the epitaxial layer unit having a first layer formed upward from the epitaxial substrate, The underlayer is formed on the top surface of the first layer body, and includes a plurality of bottom regions spaced apart from each other and regularly arranged, and a plurality of connection regions, each of the connection regions connecting the corners of the adjacent regions adjacent to each other. The top surface of the seed layer unit and the bottom region of the underlying layer and the connection region together define a plurality of etched tracks which are predetermined to divide the epitaxial layer unit into a plurality of epitaxial films respectively corresponding to the underlying regions. The semiconductor structure according to claim 1, wherein the underlying layer of the underlying layer is rectangular, and each of the connecting regions has a base portion located at a geometric center defined by four adjacent bottom regions, and four respective portions An extension of equal length connected to the adjacent base regions, the adjacent extensions of each connection region being at a predetermined angle of insertion. The semiconductor structure according to claim 2, wherein the underlying layers are square, the distance between any two adjacent underlying regions is equal, each connecting region is a symmetrical pattern, and the phase of each connecting region The adjacent two extensions are vertical, and each etched track is a hexagon. The semiconductor structure of claim 3, wherein the epitaxial layer unit further comprises a second layer body formed on the epitaxial substrate, the second layer body being etched compared to the first layer body The etching rate of the liquid is selected to be high. A method for fabricating a semiconductor structure, comprising: an epitaxial substrate preparation step, preparing an epitaxial substrate; an epitaxial layer unit forming step, epitaxially forming a first layer on the epitaxial substrate to form a Lei a layer layer unit; and a primer layer forming step, forming a bottom layer defining a plurality of etched trace patterns on the first layer body, the underlayer layer comprising a plurality of bottom regions spaced apart from each other and regularly arranged, and a plurality of connections a connection region, wherein each of the connection regions is connected to a corner of the base region adjacent to each other, and the top surface of the epitaxial layer unit and the bottom region of the base layer and the connection region jointly define a plurality of predetermined divisions of the epitaxial layer unit into a plurality Corresponding to the etched tracks of the epitaxial films of the underlying regions, respectively. The method for fabricating a semiconductor structure according to claim 5, wherein the epitaxial layer unit forming step forms a second layer body on the epitaxial substrate, and the second layer body is formed on the second layer body The first layer body, and the second layer body has a higher ratio of etching selectivity to the first layer body. A method for fabricating an epitaxial semi-finished product, comprising: a semiconductor structure process comprising: an epitaxial substrate preparation step, preparing an epitaxial substrate, an epitaxial layer unit forming step, and sequentially epitaxially e depositing the epitaxial substrate a second layer body and a first layer body are formed on the epitaxial substrate to form an epitaxial layer unit, and a bottom layer forming step, and a bottom layer defining a plurality of etched pattern is formed on the first layer a layer, the underlayer includes a plurality of bottom regions spaced apart from each other and regularly arranged, and a plurality of connection regions, each of the connection regions connecting corners of the adjacent substrate adjacent to each other, the top surface of the epitaxial layer unit and the bottom layer The underlying region of the layer and the connection region collectively define a plurality of etched tracks which are predetermined to divide the epitaxial layer unit into a plurality of epitaxial films respectively corresponding to the underlying regions, to obtain a semiconductor structure; and a molding separation process, including An etching enhancement track forming step of removing the first layer body exposed to the outside of the underlying layer, and removing the first layer body and the second layer body layer under the underlying layer that are not removed Surface, and the underlying area and connection of the underlying layer Defining a etched enhancement track that is predetermined to divide the epitaxial layer unit into a plurality of epitaxial films respectively corresponding to the underlying regions, the etching enhancement track having a depth greater than the etching path, and an electroplating thickening layer forming step The top surface of the underlayer is formed with a plating thickening layer having thermal conductivity characteristics, and an epitaxial substrate separating step, the epitaxial crystal plate is separated from the first layer of the epitaxial layer unit, and a plurality of epitaxial grains are obtained. Semi finished product. The method for producing an epitaxial semi-finished product according to claim 7, wherein the electroplated thickening layer of the electroplating thickening layer forming step is made of a material having magnetic properties. The method for fabricating an epitaxial semi-finished product according to claim 8 , wherein the electroplating thickening layer forming step first fills a filling material in the etching reinforcing track, and forms an upper surface of the underlying layer by electroplating. The plating thickens the layer and the fill is removed. The method for fabricating an epitaxial semi-finished product according to claim 9, wherein the etching enhancement path forming step is performed by dry etching from a first layer body exposed outside the underlying layer to the epitaxial substrate The direction removes the first layer body that is exposed outside the base layer. The method for fabricating an epitaxial semi-finished product according to claim 10, wherein the substrate separating step for epitaxial etching is performed by wet etching to pour an etching solution from the etching enhancement channel to etch the second layer body. The crystal substrate is separated from the first layer body.