TWI446539B - Semiconductor structure - Google Patents

Description

Semiconductor structure

This invention relates to a semiconductor structure, and more particularly to a semiconductor structure for a thin film transistor.

A liquid crystal display (LCD) mainly comprises a thin film transistor substrate, a color filter and a plurality of liquid crystal cells. The thin film transistor array substrate is composed of a plurality of pixel structures, and each pixel structure corresponds to a liquid crystal cell. The thin film transistor substrate has a scan line, a pixel electrode, and a switch. The switch has a gate, a source, and a drain, and is electrically connected to the scan line, the data line, and the pixel electrode, respectively.

In general, the aperture ratio of a pixel directly affects the utilization of the backlight and the brightness of the liquid crystal display. In the design of the capacitor structure, the common electrode line is used as the lower electrode of the capacitor structure, and the pixel electrode is formed as the common electrode line of the upper electrode covering portion of the capacitor structure, which may be referred to as a capacitor on the common electrode. (Cst on common), and because the common electrode line and the gate are on different dielectric layers, and the common electrode line overlaps with the gate electrode portion, when there is a semiconductor layer above the gate electrode, the dielectric layer covers the gate When the electrode and the semiconductor layer are formed, an inclined surface is formed on the side of the dielectric layer. When a part of the common electrode line is located on the side of the dielectric layer, the partial common electrode has an inclined surface. However, since the common electrode line is a metal layer, the inclined surface of the common electrode line reflects the light from the backlight module. If the light is reflected into the semiconductor layer, the light leakage may cause the product to crosstalk.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor structure for solving the problem of light leakage caused by the common electrode reflecting light to the channel layer.

According to an embodiment of the invention, a semiconductor structure includes a substrate, a first metal layer, a dielectric layer, a channel layer, a second metal layer, a protective layer, a third metal layer, and an insulating layer. a first transparent conductive layer and a second transparent conductive layer. The first metal layer is disposed on the substrate, and the first metal layer includes a gate. The dielectric layer is disposed on the substrate and the gate. The channel layer is disposed on the dielectric layer above the gate. The second metal layer is disposed on the dielectric layer and the channel layer, and the second metal layer includes a drain and a source. The protective layer is disposed on the dielectric layer, the second metal layer and the channel layer. The third metal layer is disposed on the protective layer, the third metal layer includes a common electrode, and the common electrode and the gate have a horizontal interval. The insulating layer is disposed on the third metal layer and the protective layer. The first transparent conductive layer is disposed between the protective layer and the insulating layer and is in direct contact with the third metal layer, wherein the first transparent conductive layer is partially located on the gate, and the first transparent conductive layer has an opening to expose the channel layer, wherein The common electrode and the first transparent conductive layer form a capacitor electrode. The third metal layer and the first transparent conductive layer form a capacitor upper electrode. The second transparent conductive layer is disposed on the insulating layer and connected to the drain. The common electrode and the first transparent conductive layer are located on the second metal layer, and the capacitor electrode and the second metal layer form a capacitor. The second transparent conductive layer portion is located on the common electrode and the first transparent conductive layer, and the capacitor electrode and the second transparent conductive layer form an additional capacitor.

A portion of the first transparent conductive layer is between the third metal layer and the insulating layer. Alternatively, a portion of the first transparent conductive layer is between the third metal layer and the protective layer. The horizontal spacing between the common electrode and the gate can be at least 3.5 microns. The first metal layer further includes a scan line, the gate is connected to the scan line, and a part of the common electrode overlaps the scan line. The width of the portion of the common electrode on the scan line is substantially larger than the width of the scan line. The first transparent conductive layer extends from the third metal layer toward the channel layer.

Another aspect of the present invention is a method of fabricating a semiconductor structure, comprising: forming a first metal layer on a substrate to define a gate; forming a dielectric layer on the first metal layer and the substrate; forming a channel Laying on the dielectric layer, wherein the channel layer is on a portion of the gate; forming a second metal layer on the dielectric layer to define a source and a drain; forming a protective layer on the second metal layer and the channel layer And a dielectric layer, wherein the protective layer is on the second metal layer; a third metal layer is formed on the protective layer to define a common electrode, and the common electrode and the gate have a horizontal spacing; forming a first transparent a conductive layer, the first transparent conductive layer directly contacts the common electrode, the first transparent conductive layer has an opening to expose the channel layer, the common electrode and the first transparent conductive layer form a capacitor upper electrode; and an insulating layer is formed on the third metal layer And a first transparent conductive layer and a protective layer; and a second transparent conductive layer on the insulating layer, and the second transparent conductive layer is connected to the drain. The common electrode and the first transparent conductive layer are located on the second metal layer, and the capacitor electrode and the second metal layer form a capacitor. The second transparent conductive layer portion is located on the common electrode and the first transparent conductive layer, and the capacitor electrode and the second transparent conductive layer form an additional capacitor.

The first transparent conductive layer is between the insulating layer and the protective layer. A portion of the first transparent conductive layer is between the third metal layer and the protective layer. Alternatively, a portion of the first transparent conductive layer is between the insulating layer and the third metal layer. The step of forming the first metal layer further includes defining a scan line, the gate is connected to the scan line, and a portion of the common electrode overlaps the scan line. The width of the portion of the common electrode on the scan line is substantially greater than the width of the scan line. The first transparent conductive layer extends from the common electrode toward the channel layer. The horizontal spacing between the common electrode and the gate is at least 3.5 microns.

There is a horizontal spacing between the common electrode and the gate to prevent light from the backlight module from being reflected by the common electrode to the channel layer on the gate. The present invention provides a transparent conductive layer in direct contact with the common electrode to maintain the capacitance value, and since the transparent conductive layer does not reflect light from the backlight module, there is no light leakage.

The spirit and scope of the present invention will be apparent from the following description of the preferred embodiments of the invention. The spirit and scope of the invention are not departed.

Referring also to FIGS. 1 through 3, FIG. 1 is a partial top plan view of an embodiment of a semiconductor structure of the present invention. Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1, and Fig. 3 is a cross-sectional view taken along line B-B' of Fig. 1.

The semiconductor structure 100 includes a substrate 110, a first metal layer 120, a dielectric layer 130, a channel layer 140, a second metal layer 150, a protective layer 160, a third metal layer 170, an insulating layer 180, and a first transparent conductive layer 190. And a second transparent conductive layer 200. The first metal layer 120 is disposed on the substrate 110, and the first metal layer 120 includes a gate 122. The dielectric layer 130 is disposed on the substrate 110 and the first metal layer 120. The channel layer 140 is disposed on the dielectric layer 130, and the channel layer 140 is located on a portion of the gate 122. The second metal layer 150 is disposed on the dielectric layer 130 and the channel layer 140, and the second metal layer 150 includes a drain 152 and a source 154. The protective layer 160 is disposed on the dielectric layer 130, the second metal layer 150, and the channel layer 140. The third metal layer 170 is disposed on the protective layer 160. The third metal layer 170 includes a common electrode 172 having a horizontal spacing d between the common electrode 172 and the gate 122. The insulating layer 180 is disposed on the third metal layer 170 and the protective layer 160. The first transparent conductive layer 190 is disposed between the protective layer 160 and the insulating layer 180 and is in direct contact with the third metal layer 170. The first transparent conductive layer 190 is partially located on the gate 122 of the first metal layer 120. A portion of the first transparent conductive layer 190 is located between the common electrode 172 of the third metal layer 170 and the insulating layer 180. The first transparent conductive layer 190 has an opening 192 to expose the channel layer 140. The second transparent conductive layer 200 is disposed on the insulating layer 180 and connected to the drain 152.

In order to prevent light from the backlight module from being reflected by the third metal layer 170 to the channel layer 140, the third metal layer 170 is disposed at a distance from the gate 122 by a horizontal distance d, and the horizontal pitch d is at least 3.5 microns. Further, since it is desired not to sacrifice the aperture ratio of the pixel, the third metal layer 170 and the gate 122 are separated by a horizontal interval d in such a manner as to reduce the area of the third metal layer 170. At the same time, in order to prevent the capacitance value from decreasing due to the reduction of the area of the third metal layer 170, the present invention provides a first transparent conductive layer 190 over the third metal layer 170, and the first transparent conductive layer 190 is directly in contact with the third metal layer 170, and It extends from the third metal layer 170 to overlap with the portion and the gate 122. The second transparent conductive layer 200, the second metal layer 150, the first transparent conductive layer 190 and the third metal layer 170 form a capacitance. More specifically, the drain 152 of the second metal layer 150 and the source 154, the first transparent conductive layer 190 and the third metal layer 170 form a capacitor, in other words, the first metal layer is provided with a first transparent layer. The conductive layer 190 serves as the upper electrode of the capacitor electrode, and the drain 152 and the source 154 of the second metal layer 150 serve as the lower electrode of the capacitor electrode; in addition, the second transparent conductive layer 200 and the first transparent conductive layer 190 and the third metal layer 170 form an additional capacitor, that is, the second transparent conductive layer 200 is used as the upper electrode of the additional capacitor electrode, and the first transparent conductive layer 190 is disposed as the additional capacitor electrode over the third metal layer 170. Lower electrode.

Referring to FIGS. 4A to 4F, there is shown a flow chart showing a method of fabricating the semiconductor structure in FIG. 1. For the following description, reference is also made to FIGS. 2 and 3. First, a first metal layer 120 is formed on the substrate 110, wherein the first metal layer 120 includes a gate 122 and a scan line 124, and the gate 122 is connected to the scan line 124. A dielectric layer 130 (see FIG. 2) is formed over the first metal layer 120 and the substrate 110. Next, as shown in FIG. 4B, a channel layer 140 is formed on the dielectric layer 130, wherein the channel layer 140 is located on a portion of the gate 122. The channel layer 140 is a semiconductor layer, and the area of the channel layer 140 is slightly smaller than the area of the gate 122.

Referring to FIG. 4C, a second metal layer 150 is formed on the dielectric layer 130. The second metal layer 150 includes a drain 152 and a source 154. The second metal layer 150 further includes a data line 156, the data line 156 is substantially perpendicular to the scan line 124, and the source 154 is connected to the data line 156. The second metal layer 150 further includes a contact window pad 158 that connects the drain 152. Part of the drain 152 and a portion of the source 154 are located on the channel layer 140. A protective layer 160 (see FIG. 3) is formed over the dielectric layer 130, the channel layer 140, and the second metal layer 150.

Referring to FIG. 4D, a third metal layer 170 is formed on the protective layer 160. The third metal layer 170 includes a common electrode 172 having an opening 174 above the gate 122 and the channel layer 140 such that the common electrode 172 does not overlap the gate 122, and the level between the common electrode 172 and the gate 122 is horizontal. Spacing distance d. A portion of the common electrode 172 overlaps the scan line 124, and a portion of the common electrode 172 located on the scan line 124 has a width w1 that is substantially larger than a width w2 of the scan line 124.

Referring to FIG. 4E, a first transparent conductive layer 190 is formed on the common electrode 172 and the protective layer 160 on the periphery of the gate 122. The first transparent conductive layer 190 is in direct contact with the common electrode 172, and the first transparent conductive layer 190 presents a frame. The first transparent conductive layer 190 has an opening 192, and the channel layer 140 is exposed to the opening 192. The opening 192 of the first transparent conductive layer 190 has an area smaller than the opening 174 of the common electrode 172, so that the first transparent conductive layer 190 surrounds the channel layer. 140 is disposed, and the outer edge of the first transparent conductive layer 190 is connected to the common electrode 172, and the first transparent conductive layer 190 extends from the common electrode 172 to the channel layer 140. Then, an insulating layer 180 (see FIG. 3) is formed on the first transparent conductive layer 190, the third metal layer 170, and the protective layer 160.

Referring to FIG. 4F, a second transparent conductive layer 200 is formed on the insulating layer 180. The second transparent conductive layer 200 serves as a pixel electrode, and the second transparent conductive layer 200 is connected to the drain 152 through the contact pad 158.

The common electrode 172 and the gate 122 have a horizontal spacing d to prevent light from the backlight module from being reflected by the common electrode 172 to the channel layer 140 on the gate 122. The present invention increases the first transparent conductive layer 190 in direct contact with the common electrode 172 to maintain the capacitance value, and since the first transparent conductive layer 190 does not reflect the light from the backlight module, there is no light leakage.

Referring to Figures 5 and 6, there is shown a cross-sectional view of another embodiment of a semiconductor structure of the present invention. Fig. 5 is a cross-sectional view taken along line A-A' of Fig. 7F, and Fig. 6 is a cross-sectional view taken along line B-B' of Fig. 7F. The semiconductor structure 100 includes a substrate 110, a first metal layer 120, a dielectric layer 130, a channel layer 140, a second metal layer 150, a protective layer 160, a third metal layer 170, an insulating layer 180, and a first transparent conductive layer 190. The second transparent conductive layer 200. The first metal layer 120 is disposed on the substrate 110, and the first metal layer 120 includes a gate 122. The dielectric layer 130 is disposed on the substrate 110 and the first metal layer 120. The channel layer 140 is disposed on the dielectric layer 130, and the channel layer 140 is located on a portion of the gate 122.

The second metal layer 150 is disposed on the dielectric layer 130 and the channel layer 140, and the second metal layer 150 includes a drain and a source. The protective layer 160 is disposed on the dielectric layer 130, the second metal layer 150, and the channel layer 140.

The first transparent conductive layer 190 is disposed on the protective layer 160, and the first transparent conductive layer 190 is partially disposed on the gate 122 of the first metal layer 120. The first transparent conductive layer 190 has an opening 192 to expose the channel layer 140. The third metal layer 170 is disposed on the first transparent conductive layer 190 and the protective layer 160. The third metal layer 170 includes a common electrode 172, and the common electrode 172 and the gate 122 have a horizontal spacing d. A portion of the first transparent conductive layer 190 is located between the common electrode 172 of the third metal layer 170 and the protective layer 160. The insulating layer 180 is then disposed on the third metal layer 170, the first transparent conductive layer 190, and the protective layer 160. Finally, the second transparent conductive layer 200 is disposed on the insulating layer 180.

The third metal layer 170 is disposed at a horizontal spacing d from the gate 122, and the horizontal spacing d is at least 3.5 microns to prevent the light of the backlight module from being reflected by the third metal layer 170 to the channel layer 140. In the meantime, in order to prevent the capacitance value from decreasing due to the reduction of the area of the third metal layer 170, the present invention provides a first transparent conductive layer 190 under the third metal layer 170, and the first transparent conductive layer 190 is directly in contact with the third metal layer 170, and The third metal layer 170 extends to partially overlap the gate 122. The second transparent conductive layer 200, the second metal layer 150, the first transparent conductive layer 190 and the third metal layer 170 form a capacitance. More specifically, the drain 152 of the second metal layer 150 and the source 154, the first transparent conductive layer 190 and the third metal layer 170 form a capacitor, in other words, the first transparent layer is disposed under the third metal layer 170. The conductive layer 190 serves as the upper electrode of the capacitor electrode, and the drain 152 and the source 154 of the second metal layer 150 serve as the lower electrode of the capacitor electrode; in addition, the second transparent conductive layer 200 and the first transparent conductive layer 190 and the third metal layer 170 form an additional capacitor, that is, the second transparent conductive layer 200 is used as the upper electrode of the additional capacitor electrode, and the first transparent conductive layer 190 is disposed under the third metal layer 170 as the additional capacitor electrode. Lower electrode.

Next, referring again to FIGS. 7A to 7F, a flow chart showing a method of fabricating the semiconductor structure in FIG. 5 is shown. First, a first metal layer 120 is formed on the substrate 110, wherein the first metal layer 120 includes a gate 122 and a scan line 124, and the gate 122 is connected to the scan line 124. A dielectric layer 130 (see FIG. 5) is formed over the first metal layer 120 and the substrate 110. Next, as shown in FIG. 7B, a channel layer 140 is formed on the dielectric layer 130, wherein the channel layer 140 is located on a portion of the gate 122. The channel layer 140 is a semiconductor layer, and the area of the channel layer 140 is slightly smaller than the area of the gate 122.

Referring to FIG. 7C, a second metal layer 150 is formed on the dielectric layer 130, and the second metal layer 150 includes a drain 152 and a source 154. The second metal layer 150 further includes a data line 156, the data line 156 is substantially perpendicular to the scan line 124, and the source 154 is connected to the data line 156. The second metal layer 150 further includes a contact window pad 158 that connects the drain 152. Part of the drain 152 and a portion of the source 154 are located on the channel layer 140. The protective layer 160 is further formed (see FIG. 5 on the dielectric layer 130, the channel layer 140, and the second metal layer 150).

Referring to FIG. 7D, a first transparent conductive layer 190 is formed on the protective layer 160. The first transparent conductive layer 190 has a frame shape, the first transparent conductive layer 190 has an opening 192, the channel layer 140 is exposed to the opening 192, and the first transparent conductive layer 190 is disposed around the channel layer 140.

Referring to FIG. 7E, a third metal layer 170 is formed on the protective layer 160 and the first transparent conductive layer 190. The third metal layer 170 includes a common electrode 172, wherein the common electrode 172 has an opening 174, and the opening 174 of the common electrode 172 has an area larger than the opening 192 of the first transparent conductive layer 190, so that the common electrode 172 exposes a portion of the first transparent conductive layer. 190, and the common electrode 172 is in direct contact with the outer edge of the first transparent conductive layer 190. The opening 174 of the common electrode 172 places the common electrode 172 at the periphery of the gate 122 and the channel layer 140 without overlapping the gate 122, and has a horizontal spacing between the common electrode 172 and the gate 122. A portion of the common electrode 172 overlaps the scan line 124, and a portion of the common electrode 172 located on the scan line 124 has a width w1 that is substantially larger than a width w2 of the scan line 124. Then, an insulating layer 180 (see FIG. 5) is formed on the third metal layer 170, the first transparent conductive layer 190, and the protective layer 160.

Referring to FIG. 7F, a second transparent conductive layer 200 is formed on the insulating layer 180. The second transparent conductive layer 200 serves as a pixel electrode, and the second transparent conductive layer 200 is connected to the drain 152 through the contact pad 158.

The common electrode 172 and the gate 122 have a horizontal spacing to prevent light from the backlight module from being reflected by the common electrode 172 to the channel layer 140 on the gate 122. The present invention increases the first transparent conductive layer 190 in direct contact with the common electrode 172 to maintain the capacitance value, and since the first transparent conductive layer 190 does not reflect the light from the backlight module, there is no light leakage.

Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Semiconductor structure

110. . . Substrate

120. . . First metal layer

122. . . Gate

124. . . Scanning line

130. . . Dielectric layer

140. . . Channel layer

150. . . Second metal layer

152. . . Bungee

154. . . Source

156. . . Data line

158. . . Contact window mat

160. . . The protective layer

170. . . Third metal layer

172. . . Common electrode

174. . . Opening

180. . . Insulation

190. . . First transparent conductive layer

192. . . Opening

200. . . Second transparent conductive layer

d. . . Horizontal spacing

W1, w2. . . width

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

1 is a partial top elevational view of an embodiment of a semiconductor structure of the present invention.

Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1.

Fig. 3 is a cross-sectional view taken along line B-B' of Fig. 1.

4A to 4F are flowcharts showing a method of fabricating the semiconductor structure in Fig. 1.

5 and 6 are cross-sectional views showing another embodiment of the semiconductor structure of the present invention, respectively.

7A to 7F are flowcharts showing a method of fabricating the semiconductor structure in FIG. 5.

100. . . Semiconductor structure

110. . . Substrate

120. . . First metal layer

122. . . Gate

130. . . Dielectric layer

150. . . Second metal layer

160. . . The protective layer

170. . . Third metal layer

172. . . Common electrode

180. . . Insulation

190. . . First transparent conductive layer

d. . . Horizontal spacing

Claims (18)

A semiconductor structure comprising: a substrate; a first metal layer disposed on the substrate, the first metal layer comprising a gate; a dielectric layer disposed on the substrate and the gate; a channel layer, disposed On the dielectric layer above the gate; a second metal layer disposed on the dielectric layer and the channel layer, the second metal layer comprising a drain and a source; a protective layer disposed on The dielectric layer, the second metal layer and the channel layer; a third metal layer disposed on the protective layer, the third metal layer comprises a common electrode, and the common electrode and the gate have a a horizontal spacing; an insulating layer disposed on the third metal layer and the protective layer; a first transparent conductive layer disposed between the protective layer and the insulating layer and in direct contact with the common electrode, wherein the first a transparent conductive layer is partially disposed on the gate, the first transparent conductive layer has an opening to expose the channel layer, wherein the common electrode and the first transparent conductive layer form a capacitor electrode; and a second transparent conductive layer, Placed on top of the insulating layer Connected to the drain. The semiconductor structure of claim 1, wherein the common electrode and the first transparent conductive layer are on the second metal layer, and the capacitor electrode and the second metal layer form a capacitor. The semiconductor structure of claim 1, wherein the second transparent conductive layer is partially located on the common electrode and the first transparent conductive layer, and the capacitor electrode and the second transparent conductive layer form an additional capacitor. The semiconductor structure of claim 1, wherein a portion of the first transparent conductive layer is between the third metal layer and the insulating layer. The semiconductor structure of claim 1, wherein a portion of the first transparent conductive layer is between the third metal layer and the protective layer. The semiconductor structure of claim 1, wherein the horizontal spacing between the common electrode and the gate is at least 3.5 microns. The semiconductor structure of claim 1, wherein the first metal layer further comprises a scan line, the gate is connected to the scan line, and a portion of the common electrode overlaps the scan line. The semiconductor structure of claim 7, wherein the portion of the common electrode on the scan line has a width substantially greater than a width of the scan line. The semiconductor structure of claim 1, wherein the first transparent conductive layer extends from the third metal layer to the channel layer. A method for fabricating a semiconductor structure, comprising: forming a first metal layer on a substrate to define a gate; forming a dielectric layer on the first metal layer and the substrate; forming a channel layer on the dielectric a layer, wherein the channel layer is located on a portion of the gate; forming a second metal layer on the dielectric layer to define a source and a drain; forming a protective layer on the second metal layer, the channel Forming a third metal layer on the protective layer to define a common electrode having a horizontal spacing between the common electrode and the gate; forming a first transparent conductive layer, the first a transparent conductive layer directly contacting the common electrode, the first transparent conductive layer having an opening to expose the channel layer, wherein the common electrode and the first transparent conductive layer form a capacitor electrode; forming an insulating layer in the third a metal layer, the first transparent conductive layer and the protective layer; and a second transparent conductive layer on the insulating layer, and the second transparent conductive layer is connected to the drain. The method of fabricating a semiconductor structure according to claim 10, wherein the common electrode and the first transparent conductive layer are on the second metal layer, and the capacitor electrode and the second metal layer form a capacitor. The method of fabricating a semiconductor structure according to claim 10, wherein the second transparent conductive layer is partially located on the common electrode and the first transparent conductive layer, and the capacitor electrode and the second transparent conductive layer form a Additional capacitors. The method of fabricating a semiconductor structure according to claim 10, wherein a portion of the first transparent conductive layer is located between the third metal layer and the protective layer. The method of fabricating a semiconductor structure according to claim 10, wherein a portion of the first transparent conductive layer is between the insulating layer and the third metal layer. The method of fabricating a semiconductor structure according to claim 10, wherein the step of forming a first metal layer further comprises defining a scan line, the gate is connected to the scan line, and a portion of the common electrode overlaps the scan line. . The method of fabricating a semiconductor structure according to claim 15 wherein the width of the portion of the common electrode on the scan line is substantially greater than the width of the scan line. The method of fabricating a semiconductor structure according to claim 10, wherein the first transparent conductive layer extends from the common electrode toward the channel layer. The method of fabricating a semiconductor structure according to claim 10, wherein the horizontal spacing between the common electrode and the gate is at least 3.5 microns.