CN1893088A - Film transistor array - Google Patents
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- CN1893088A CN1893088A CN 200510079394 CN200510079394A CN1893088A CN 1893088 A CN1893088 A CN 1893088A CN 200510079394 CN200510079394 CN 200510079394 CN 200510079394 A CN200510079394 A CN 200510079394A CN 1893088 A CN1893088 A CN 1893088A
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Abstract
The array of thin film transistor (TFT) includes base plate, multiple TFT, multiple pixel electrodes, multiple bars of shared wiring, and multiple auxiliary electrodes. Multiple TFT, pixel electrodes, and auxiliary electrodes are setup on pixel area on base plate respectively. There is first overlap area between drain electrode and grid electrode of TFT in order to form parasitic capacitance between grid electrode and drain electrode. Extending to under a pixel electrode on channel layer along one direction, drain electrode of TFT is connected to the pixel electrode electrically through contact window. Being positioned under pixel electrode, each auxiliary electrode is extended to one side of shared wiring above the shared wiring along the said direction so as to form second overlap area between extended auxiliary electrode and shared wiring, or form storage capacitance.
Description
Technical field
The present invention relates to a kind of thin film transistor (TFT) array (thin film transistor array, TFT array), and be particularly related to a kind of inhomogeneity thin film transistor (TFT) array that can improve display brightness.
Background technology
Multimedia society improves rapidly, is indebted to the tremendous progress of semiconductor element or display unit mostly.With regard to display, have that high image quality, space utilization efficient are good, (thin film transistor liquid crystaldisplay TFT-LCD) becomes the main flow in market to the Thin Film Transistor-LCD of low consumpting power, advantageous characteristic such as radiationless gradually.
Thin Film Transistor-LCD mainly is made of thin film transistor (TFT) array, colored filter (colorfilter) and liquid crystal layer (liquid crystal layer).Fig. 1 is the schematic top plan view of known thin film transistor (TFT) array.Please refer to Fig. 1, thin film transistor (TFT) array 100 mainly is made of a plurality of dot structures 110 with arrayed.Wherein, each dot structure 110 by scan distribution (scanline) 112, data wiring (date line) 114, thin-film transistor 116 and with 118 compositions of pixel electrode (pixel electrode) of thin-film transistor 116 corresponding settings.
Please continue with reference to Fig. 1, thin-film transistor 116 is used as the switch element of dot structure 110, scan wiring 112 and data wiring 114 then are used to provide the suitable operating voltage of its selected dot structure 110, the display image to drive each dot structure 110 respectively.
Fig. 2 is a kind of schematic equivalent circuit of single pixel of known Thin Film Transistor-LCD.Please refer to Fig. 2, in the single pixel of known Thin Film Transistor-LCD, comprise thin-film transistor 110, liquid crystal capacitance C usually
LCAnd storage capacitance (storage capacitance) C
St
Please be simultaneously with reference to Fig. 1 and Fig. 2, liquid crystal capacitance C
LCBe coupled to form by common electrode (common electrode) (not shown) on pixel electrode on the thin film transistor (TFT) array 100 118 and the colored filter.Storage capacitance C
StBe positioned on the thin film transistor (TFT) array 100, and this storage capacitance C
StWith liquid crystal capacitance C
LCAnd scan wiring 112 is electrically connected.In addition, the grid G of thin-film transistor 116, source S and drain D respectively with scan wiring 112, data wiring 114 and liquid crystal capacitance C
LCIn pixel electrode 118 connect.And, owing between the grid G of thin-film transistor 116 and the drain D zone that overlaps each other is arranged, therefore between grid G and drain D, can there be a gate-to-drain parasitic capacitance (parasitic capacitance) C
Gd
Please continue with reference to Fig. 1 and Fig. 2, owing to be applied to liquid crystal capacitance C
LCOn voltage (also just putting on the voltage on pixel electrode 118 and the common electrode) and the light transmittance of liquid crystal molecule between have particular kind of relationship, therefore be applied to liquid crystal capacitance C as long as control according to picture to display
LCOn voltage, can make display show predetermined picture.Wherein, when thin-film transistor 116 cuts out, liquid crystal capacitance C
LCOn voltage keep certain value (also just being in the holding state), but because gate-to-drain parasitic capacitance C
GdExistence, liquid crystal capacitance C
LCOn the voltage that kept will change and change (also with regard to so-called coupling effect) to some extent along with the signal on the data wiring 114, thereby make liquid crystal capacitance C
LCOn the value of the original setting of the voltage deviation that kept.This variation in voltage amount is called feed-trough voltage (feed-through voltage) Δ Vp, and it can be expressed as:
Wherein Δ Vg puts on the amplitude that scans the pulse voltage on the distribution 112.
In present thin film transistor (TFT) array manufacturing process, carry out the exposure manufacturing process of thin film transistor (TFT) array mostly with the spliced photomask of step-by-step exposure machine, therefore in exposure process, the position that the offset deviation amount when board moves will cause formed pattern in each exposure area (shot) is difference to some extent.Special between each exposure area, the overlapping area of the grid G of thin-film transistor 116 and drain D (see figure 1) not simultaneously, with the gate-to-drain parasitic capacitance C that makes in each exposure area
GdDifference causes the feed-trough voltage Δ Vp in each exposure area inequality, and produces the uneven problem of display brightness in procedure for displaying.
In order to address the above problem, the known people of having proposes a kind of thin film transistor (TFT) array, and Fig. 3 is the schematic top plan view of another kind of known thin film transistor (TFT) array.Please refer to Fig. 3, known technology is designed to the T font with the drain electrode of thin-film transistor 316 in the thin film transistor (TFT) array 300, with the overlapping area R of drain electrode in the manufacturing process of will exposing with grid
1Issuable variation is reduced to w * x, and then dwindles the difference between each gate-to-drain parasitic capacitance.
In addition, the known another kind of method that addresses the above problem adds The Fuzzy Design between different exposure areas, to reduce the display defect (mura) of brightness irregularities on the border of exposure area.Yet, when the exposure accuracy error is excessive, more than two kinds of methods still can't improve the uneven problem of display brightness that is caused because of the photomask displacement error effectively.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of thin film transistor (TFT) array, and the exposure accuracy error of its each pixel can not impact its feed-trough voltage, so the display that thin film transistor (TFT) array constituted can have excellent display quality.
Another object of the present invention provides a kind of thin film transistor (TFT) array, and the display that it constituted can have good aperture opening ratio and display brightness uniformity simultaneously.
The present invention proposes a kind of thin film transistor (TFT) array, and it comprises substrate, a plurality of thin-film transistor, a plurality of pixel electrode, many shared distributions and a plurality of auxiliary electrode.Wherein, distinguish a plurality of pixel regions on the substrate, these thin-film transistors are separately positioned in each pixel region, and each thin-film transistor includes grid, channel layer, source electrode and drain electrode.In each thin-film transistor, has first overlapping region between drain electrode and the grid, so that form the gate-to-drain parasitic capacitance between drain electrode and the grid.These pixel electrodes also are arranged in each pixel region.Shared distribution is arranged on the substrate, and the subregion of these shared distributions is positioned at the pixel electrode below.
From the above, these auxiliary electrodes are arranged at respectively in each pixel region, and in each pixel region, auxiliary electrode is positioned at the pixel electrode below, and extend to a side of shared distribution from shared distribution top, and its bearing of trend is identical with the bearing of trend of drain electrode.Wherein, have second overlapping region between auxiliary electrode and the shared distribution, and these auxiliary electrodes are electrically connected to the pixel electrode of correspondence respectively, so that each auxiliary electrode shared wiring closet corresponding with its institute forms storage capacitance.
In preferred embodiment of the present invention, in each pixel region, shared distribution comprises first strip pattern and second strip pattern, and the bearing of trend of first strip pattern is different with the bearing of trend of second strip pattern.For instance, the bearing of trend of first strip pattern is for example vertical mutually with the bearing of trend of second strip pattern.
In preferred embodiment of the present invention, in each pixel region, auxiliary electrode for example is positioned partially between pixel electrode and first strip pattern and/or second strip pattern.
In preferred embodiment of the present invention, above-mentioned thin film transistor (TFT) array for example also comprises insulating barrier (insulating layer), is arranged between pixel electrode and auxiliary electrode, source electrode and the drain electrode.In one example, this insulating barrier for example has a plurality of first contact windows, and these pixel electrodes are inserted these first contact windows respectively and be electrically connected to the drain electrode and auxiliary electrode.
The present invention proposes a kind of thin film transistor (TFT) array in addition, and it comprises substrate, a plurality of thin-film transistor, a plurality of pixel electrode, many shared distributions, a plurality of bonding conductor layer and a plurality of auxiliary electrodes.Wherein, distinguish a plurality of pixel regions on the substrate, these thin-film transistors are separately positioned in each pixel region, and each thin-film transistor includes grid, channel layer, source electrode and drain electrode.In each thin-film transistor, has first overlapping region between drain electrode and the grid, so that form the gate-to-drain parasitic capacitance between drain electrode and the grid.These pixel electrodes also are arranged in each pixel region, and the drain electrode of each thin-film transistor extends to the pixel electrode below of correspondence from channel layer upper edge one direction, and are electrically connected pixel electrode so far.Shared distribution is arranged on the substrate, and the subregion of these shared distributions is positioned at the pixel electrode below.
From the above, these bonding conductor layers are separately positioned in each pixel region, and are positioned at shared distribution top and are electrically connected to these shared distributions.Auxiliary electrode then is arranged in each pixel region respectively, and in each pixel region, auxiliary electrode is positioned at pixel electrode and bonding conductor layer below, and extends to a side of shared distribution from shared distribution top, and its bearing of trend is identical with the bearing of trend of drain electrode.Wherein, have second overlapping region between auxiliary electrode and the shared distribution, and these auxiliary electrodes are electrically connected to the pixel electrode of correspondence respectively, so that each auxiliary electrode shared wiring closet corresponding with its institute forms storage capacitance.In addition, then form interlayer electric capacity between these bonding conductor layers and each auxiliary electrode.
In preferred embodiment of the present invention, in each pixel region, shared distribution comprises first strip pattern and second strip pattern, and the bearing of trend of first strip pattern is different with the bearing of trend of second strip pattern.For instance, the bearing of trend of first strip pattern is for example vertical mutually with the bearing of trend of second strip pattern.
In preferred embodiment of the present invention, in each pixel region, the bonding conductor layer for example is positioned at the top of first strip pattern and/or second strip pattern of shared distribution.
In preferred embodiment of the present invention, above-mentioned thin film transistor (TFT) array for example also comprises insulating barrier, is arranged between pixel electrode and auxiliary electrode, source electrode and the drain electrode.In one example, this insulating barrier for example has a plurality of first contact windows, and these pixel electrodes are inserted these first contact windows respectively and be electrically connected to the drain electrode and auxiliary electrode.
In preferred embodiment of the present invention, above-mentioned thin film transistor (TFT) array for example also comprises gate insulation layer, and it is arranged between drain electrode, source electrode and the grid, and between auxiliary electrode and the shared distribution.In one example, above-mentioned insulating barrier also has a plurality of second contact windows, and it for example runs through insulating barrier and gate insulation layer, and the bonding conductor layer is inserted these second contact windows respectively and be electrically connected to shared distribution.
The present invention can solve known display floater because of the not good problem of thin film transistor (TFT) array exposure manufacturing process display quality that error causes, and aperture opening ratio that also can counter plate causes bad influence.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the schematic top plan view of known thin film transistor (TFT) array.
Fig. 2 is a kind of schematic equivalent circuit of single pixel of known Thin Film Transistor-LCD.
Fig. 3 is the schematic top plan view of another kind of known thin film transistor (TFT) array.
Fig. 4 is the schematic top plan view of thin film transistor (TFT) array among the present invention's first embodiment.
Fig. 5 is the generalized section of the thin film transistor (TFT) array of Fig. 4 along I-I ' line.
Fig. 6 is the schematic top plan view of thin film transistor (TFT) array among the present invention's second embodiment.
Fig. 7 is the schematic top plan view of thin film transistor (TFT) array among the present invention's the 3rd embodiment.
Fig. 8 is the generalized section of the thin film transistor (TFT) array of Fig. 7 along II-II ' line.
Fig. 9 is the schematic top plan view of thin film transistor (TFT) array among the present invention's the 4th embodiment.
The main element description of symbols
100,300,400,600,700: thin film transistor (TFT) array
110: dot structure
112,404: scan distribution
114,406: data wiring
116,316,410: thin-film transistor
118,420: pixel electrode
402: substrate
408: pixel region
412, G: grid
414: channel layer
416, S: source electrode
418, D: drain electrode
422: gate insulation layer
424: the first contact windows
425; Second contact window
426: insulating barrier
430: shared distribution
432: the first strip patterns
434: the second strip patterns
440: auxiliary electrode
450: the bonding conductor layer
A
1: first overlapping region
A
2: second overlapping region
C
1, C
2, C
St: storage capacitance
C
Gd: the gate-to-drain parasitic capacitance
C
LC: liquid crystal capacitance
Embodiment
The present invention is provided with auxiliary electrode in thin film transistor (TFT) array, it is used so that the gate-to-drain parasitic capacitance variation in each pixel region becomes a special ratios with the storage capacitance variation, and then makes the feed-trough voltage in each exposure area approximate each other.Below will the present invention be described, but it is not in order to limit the present invention for embodiment.
Fig. 4 is the schematic top plan view of thin film transistor (TFT) array among the present invention's first embodiment.Fig. 5 then is the generalized section of the thin film transistor (TFT) array of Fig. 4 along I-I ' line.Please refer to Fig. 4, thin film transistor (TFT) array 400 mainly is made of substrate 402, a plurality of thin-film transistor 410, a plurality of pixel electrode 420, many shared distributions 430 and a plurality of auxiliary electrode 440.Wherein, substrate 402 is provided with and scans distribution 404 and data wiring 406, and scans distribution 404 and data wiring 406 is distinguished a plurality of pixel regions 408 on substrate 402, and these pixel electrodes 420 promptly are separately positioned in each pixel region 408.
From the above, be provided with a thin-film transistor 410 in each pixel region 408, and each thin-film transistor 410 includes grid 412, channel layer 414, source electrode 416 and drains 418.Wherein, grid 412 is electrically connected to and scans distribution 404, and since grid 412 with scanning distribution 404 with finishing in the manufacturing process, so can be directly with the some that scans distribution 404 grids 412, as shown in Figure 4 as thin-film transistor 410.Source electrode 416 is electrically connected to data wiring 406, drains 418 and extends to pixel electrode 420 belows from channel layer 414 upper edge direction p, and be electrically connected to pixel electrode 420.Noticeable, have the first overlapping region A between drain electrode 418 and the grid 412
1, thereby between grid 412 and drain electrode 418, form gate-to-drain parasitic capacitance C
Gd(see figure 5).
Please continue with reference to Fig. 4, shared distribution 430 is arranged on the substrate 402, and has the subregion to be positioned at pixel electrode 420 belows, and the shared distribution 430 of each bar all scans between the distribution 404 at adjacent two.In addition, shared distribution 430 for example has first strip pattern 432 and second strip pattern 434 in each pixel region 408.Wherein, first strip pattern 432 and second strip pattern 434 for example extend toward different directions.In the present embodiment, first strip pattern 432 is for example vertical mutually with second strip pattern 434.For instance, first strip pattern 432 is for example parallel with data wiring 416, and second strip pattern 434 for example with scan distribution parallel 414.Certainly, the person of ordinary skill in the field should be understood that shared distribution 430 can also be rendered as other pattern, and the present invention is not limited it.
Especially, also be provided with auxiliary electrode 440 in each pixel region 408, it is arranged at pixel electrode 420 belows, and extends to a side of shared distribution 430 along direction p from shared distribution 430 tops.Wherein, direction p is for example perpendicular to the bearing of trend of second strip pattern 434 of shared distribution 430.And auxiliary electrode 440 is promptly from second strip pattern, the 434 upper edge direction p of shared distribution 430 and extend to the one side.At this, has the second overlapping region A between auxiliary electrode 440 and the shared distribution 430
2
Please refer to Fig. 5, the person of ordinary skill in the field should be understood that usually after forming grid 412 and shared distribution 430, can form gate insulation layer 422 earlier on substrate 402, just forms channel layer 414 then on gate insulation layer 422.And grid, drain electrode 418 promptly constitute with gate insulation layer 422 and have above-mentioned gate-to-drain parasitic capacitance C
GdCapacitor.
In addition, after forming source electrode 416 and drain electrode 418, cambium layer insulating barrier 426 on substrate 402 earlier covering thin-film transistor 410, shared distribution 430 and auxiliary electrode 440, and then forms pixel electrode 420 on insulating barrier 426.Wherein, insulating barrier 426 has a plurality of first contact windows 424 that expose the drain electrode 418 of thin-film transistor 410, and pixel electrode 420 is promptly inserted in these first contact windows 424, to be electrically connected to drain electrode 418.
Be worth mentioning, first contact window 424 of part also exposes auxiliary electrode 440.In other words, the pixel electrode of inserting in first contact window 424 420 also can be electrically connected to auxiliary electrode 440.Hence one can see that, the present invention's auxiliary electrode 440 and pixel electrode 420 equipotentials, and the second overlapping region A of auxiliary electrode 440
2And then form storage capacitance C between the shared distribution 430
St
Referring again to Fig. 4, especially since drain electrode 418 with auxiliary electrode 440 to finish the patterning manufacturing process with photomask, therefore in the exposure manufacturing process, when photomask generation displacement error and make the first overlapping region A
1During less than default value, the second overlapping region A
2Also can be less than default value.Similarly, produce displacement error and make the first overlapping region A when photomask
1During greater than default value, the second overlapping region A
2Also can be greater than default value.Also just say gate-to-drain parasitic capacitance C
GdWith storage capacitance C
StCan increase simultaneously or reduce because of the manufacturing process error.
And, by the expression (seeing formula (1)) of feed-trough voltage Δ Vp as can be known, at voltage Δ Vg and liquid crystal capacitance C
LCBe under the situation of definite value, if gate-to-drain parasitic capacitance C
GdWith storage capacitance C
StIncrease simultaneously in the proper ratio or reduce, then can make feed-trough voltage Δ Vp keep definite value.Referring again to Fig. 4, the present invention promptly designs the shape and the area of auxiliary electrode 440 according to this principle, so that storage capacitance C
StThe variation and the gate-to-drain parasitic capacitance C that are produced because of the manufacturing process error
GdVariation between have proper proportion.Thus, even the first overlapping region A in each pixel region 408
1And the second overlapping region A
2Area different because of the manufacturing process error, but still can have identical feed-trough voltage Δ Vp in each pixel region 408.
Fig. 6 is the schematic top plan view of thin film transistor (TFT) array among the present invention's second embodiment.Wherein, the thin film transistor (TFT) array 600 of present embodiment and the thin film transistor (TFT) array 400 of first embodiment are roughly the same, therefore hereinafter will do explanation at its different place.
Please refer to Fig. 6, the drain electrode 412 of thin-film transistor 410 extends to pixel electrode 420 belows from channel layer 414 upper edge direction q, and is electrically connected with pixel electrode 420 by first contact window 424.In addition, auxiliary electrode 440 is extended to a side of shared distribution 430 along direction q by shared distribution 430 tops.Wherein, direction q is for example perpendicular to the bearing of trend of first strip pattern 432 of shared distribution 430, and auxiliary electrode 440 is promptly from first strip pattern, the 432 upper edge direction q of shared distribution 430 and extend to the one side.Hence one can see that, and when producing the displacement error on the direction q in drain electrode 418 is exposing manufacturing process, auxiliary electrode 440 also can produce displacement error on direction q.Therefore, the second overlapping region A between auxiliary electrode 440 and the shared distribution 430
2Area will and the drain electrode 418 and grid 412 between the first overlapping region A
1Area increase simultaneously pro rata or reduce, and then make the feed-trough voltages in each pixel region 408 keep definite value.
Noticeable, though the storage capacitance C of present embodiment
StVariable quantity depend primarily on the overlapping area variable quantity of auxiliary electrode 440 and first strip pattern 432 of shared distribution 430, but auxiliary electrode 440 also can partly be overlapped in second strip pattern, 434 tops of shared distribution 430, to increase the storage capacitance C in each pixel region 408
StSame, in the present invention's first embodiment, auxiliary electrode 400 also can partly be overlapped in first strip pattern, 432 tops of shared distribution 430, and the person of ordinary skill in the field should understand its details, draws accompanying drawing explanation herein no longer separately.
In addition, the present invention also proposes a kind of thin film transistor (TFT) array in another embodiment, it not only can reach the effect of the foregoing description, more owing to the two interelectrode spacings that wherein constitute storage capacitance are little, therefore can be under the prerequisite that does not influence storage capacitance value, dwindle the area of auxiliary electrode, and then increase the aperture opening ratio of thin film transistor (TFT) array.Below will it be described for embodiment.
Fig. 7 is the schematic top plan view of thin film transistor (TFT) array among the present invention's the 3rd embodiment.Fig. 8 then is the generalized section of the thin film transistor (TFT) array of Fig. 7 along II-II ' line.Similarly, the thin film transistor (TFT) array 700 of present embodiment and the thin film transistor (TFT) array 400 of first embodiment are roughly the same, therefore hereinafter will do explanation at its different place.
Please except element shown in Figure 4, also be provided with bonding conductor layer 450 in each pixel region 408 of thin film transistor (TFT) array 700 simultaneously with reference to Fig. 7 and Fig. 8, it is positioned at the top of auxiliary electrode 440 and shared distribution 430, and is electrically connected to shared distribution 430.In detail, the insulating barrier 426 of present embodiment for example also has a plurality of second contact windows 425, and these second contact windows run through insulating barrier 426 and gate insulation layer 422, and expose partial common distribution 430 in each pixel region 408, so that the bonding conductor layer 450 that is arranged on the insulating barrier 426 can be electrically connected to shared distribution 430 by inserting second contact window 425.
In addition, bonding conductor layer 450 can be with pixel electrode 720 to complete with photomask.Also just say that bonding conductor layer 450 for example is made of transparent conductive oxide equally with pixel electrode 720.Certainly, bonding conductor layer 450 also can use different photomasks next patterned respectively with pixel electrode 720, and the present invention is not limited it.
Please continue with reference to Fig. 8, from the above, bonding conductor layer 450 and shared distribution 430 equipotentials then form storage capacitance C between bonding conductor layer 450 and the auxiliary electrode 440
1In addition, as described in first embodiment, pixel electrode 720 is inserted first contact window 424 of insulating barrier 426 and is electrically connected to auxiliary electrode 440, and then forms storage capacitance C between auxiliary electrode 440 and the shared distribution 430
2Hence one can see that, the storage capacitance C of present embodiment
StBe storage capacitance C
1With storage capacitance C
2In parallel and equivalent capacity.
The capacitance that the person of ordinary skill in the field the should be understood that capacitor area of two electrodes of capacitor therewith is directly proportional, and the spacing of two electrodes of capacitor is inversely proportional to therewith.According to this principle, in the present embodiment since between bonding conductor layer 450 and the auxiliary electrode 440 and the spacing between auxiliary electrode 440 and the shared distribution 430 lack, so with have storage capacitance C equally
StThin film transistor (TFT) array in comparison, the thin film transistor (TFT) array 700 of present embodiment can also dwindle the area of auxiliary electrode 440 further, so that increase the aperture opening ratio of thin film transistor (TFT) array 700.
Fig. 9 is the schematic top plan view of thin film transistor (TFT) array among the present invention's the 4th embodiment.Please refer to Fig. 9, be worth mentioning, though second strip pattern, 434 tops that auxiliary electrode 440 shown in Figure 7 and bonding conductor layer 450 are positioned at shared distribution 430, but as aforementioned explanation, auxiliary electrode 440 and bonding conductor layer 450 also can be arranged on first strip pattern, 432 tops of shared distribution 430 in the present embodiment.Certainly, auxiliary electrode 440 and bonding conductor layer 450 can also be arranged on first strip pattern 432 and second strip pattern, the 434 top (not shown)s of shared distribution 430 simultaneously, and the present invention is not limited this.
The present invention's thin film transistor (TFT) array mainly is provided with auxiliary electrode in each pixel region, and makes this auxiliary electrode and shared distribution constitute storage capacitance.When this thin film transistor (TFT) array in the exposure manufacturing process because of photomask produces displacement error, and when forming different gate-to-drain parasitic capacitances in each exposure area, it also can form different storage capacitances simultaneously in each exposure area.Wherein, when the gate-to-drain parasitic capacitance in a certain exposure area greater than/during less than the gate-to-drain parasitic capacitance in the exposure area last time, storage capacitance in this exposure area also greater than/less than the storage capacitance in the exposure area last time, and the variable quantity of storage capacitance becomes a special ratios with the variable quantity of gate-to-drain parasitic capacitance, so that the feed-trough voltage in each exposure area is kept identical definite value, and then make the thin film transistor (TFT) array that utilizes the present invention can have excellent display quality as the display of display floater.
In addition, the present invention also is provided with the bonding conductor layer in thin film transistor (TFT) array, and constituting storage capacitance between auxiliary electrode and the shared distribution and between bonding conductor layer and the auxiliary electrode, also just shorten the spacing of two electrodes that constitute these storage capacitances, with under the prerequisite of the electrical performance that does not change storage capacitance, dwindle the area of auxiliary electrode, and then increase the aperture opening ratio of thin-film transistor.
In sum, the present invention can solve known display floater because of the not good problem of thin film transistor (TFT) array exposure manufacturing process display quality that error causes, and aperture opening ratio that also can counter plate causes bad influence.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and improvement, thus the present invention's protection range when with claim the person of being defined be as the criterion.
Claims (14)
1. thin film transistor (TFT) array is characterized in that comprising:
Substrate has a plurality of pixel regions;
A plurality of thin-film transistors, be arranged at respectively respectively in this pixel region, and respectively this thin-film transistor comprises grid, channel layer, source electrode and drain electrode, wherein this channel layer is arranged between this source electrode, this drain electrode and this grid, and have first overlapping region between this drain electrode and this grid, form gate-to-drain parasitic capacitance (parasitic capacitance) between drain electrode and this grid so that be somebody's turn to do;
A plurality of pixel electrodes are arranged at respectively respectively in this pixel region, and wherein respectively this drain electrode extends to this pixel electrode below of correspondence from this channel layer upper edge one direction of correspondence, and is electrically connected to this pixel electrode;
Many shared distributions are arranged on this substrate, and the subregion of above-mentioned these shared distributions is positioned at above-mentioned these pixel electrode belows; And
A plurality of auxiliary electrodes, be arranged at respectively this interior pixel electrode below of this pixel region respectively, and respectively this auxiliary electrode is from this shared distribution top of correspondence, extend to a side of this shared distribution in the direction, wherein respectively this auxiliary electrode has second overlapping region with corresponding this shared wiring closet, and above-mentioned these auxiliary electrodes are electrically connected to respectively one of to be stated on the correspondence in these pixel electrodes, so that formation one storage capacitance (storagecapacitance) between this auxiliary electrode and corresponding this shared distribution respectively.
2. the thin film transistor (TFT) array according to claim 1, it is characterized in that in this pixel region respectively, this shared distribution has first strip pattern and second strip pattern, and the bearing of trend of this first strip pattern is different with the bearing of trend of this second strip pattern.
3. the thin film transistor (TFT) array according to claim 2 is characterized in that in this pixel region respectively, vertical this second strip pattern of this first strip pattern of this shared distribution.
4. the thin film transistor (TFT) array according to claim 2 is characterized in that in this pixel region respectively, and this auxiliary electrode is positioned partially at this first strip pattern and/or this second strip pattern top.
5. the thin film transistor (TFT) array according to claim 1 is characterized in that also comprising insulating barrier, is arranged between above-mentioned these pixel electrodes and above-mentioned these auxiliary electrodes, above-mentioned these source electrodes and above-mentioned these drain electrodes.
6. the thin film transistor (TFT) array according to claim 5, it is characterized in that this insulating barrier has a plurality of first contact windows, and above-mentioned these pixel electrodes are inserted above-mentioned these first contact windows respectively and be electrically connected to above-mentioned these the drain electrode with above-mentioned these auxiliary electrodes.
7. thin film transistor (TFT) array is characterized in that comprising:
Substrate has a plurality of pixel regions;
A plurality of thin-film transistors, be arranged at respectively respectively in this pixel region, and respectively this thin-film transistor comprises grid, channel layer, source electrode and drain electrode, wherein this channel layer is arranged between this source electrode, this drain electrode and this grid, and this drain electrode and this grid have first overlapping region, form the gate-to-drain parasitic capacitance between drain electrode and this grid so that be somebody's turn to do;
A plurality of pixel electrodes are arranged at respectively respectively in this pixel region, and wherein respectively this drain electrode extends to this pixel electrode below of correspondence from this channel layer upper edge one direction of correspondence, and is electrically connected to this pixel electrode;
Many shared distributions are arranged on this substrate, and the subregion of above-mentioned these shared distributions is positioned at above-mentioned these pixel electrode belows;
A plurality of bonding conductor layers are arranged at respectively respectively in this pixel region and are positioned at this shared distribution top, and above-mentioned these bonding conductor layers are electrically connected to above-mentioned these shared distributions respectively; And
A plurality of auxiliary electrodes, be arranged at respectively interior this pixel electrode and this bonding conductor layer below of this pixel region respectively, respectively this auxiliary electrode is from this shared distribution top of correspondence, extend to a side of this shared distribution in the direction, wherein respectively this auxiliary electrode has second overlapping region with corresponding this shared wiring closet, and above-mentioned these auxiliary electrodes are electrically connected to respectively one of to be stated on the correspondence in these pixel electrodes, so that respectively this auxiliary electrode with corresponding on one of state in these shared distributions between, and above-mentioned these bonding conductor layers and respectively form storage capacitance between this auxiliary electrode respectively.
8. the thin film transistor (TFT) array according to claim 7, it is characterized in that in this pixel region respectively, this shared distribution has first strip pattern and second strip pattern, and the bearing of trend of this first strip pattern is different with the bearing of trend of this second strip pattern.
9. described according to Claim 8 thin film transistor (TFT) array is characterized in that this first strip pattern of this shared distribution is perpendicular to this second strip pattern in this pixel region respectively.
10. described according to Claim 8 thin film transistor (TFT) array is characterized in that in this pixel region respectively, and this bonding conductor layer is positioned at this first strip pattern and/or this second strip pattern top.
11. the thin film transistor (TFT) array according to claim 7 is characterized in that also comprising insulating barrier, is arranged between above-mentioned these pixel electrodes and above-mentioned these auxiliary electrodes, above-mentioned these source electrodes and above-mentioned these drain electrodes.
12. the thin film transistor (TFT) array according to claim 11, it is characterized in that this insulating barrier has a plurality of first contact windows, and above-mentioned these pixel electrodes are inserted above-mentioned these first contact windows respectively and be electrically connected to above-mentioned these the drain electrode with above-mentioned these auxiliary electrodes.
13. the thin film transistor (TFT) array according to claim 12 is characterized in that also comprising gate insulation layer, is arranged at above-mentioned these drain electrodes, above-mentioned these source electrodes and above-mentioned these grids, and between above-mentioned these auxiliary electrodes and above-mentioned these shared distributions.
14. the thin film transistor (TFT) array according to claim 13, it is characterized in that this insulating barrier also has a plurality of second contact windows, and above-mentioned these second contact windows run through this insulating barrier and this gate insulation layer, and above-mentioned these bonding conductor layers are inserted above-mentioned these second contact windows respectively and be electrically connected to above-mentioned these shared distributions.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510079394 CN1893088A (en) | 2005-07-04 | 2005-07-04 | Film transistor array |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510079394 CN1893088A (en) | 2005-07-04 | 2005-07-04 | Film transistor array |
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| CN1893088A true CN1893088A (en) | 2007-01-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200510079394 Pending CN1893088A (en) | 2005-07-04 | 2005-07-04 | Film transistor array |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2011131143A1 (en) * | 2010-04-23 | 2011-10-27 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and liquid crystal display |
| CN102520555A (en) * | 2011-12-02 | 2012-06-27 | 深圳市华星光电技术有限公司 | Pixel structure, array substrate and liquid crystal display device |
| CN102610629A (en) * | 2011-12-23 | 2012-07-25 | 友达光电股份有限公司 | Semiconductor structure |
| CN103336397A (en) * | 2013-07-01 | 2013-10-02 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN105259717A (en) * | 2015-11-25 | 2016-01-20 | 深圳市华星光电技术有限公司 | Array substrate and display device |
| CN112863329A (en) * | 2019-11-12 | 2021-05-28 | 群创光电股份有限公司 | Display device |
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2005
- 2005-07-04 CN CN 200510079394 patent/CN1893088A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2011131143A1 (en) * | 2010-04-23 | 2011-10-27 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and liquid crystal display |
| US9753335B2 (en) | 2010-04-23 | 2017-09-05 | Beijing Boe Optoelectronics Technology Co., Ltd. | Array substrate with additional electrode formed above gate line, manufacturing method thereof and liquid crystal display |
| CN102520555A (en) * | 2011-12-02 | 2012-06-27 | 深圳市华星光电技术有限公司 | Pixel structure, array substrate and liquid crystal display device |
| CN102610629A (en) * | 2011-12-23 | 2012-07-25 | 友达光电股份有限公司 | Semiconductor structure |
| CN102610629B (en) * | 2011-12-23 | 2014-04-02 | 友达光电股份有限公司 | Semiconductor structure |
| CN103336397A (en) * | 2013-07-01 | 2013-10-02 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| WO2015000273A1 (en) * | 2013-07-01 | 2015-01-08 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN103336397B (en) * | 2013-07-01 | 2015-09-09 | 京东方科技集团股份有限公司 | A kind of array base palte, display panel and display device |
| US9613574B2 (en) | 2013-07-01 | 2017-04-04 | Boe Technology Group Co., Ltd. | Switch circuit to control the flow of charges in the parasitic capacitance of a TFT in the pixel of a display |
| CN105259717A (en) * | 2015-11-25 | 2016-01-20 | 深圳市华星光电技术有限公司 | Array substrate and display device |
| CN112863329A (en) * | 2019-11-12 | 2021-05-28 | 群创光电股份有限公司 | Display device |
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