CN1893088A - thin film transistor array - Google Patents

Abstract

A thin film transistor array includes a substrate, a plurality of thin film transistors, a plurality of pixel electrodes, a plurality of common wirings and a plurality of auxiliary electrodes. These thin film transistors, pixel electrodes and auxiliary electrodes are respectively arranged in the pixel area on the substrate. There is a first overlapping area between the drain and the gate of the thin film transistor, so that a gate-drain parasitic capacitor is formed between the drain and the gate, and the drain of the thin film transistor extends from the channel layer in one direction to the bottom of the pixel electrode, and is electrically connected to the pixel electrode through a contact window. Each auxiliary electrode is located below the pixel electrode, and extends from above the common wiring in the above direction to one side of the common wiring, and has a second overlapping area with the common wiring, so that a storage capacitor is formed between each auxiliary electrode and the corresponding common wiring.

Description

thin film transistor array

technical field

The present invention relates to a thin film transistor array (thin film transistor array, TFT array), and in particular to a thin film transistor array capable of improving the uniformity of display brightness.

Background technique

The rapid progress of the multimedia society is mostly due to the rapid progress of semiconductor components or display devices. As far as displays are concerned, thin film transistor liquid crystal displays (TFT-LCDs), which have superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation, have gradually become the mainstream of the market.

TFT LCD is mainly composed of TFT array, color filter (color filter) and liquid crystal layer (liquid crystal layer). FIG. 1 is a schematic top view of a known thin film transistor array. Referring to FIG. 1 , the thin film transistor array 100 is mainly composed of a plurality of pixel structures 110 arranged in an array. Each pixel structure 110 is composed of a scanline 112, a data line 114, a TFT 116 and a pixel electrode 118 corresponding to the TFT 116.

Please continue to refer to FIG. 1, the thin film transistor 116 is used as a switching element of the pixel structure 110, and the scan wiring 112 and the data wiring 114 are used to provide the appropriate operating voltage for the selected pixel structure 110 to drive each pixel structure 110 respectively. The pixel structure 110 is used to display an image.

FIG. 2 is a schematic diagram of an equivalent circuit of a single pixel of a known thin film transistor liquid crystal display. Referring to FIG. 2 , a single pixel of a known TFT-LCD usually includes a TFT 110 , a liquid crystal capacitor C _LC , and a storage capacitor (storage capacitance) C _st .

Please refer to FIG. 1 and FIG. 2 at the same time. The liquid crystal capacitor C _LC is formed by coupling the pixel electrode 118 on the thin film transistor array 100 and the common electrode (not shown) on the color filter. The storage capacitor C _st is located on the thin film transistor array 100 , and the storage capacitor C _st is electrically connected to the liquid crystal capacitor C _LC and the scanning wire 112 . In addition, the gate G, the source S and the drain D of the TFT 116 are respectively connected to the scan line 112 , the data line 114 and the pixel electrode 118 in the liquid crystal capacitor C _LC . Moreover, since the gate G and the drain D of the TFT 116 overlap each other, there is a gate-drain parasitic capacitance C _gd between the gate G and the drain D.

Please continue to refer to FIG. 1 and FIG. 2, since there is a specific relationship between the voltage applied to the liquid crystal capacitor C _LC (that is, the voltage applied to the pixel electrode 118 and the common electrode) and the light transmittance of the liquid crystal molecules, as long as Control the voltage applied to the liquid crystal capacitor C _LC according to the picture to be displayed, so that the display can display a predetermined picture. Wherein, when the thin film transistor 116 is turned off, the voltage on the liquid crystal capacitor C _LC maintains a certain value (that is, in the holding state), but due to the existence of the gate-drain parasitic capacitance C _gd , the voltage held on the liquid crystal capacitor C _LC It will change as the signal on the data wiring 114 changes (so-called coupling effect), so that the voltage held on the liquid crystal capacitor C _LC deviates from the originally set value. This voltage variation is called feed-through voltage ΔVp, which can be expressed as:

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; st</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; LC</span>}}}\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Wherein ΔVg is the amplitude of the pulse voltage applied to the scanning wiring 112 .

In the current thin film transistor array manufacturing process, most of the exposure manufacturing process of the thin film transistor array is carried out with the spliced photomask of the stepper exposure machine. Therefore, during the exposure process, the displacement deviation when the machine moves will cause each The position of the pattern formed in the exposure area (shot) is different. Especially when the overlapping areas of the gate G and the drain D (see FIG. 1 ) of the thin film transistor 116 are different between each exposure area, the gate-drain parasitic capacitance C _gd in each exposure area will be different, causing each The feed-through voltage ΔVp in the exposure area is not the same, and the problem of non-uniform display brightness occurs during the display process.

In order to solve the above problems, a known thin film transistor array has been proposed, and FIG. 3 is a schematic top view of another known thin film transistor array. Please refer to FIG. 3 . In the known technology, the drain of the thin film transistor 316 in the thin film transistor array 300 is designed to be T-shaped, so as to reduce the possible fluctuation of the overlapping area _R1 between the drain and the gate in the exposure manufacturing process to w× x, thereby reducing the difference between the individual gate-drain parasitic capacitances.

In addition, another known method to solve the above-mentioned problem is to add a blurring design between different exposure areas to reduce the display defect (mura) of uneven brightness at the boundary of the exposure areas. However, when the exposure accuracy error is too large, the above two methods still cannot effectively improve the problem of non-uniform display brightness caused by the photomask displacement error.

Contents of the invention

In view of this, the purpose of the present invention is to provide a thin film transistor array, the exposure accuracy error of each pixel will not affect its feed-through voltage, so the display formed by the thin film transistor array can have excellent display quality.

Another object of the present invention is to provide a thin film transistor array, and the display formed by it can have good aperture ratio and uniformity of display brightness at the same time.

The invention provides a thin film transistor array, which includes a substrate, a plurality of thin film transistors, a plurality of pixel electrodes, a plurality of common wiring lines and a plurality of auxiliary electrodes. Wherein, a plurality of pixel regions are distinguished on the substrate, and these thin film transistors are respectively arranged in each pixel region, and each thin film transistor includes a gate, a channel layer, a source and a drain. In each thin film transistor, there is a first overlapping region between the drain and the gate, so that a gate-drain parasitic capacitance is formed between the drain and the gate. These pixel electrodes are also arranged in each pixel area. The common lines are arranged on the substrate, and some areas of these common lines are located under the pixel electrodes.

As mentioned above, these auxiliary electrodes are respectively arranged in each pixel area, and in each pixel area, the auxiliary electrodes are located below the pixel electrodes, and extend from above the common wiring to one side of the common wiring, and the extending direction Same direction as the extension of the drain. There is a second overlapping area between the auxiliary electrodes and the common wiring, and these auxiliary electrodes are respectively electrically connected to the corresponding pixel electrodes, so that storage capacitors are formed between each auxiliary electrode and the corresponding common wiring.

In a preferred embodiment of the present invention, in each pixel area, the common wiring includes a first strip pattern and a second strip pattern, and the extension direction of the first strip pattern is the same as the extension direction of the second strip pattern different. For example, the extending direction of the first strip pattern and the extending direction of the second strip pattern are, for example, perpendicular to each other.

In a preferred embodiment of the present invention, in each pixel area, for example, the auxiliary electrode is partially located between the pixel electrode and the first strip pattern and/or the second strip pattern.

In a preferred embodiment of the present invention, the above-mentioned thin film transistor array further includes, for example, an insulating layer disposed between the pixel electrode and the auxiliary electrode, the source electrode and the drain electrode. In one example, the insulating layer has a plurality of first contact openings, and the pixel electrodes respectively fill in the first contact openings and are electrically connected to the drain and the auxiliary electrodes.

The present invention further provides a thin film transistor array, which includes a substrate, a plurality of thin film transistors, a plurality of pixel electrodes, a plurality of common lines, a plurality of connection conductor layers, and a plurality of auxiliary electrodes. Wherein, a plurality of pixel regions are distinguished on the substrate, and these thin film transistors are respectively arranged in each pixel region, and each thin film transistor includes a gate, a channel layer, a source and a drain. In each thin film transistor, there is a first overlapping region between the drain and the gate, so that a gate-drain parasitic capacitance is formed between the drain and the gate. These pixel electrodes are also arranged in each pixel region, and the drain of each thin film transistor extends from the channel layer to the bottom of the corresponding pixel electrode along a direction, and is electrically connected to the pixel electrode. The common lines are arranged on the substrate, and some areas of these common lines are located under the pixel electrodes.

As mentioned above, the connecting conductor layers are respectively disposed in the respective pixel regions, and are located above the common wirings and electrically connected to the common wirings. The auxiliary electrodes are respectively arranged in each pixel area, and in each pixel area, the auxiliary electrodes are located below the pixel electrode and the connecting conductor layer, and extend from above the common wiring to one side of the common wiring, and its extending direction is the same as that of the common wiring. The drain electrodes extend in the same direction. There is a second overlapping area between the auxiliary electrodes and the common wiring, and these auxiliary electrodes are respectively electrically connected to the corresponding pixel electrodes, so that storage capacitors are formed between each auxiliary electrode and the corresponding common wiring. In addition, interlayer capacitors are formed between these connection conductor layers and each auxiliary electrode.

In a preferred embodiment of the present invention, in each pixel area, the common wiring includes a first strip pattern and a second strip pattern, and the extension direction of the first strip pattern is the same as the extension direction of the second strip pattern different. For example, the extending direction of the first strip pattern and the extending direction of the second strip pattern are, for example, perpendicular to each other.

In a preferred embodiment of the present invention, in each pixel region, the connection conductor layer is located above the first strip pattern and/or the second strip pattern of the common wiring, for example.

In a preferred embodiment of the present invention, the above thin film transistor array further includes, for example, an insulating layer disposed between the pixel electrode and the auxiliary electrode, the source electrode and the drain electrode. In one example, the insulating layer has a plurality of first contact openings, and the pixel electrodes respectively fill in the first contact openings and are electrically connected to the drain and the auxiliary electrodes.

In a preferred embodiment of the present invention, the above thin film transistor array further includes, for example, a gate insulating layer disposed between the drain, the source and the gate, and between the auxiliary electrode and the common wiring. In one example, the above-mentioned insulating layer further has a plurality of second contact openings, for example, penetrating through the insulating layer and the gate insulating layer, and the connecting conductor layer respectively fills these second contact openings and electrically connects to the common wiring.

The present invention can solve the known problem of poor display quality of the display panel due to the error in the exposure manufacturing process of the thin film transistor array, and will not cause adverse effects on the aperture ratio of the panel.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a schematic top view of a known thin film transistor array.

FIG. 2 is a schematic diagram of an equivalent circuit of a single pixel of a known thin film transistor liquid crystal display.

FIG. 3 is a schematic top view of another known thin film transistor array.

FIG. 4 is a schematic top view of the thin film transistor array in the first embodiment of the present invention.

5 is a schematic cross-sectional view of the thin film transistor array in FIG. 4 along line I-I'.

FIG. 6 is a schematic top view of the thin film transistor array in the second embodiment of the present invention.

FIG. 7 is a schematic top view of a thin film transistor array in a third embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of the thin film transistor array in FIG. 7 along the line II-II'.

FIG. 9 is a schematic top view of a thin film transistor array in a fourth embodiment of the present invention.

Description of main component marking

100, 300, 400, 600, 700: thin film transistor array

110: Pixel structure

112, 404: Scan wiring

114, 406: data wiring

116, 316, 410: thin film transistors

118, 420: pixel electrode

402: Substrate

408: Pixel area

412, G: grid

414: channel layer

416, S: source

418, D: Drain

422: Gate insulating layer

424: first contact window opening

425; second contact window opening

426: insulating layer

430: Shared wiring

432: First bar pattern

434: Second bar pattern

440: auxiliary electrode

450: Connect conductor layer

A ₁ : first overlapping area

A ₂ : Second overlapping area

C ₁ , C ₂ , C _st : storage capacitor

C _gd : Gate-drain parasitic capacitance

C _LC : Liquid crystal capacitance

Detailed ways

In the present invention, an auxiliary electrode is provided in the thin film transistor array, which is used to make the variation of the gate-drain parasitic capacitance in each pixel area and the variation of the storage capacitance in a specific ratio, and then make the feedthrough voltages in each exposure area approximate to each other . The following examples will be given to illustrate the present invention, but they are not intended to limit the present invention.

FIG. 4 is a schematic top view of the thin film transistor array in the first embodiment of the present invention. Fig. 5 is a schematic cross-sectional view of the thin film transistor array of Fig. 4 along the line I-I'. Referring to FIG. 4 , the thin film transistor array 400 is mainly composed of a substrate 402 , a plurality of thin film transistors 410 , a plurality of pixel electrodes 420 , a plurality of common wiring lines 430 and a plurality of auxiliary electrodes 440 . Wherein, the scanning wiring 404 and the data wiring 406 are arranged on the substrate 402, and the scanning wiring 404 and the data wiring 406 define a plurality of pixel regions 408 on the substrate 402, and these pixel electrodes 420 are respectively arranged on within each pixel region 408 .

As mentioned above, each pixel region 408 is provided with a thin film transistor 410 , and each thin film transistor 410 includes a gate 412 , a channel layer 414 , a source 416 and a drain 418 . Wherein, the gate 412 is electrically connected to the scanning wiring 404, and since the gate 412 and the scanning wiring 404 are completed in the same manufacturing process, a part of the scanning wiring 404 can be directly used as the thin film transistor 410 The gate 412 is shown in FIG. 4 . The source electrode 416 is electrically connected to the data wiring 406 , and the drain electrode 418 extends from the channel layer 414 to the bottom of the pixel electrode 420 along the direction p, and is electrically connected to the pixel electrode 420 . It is worth noting that there is a first overlapping region A ₁ between the drain 418 and the gate 412 , thus a gate-drain parasitic capacitance C _gd is formed between the gate 412 and the drain 418 (see FIG. 5 ).

Please continue to refer to FIG. 4 , the common lines 430 are disposed on the substrate 402 , and some areas are located under the pixel electrodes 420 , and each common line 430 is located between two adjacent scanning lines 404 . In addition, the common wiring 430 has, for example, a first strip pattern 432 and a second strip pattern 434 in each pixel region 408 . Wherein, the first strip pattern 432 and the second strip pattern 434 extend in different directions, for example. In this embodiment, the first strip pattern 432 and the second strip pattern 434 are perpendicular to each other, for example. For example, the first strip pattern 432 is parallel to the data wiring 416 , and the second strip pattern 434 is parallel to the scanning wiring 414 . Of course, those skilled in the art should know that the common wiring 430 may also be in other patterns, which are not limited by the present invention.

In particular, each pixel region 408 is also provided with an auxiliary electrode 440 , which is disposed below the pixel electrode 420 and extends from above the common wiring 430 to one side of the common wiring 430 along the direction p. Wherein, the direction p is, for example, perpendicular to the extending direction of the second strip pattern 434 of the common wiring 430 . The auxiliary electrode 440 extends from the second strip pattern 434 of the common wiring 430 to one side thereof along the direction p. Here, there is a second overlapping region A ₂ between the auxiliary electrode 440 and the common wiring 430 .

Referring to FIG. 5 , those skilled in the art should know that usually after forming the gate 412 and the common wiring 430 , a gate insulating layer 422 is formed on the substrate 402 first, and then a channel layer is formed on the gate insulating layer 422 414. The gate, the drain 418 and the gate insulating layer 422 constitute a capacitor having the above-mentioned gate-drain parasitic capacitance C _gd .

In addition, after the source electrode 416 and the drain electrode 418 are formed, an insulating layer 426 is first formed on the substrate 402 to cover the thin film transistor 410, the common wiring 430 and the auxiliary electrode 440, and then the pixel is formed on the insulating layer 426 electrode 420 . The insulating layer 426 has a plurality of first contact openings 424 exposing the drain 418 of the thin film transistor 410 , and the pixel electrode 420 is filled into the first contact openings 424 to be electrically connected to the drain 418 .

It is worth mentioning that part of the first contact window opening 424 also exposes the auxiliary electrode 440 . In other words, the pixel electrode 420 filled in the first contact opening 424 is also electrically connected to the auxiliary electrode 440 . It can be seen that the auxiliary electrode 440 of the present invention is at the same potential as the pixel electrode 420 , and a storage capacitor C _st is formed between the second overlapping region A ₂ of the auxiliary electrode 440 and the common wiring 430 .

Please refer to FIG. 4 again. In particular, since the drain electrode 418 and the auxiliary electrode 440 are patterned with the same photomask, in the exposure manufacturing process, when the photomask produces a displacement error, the first overlapping region A ₁ When it is smaller than the default value, the second overlapping area A ₂ is also smaller than the default value. Similarly, when the photomask produces a displacement error that makes the first overlapping area _A1 larger than the default value, the second overlapping area _A2 will also be larger than the default value. That is to say, the gate-drain parasitic capacitance C _gd and the storage capacitance C _st will increase or decrease simultaneously due to manufacturing process errors.

Moreover, from the expression of the feed-through voltage ΔVp (see formula (1)), it can be known that, when the voltage ΔVg and the liquid crystal capacitance C _LC are both constant values, if the gate-drain parasitic capacitance C _gd and the storage capacitance C _st Simultaneously increasing or decreasing in an appropriate proportion can maintain the feedthrough voltage ΔVp at a constant value. Please refer to FIG. 4 again, the present invention designs the shape and area of the auxiliary electrode 440 based on this principle, so that the variation of the storage capacitor C _st due to manufacturing process errors and the variation of the gate-drain parasitic capacitance C _gd There is an appropriate ratio between the quantities. In this way, even though the areas of the first overlapping region _A1 and the second overlapping region _A2 in each pixel region 408 are different due to manufacturing process errors, each pixel region 408 can still have the same feed-through voltage ΔVp .

FIG. 6 is a schematic top view of the thin film transistor array in the second embodiment of the present invention. Wherein, the thin film transistor array 600 of this embodiment is substantially the same as the thin film transistor array 400 of the first embodiment, so the differences will be described below.

Referring to FIG. 6 , the drain 412 of the thin film transistor 410 extends from the channel layer 414 to the bottom of the pixel electrode 420 along the direction q, and is electrically connected to the pixel electrode 420 through the first contact opening 424 . In addition, the auxiliary electrode 440 extends from above the common wiring 430 to one side of the common wiring 430 along the direction q. Wherein, the direction q is, for example, perpendicular to the extending direction of the first strip pattern 432 of the common wiring 430 , and the auxiliary electrode 440 extends from the first strip pattern 432 of the common wiring 430 to one side thereof along the direction q. It can be seen that, when the drain electrode 418 produces a displacement error in the direction q during the exposure manufacturing process, the auxiliary electrode 440 also produces a displacement error in the direction q. Therefore, the area of the second overlapping region _A2 between the auxiliary electrode 440 and the common wiring 430 will increase or decrease simultaneously in proportion to the area of the first overlapping region _A1 between the drain electrode 418 and the gate 412, Furthermore, the feedthrough voltage in each pixel region 408 is maintained at a constant value.

It is worth noting that although the variation of the storage capacitor C _st in this embodiment mainly depends on the variation of the overlapping area of the auxiliary electrode 440 and the first strip pattern 432 of the common wiring 430, the auxiliary electrode 440 can also partially overlap Above the second strip pattern 434 of the common wiring 430 to increase the storage capacitance C _st in each pixel region 408 . Similarly, in the first embodiment of the present invention, the auxiliary electrode 400 can also partially overlap the first strip pattern 432 of the common wiring 430, and those skilled in the art should be able to understand the details, and will not be described here. Draw additional drawings to illustrate.

In addition, the present invention also proposes a thin film transistor array in another embodiment, which can not only achieve the effects of the above embodiments, but also because the distance between the two electrodes forming the storage capacitor is small, it can be used without affecting Under the premise of keeping the storage capacitance value, the area of the auxiliary electrode is reduced, thereby increasing the aperture ratio of the thin film transistor array. Examples will be given below to illustrate it.

FIG. 7 is a schematic top view of a thin film transistor array in a third embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of the thin film transistor array in FIG. 7 along the line II-II'. Likewise, the thin film transistor array 700 of this embodiment is substantially the same as the thin film transistor array 400 of the first embodiment, so the differences will be described below.

Please refer to FIG. 7 and FIG. 8 at the same time. In addition to the elements shown in FIG. 4 , each pixel region 408 of the thin film transistor array 700 is also provided with a connection conductor layer 450, which is located above the auxiliary electrode 440 and the common wiring 430. And electrically connected to the common wiring 430 . In detail, the insulating layer 426 of this embodiment also has a plurality of second contact openings 425, and these second contact openings penetrate the insulating layer 426 and the gate insulating layer 422, exposing each pixel area 408. Part of the common wiring 430 , so that the connection conductor layer 450 disposed on the insulating layer 426 can be electrically connected to the common wiring 430 by filling the second contact opening 425 .

In addition, the connecting conductor layer 450 and the pixel electrode 720 can be fabricated with the same photomask. That is to say, the connecting conductor layer 450 is made of transparent conductive oxide like the pixel electrode 720 , for example. Of course, the connection conductor layer 450 and the pixel electrode 720 may also be patterned using different photomasks, which is not limited in the present invention.

Please continue to refer to FIG. 8 , it can be known from the above that the connection conductor layer 450 and the common wiring 430 have the same potential, and a storage capacitor C ₁ is formed between the connection conductor layer 450 and the auxiliary electrode 440 . In addition, as described in the first embodiment, the pixel electrode 720 fills the first contact opening 424 of the insulating layer 426 and is electrically connected to the auxiliary electrode 440, and a storage capacitor _C2 is formed between the auxiliary electrode 440 and the common wiring 430. . It can be known that the storage capacitor C _st in this embodiment is the equivalent capacitance obtained by connecting the storage capacitor C ₁ and the storage capacitor C ₂ in parallel.

Those skilled in the art should know that the capacitance of a capacitor is directly proportional to the area of the two electrodes of the capacitor and inversely proportional to the distance between the two electrodes of the capacitor. According to this principle, in this embodiment, since the distance between the connecting conductor layer 450 and the auxiliary electrode 440 and between the auxiliary electrode 440 and the common wiring 430 is short, compared with the thin film transistor array that also has the storage capacitance C _st Next, the thin film transistor array 700 of this embodiment can further reduce the area of the auxiliary electrode 440 so as to increase the aperture ratio of the thin film transistor array 700 .

FIG. 9 is a schematic top view of a thin film transistor array in a fourth embodiment of the present invention. Please refer to FIG. 9. It is worth mentioning that although the auxiliary electrode 440 and the connecting conductor layer 450 shown in FIG. 440 and the connecting conductor layer 450 may also be disposed above the first strip pattern 432 of the common wiring 430 . Certainly, the auxiliary electrode 440 and the connecting conductor layer 450 may also be disposed above the first strip pattern 432 and the second strip pattern 434 of the common wiring 430 (not shown in the figure), which is not limited in the present invention.

In the thin film transistor array of the present invention, auxiliary electrodes are mainly arranged in each pixel area, and the auxiliary electrodes and the common wiring form storage capacitors. When the thin film transistor array forms different gate-drain parasitic capacitances in each exposure area due to displacement errors caused by the photomask in the exposure manufacturing process, it will also form different storage capacitances in each exposure area at the same time . Wherein, when the gate-drain parasitic capacitance in a certain exposure area is larger/smaller than the gate-drain parasitic capacitance in the previous exposure area, the storage capacitance in this exposure area is also larger/smaller than that in the previous exposure area storage capacitance, and the variation of the storage capacitance is in a specific ratio to the variation of the gate-drain parasitic capacitance, so that the feed-through voltage in each exposure area maintains the same constant value, and then the thin film transistor array utilizing the present invention A display as a display panel can have excellent display quality.

In addition, the present invention also arranges a connection conductor layer in the thin film transistor array, and forms storage capacitors between the auxiliary electrodes and the common wiring and between the connection conductor layer and the auxiliary electrodes, so that the distance between the two electrodes forming these storage capacitors is shortened. , so as to reduce the area of the auxiliary electrode without changing the electrical performance of the storage capacitor, thereby increasing the aperture ratio of the thin film transistor.

To sum up, the present invention can solve the known problem of poor display quality of the display panel caused by the error in the exposure manufacturing process of the thin film transistor array, and will not cause adverse effects on the aperture ratio of the panel.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (14)

1. thin film transistor (TFT) array is characterized in that comprising:

Substrate has a plurality of pixel regions;

A plurality of thin-film transistors, be arranged at respectively respectively in this pixel region, and respectively this thin-film transistor comprises grid, channel layer, source electrode and drain electrode, wherein this channel layer is arranged between this source electrode, this drain electrode and this grid, and have first overlapping region between this drain electrode and this grid, form gate-to-drain parasitic capacitance (parasitic capacitance) between drain electrode and this grid so that be somebody's turn to do;

A plurality of pixel electrodes are arranged at respectively respectively in this pixel region, and wherein respectively this drain electrode extends to this pixel electrode below of correspondence from this channel layer upper edge one direction of correspondence, and is electrically connected to this pixel electrode;

Many shared distributions are arranged on this substrate, and the subregion of above-mentioned these shared distributions is positioned at above-mentioned these pixel electrode belows; And

A plurality of auxiliary electrodes, be arranged at respectively this interior pixel electrode below of this pixel region respectively, and respectively this auxiliary electrode is from this shared distribution top of correspondence, extend to a side of this shared distribution in the direction, wherein respectively this auxiliary electrode has second overlapping region with corresponding this shared wiring closet, and above-mentioned these auxiliary electrodes are electrically connected to respectively one of to be stated on the correspondence in these pixel electrodes, so that formation one storage capacitance (storagecapacitance) between this auxiliary electrode and corresponding this shared distribution respectively.

2. the thin film transistor (TFT) array according to claim 1, it is characterized in that in this pixel region respectively, this shared distribution has first strip pattern and second strip pattern, and the bearing of trend of this first strip pattern is different with the bearing of trend of this second strip pattern.

3. the thin film transistor (TFT) array according to claim 2 is characterized in that in this pixel region respectively, vertical this second strip pattern of this first strip pattern of this shared distribution.

4. the thin film transistor (TFT) array according to claim 2 is characterized in that in this pixel region respectively, and this auxiliary electrode is positioned partially at this first strip pattern and/or this second strip pattern top.

5. the thin film transistor (TFT) array according to claim 1 is characterized in that also comprising insulating barrier, is arranged between above-mentioned these pixel electrodes and above-mentioned these auxiliary electrodes, above-mentioned these source electrodes and above-mentioned these drain electrodes.

6. the thin film transistor (TFT) array according to claim 5, it is characterized in that this insulating barrier has a plurality of first contact windows, and above-mentioned these pixel electrodes are inserted above-mentioned these first contact windows respectively and be electrically connected to above-mentioned these the drain electrode with above-mentioned these auxiliary electrodes.

7. thin film transistor (TFT) array is characterized in that comprising:

Substrate has a plurality of pixel regions;

A plurality of thin-film transistors, be arranged at respectively respectively in this pixel region, and respectively this thin-film transistor comprises grid, channel layer, source electrode and drain electrode, wherein this channel layer is arranged between this source electrode, this drain electrode and this grid, and this drain electrode and this grid have first overlapping region, form the gate-to-drain parasitic capacitance between drain electrode and this grid so that be somebody's turn to do;

A plurality of pixel electrodes are arranged at respectively respectively in this pixel region, and wherein respectively this drain electrode extends to this pixel electrode below of correspondence from this channel layer upper edge one direction of correspondence, and is electrically connected to this pixel electrode;

Many shared distributions are arranged on this substrate, and the subregion of above-mentioned these shared distributions is positioned at above-mentioned these pixel electrode belows;

A plurality of bonding conductor layers are arranged at respectively respectively in this pixel region and are positioned at this shared distribution top, and above-mentioned these bonding conductor layers are electrically connected to above-mentioned these shared distributions respectively; And

A plurality of auxiliary electrodes, be arranged at respectively interior this pixel electrode and this bonding conductor layer below of this pixel region respectively, respectively this auxiliary electrode is from this shared distribution top of correspondence, extend to a side of this shared distribution in the direction, wherein respectively this auxiliary electrode has second overlapping region with corresponding this shared wiring closet, and above-mentioned these auxiliary electrodes are electrically connected to respectively one of to be stated on the correspondence in these pixel electrodes, so that respectively this auxiliary electrode with corresponding on one of state in these shared distributions between, and above-mentioned these bonding conductor layers and respectively form storage capacitance between this auxiliary electrode respectively.

8. the thin film transistor (TFT) array according to claim 7, it is characterized in that in this pixel region respectively, this shared distribution has first strip pattern and second strip pattern, and the bearing of trend of this first strip pattern is different with the bearing of trend of this second strip pattern.

9. described according to Claim 8 thin film transistor (TFT) array is characterized in that this first strip pattern of this shared distribution is perpendicular to this second strip pattern in this pixel region respectively.

10. described according to Claim 8 thin film transistor (TFT) array is characterized in that in this pixel region respectively, and this bonding conductor layer is positioned at this first strip pattern and/or this second strip pattern top.

11. the thin film transistor (TFT) array according to claim 7 is characterized in that also comprising insulating barrier, is arranged between above-mentioned these pixel electrodes and above-mentioned these auxiliary electrodes, above-mentioned these source electrodes and above-mentioned these drain electrodes.

12. the thin film transistor (TFT) array according to claim 11, it is characterized in that this insulating barrier has a plurality of first contact windows, and above-mentioned these pixel electrodes are inserted above-mentioned these first contact windows respectively and be electrically connected to above-mentioned these the drain electrode with above-mentioned these auxiliary electrodes.

13. the thin film transistor (TFT) array according to claim 12 is characterized in that also comprising gate insulation layer, is arranged at above-mentioned these drain electrodes, above-mentioned these source electrodes and above-mentioned these grids, and between above-mentioned these auxiliary electrodes and above-mentioned these shared distributions.

14. the thin film transistor (TFT) array according to claim 13, it is characterized in that this insulating barrier also has a plurality of second contact windows, and above-mentioned these second contact windows run through this insulating barrier and this gate insulation layer, and above-mentioned these bonding conductor layers are inserted above-mentioned these second contact windows respectively and be electrically connected to above-mentioned these shared distributions.

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