CN1992293A - Thin film transistor array substrate and method for manufacturing the same - Google Patents

Thin film transistor array substrate and method for manufacturing the same Download PDF

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Publication number
CN1992293A
CN1992293A CNA200610168254XA CN200610168254A CN1992293A CN 1992293 A CN1992293 A CN 1992293A CN A200610168254X A CNA200610168254X A CN A200610168254XA CN 200610168254 A CN200610168254 A CN 200610168254A CN 1992293 A CN1992293 A CN 1992293A
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layer
electrode
grid
data
thin
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CN1992293B (en
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朴容仁
吴载映
金秀浦
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LG Display Co Ltd
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LG Philips LCD Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
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Abstract

A thin film transistor array substrate and a method for manufacturing the thin film transistor array substrate are disclosed. Specifically, a thin film transistor array may be formed using a reduced number of masks. The thin film transistor substrate comprising gate lines and data lines crossing each other to define pixel regions on a substrate, a plurality of thin film transistors disposed adjacent to each crossing point of one of the gate lines and one of the data lines, each thin film transistor including a gate electrode protruded from the gate line, source electrode protruded from the data line and a drain electrode located adjacent the source electrode, a plurality of pixel electrodes on the pixel regions, and a plurality of transparent electrode patterns.

Description

Thin-film transistor array base-plate system and manufacture method thereof
The application requires the rights and interests at the korean patent application No.P2005-134119 of submission on December 29th, 2005, quotes this patent application in this mode by reference, as fully setting forth at this.
Technical field
The present invention relates to a kind of liquid crystal display (LCD) device, relate more specifically to the manufacture method of a kind of thin-film transistor array base-plate and this thin film transistor (TFT) array.
Background technology
Along with the development of information-intensive society, for the also constantly increase of demand of different display devices.In order to satisfy this demand, people have done a lot of effort for the flat-panel display device of research and development such as liquid crystal display (LCD) device, plasma display (PDP), electroluminescence demonstration (ELD) device, vacuum fluorescence demonstration (VFD) device etc.Wherein the flat-panel display device of some type just is being applied to various devices and/or is being used for showing the device of purpose.
Because therefore advantages such as the LCD device has that picture quality is good, in light weight, volume is thin and power consumption is little are beginning to adopt the substitute of LCD as cathode ray tube (CRT) aspect the mobile image display device.The application of the current various LCD that researching and developing not only relates to such as the mobile image display device of the display of notebook computer but also relates to and receiving and the televimonitor of display of broadcast signal.LCD successfully is applied to various image display devices depends on whether LCD can produce the high image quality that comprises high-resolution, high brightness and big display area, keep the characteristic of required light, thin and low-power consumption simultaneously.
LCD has the structure that comprises first substrate and second substrate, and wherein this first and second substrate is bonded together in the mode that forms the space between two substrates.Sealing fluid crystal layer in the space between first and second substrates.First substrate comprises many grid lines that the even distance of while each interval is set with a certain direction.With perpendicular to the direction of grid line many data wires of the even distance of each interval simultaneously.The cross section of data wire and grid line limits pixel region P.First substrate also comprises a plurality of pixel electrodes that are formed on each pixel region P, and a plurality of thin-film transistors (TFT) T of forming of the cross section between grid line and one of them data wire one of therein respectively.Apply data-signal on each data wire in response to the signal that imposes on one of them grid line to one of them pixel electrode.
Although not shown, second substrate can comprise and is used to stop that incident illumination is mapped to the black matrix layer in the zone except that pixel region P.Second substrate also can comprise R, G and the B color filter layer that is formed on corresponding to the zone of each pixel region P, and configuration is used to reproduce tone.Public electrode can be arranged on the color filter layer, and it is used for reproduced image.
In above-mentioned LCD, make the liquid crystal that is arranged in the liquid crystal layer between first and second substrates in each pixel region be orientated with a certain direction by the electric field that between pixel electrode and public electrode, produces.Orientation based on liquid crystal layer is controlled the light quantity of passing through liquid crystal layer, thus suitable display image.
LCD with above-mentioned drive principle is called twisted-nematic (TN) mode LCD.Except this TN mode LCD, also researched and developed in-plain switching (IPS) mode LCD that adopts horizontal component of electric field.In the IPS mode LCD, in order to produce copline electric field (horizontal component of electric field), on each pixel region of first substrate, form pixel electrode and public electrode, make pixel electrode and public electrode extend parallel to each other.By the copline electric field liquid crystal layer is orientated with a certain direction.
Describe among the above-mentioned LCD hereinafter with reference to Fig. 1 and Fig. 2 and to form TFT in the grid line on first substrate and the cross part office between the data wire and to form the structure of pixel electrode and the process that is used to form TFT and pixel electrode at pixel region.Fig. 1 is the sectional view according to the tft array substrate of prior art.Fig. 2 is the method flow diagram that is used to make according to the tft array substrate of prior art.
As shown in Figure 1, each TFT of thin-film transistor array base-plate comprises the grid 11 that stretches out from the grid line (not shown).Above grid 11, semiconductor layer 13 is set, makes between grid 11 and semiconductor layer 13, gate insulation layer 12 to be set with island.Each TFT also comprises two opposite sides and the source electrode 14a spaced apart and the 14b that drains that is separately positioned on semiconductor layer 13.Stretch out formation source electrode 14a from the data wire (not shown).Semiconductor layer 13 has stepped construction, and it comprises following amorphous silicon layer 13a and is arranged on last doped layer (n on the amorphous silicon layer 13a except that channel region +Layer) 13b.This doped layer 13b contacts with the lower surface of source electrode 14a and drain electrode 14b.
Pixel electrode 16 is set makes it contact with the part upper surface of drain electrode 14b among each TFT.Between pixel electrode 16 and each source electrode 14a and drain electrode 14b, form passivation layer 15 as interlayer.The said structure that forms on first substrate 10 is called " tft array ".Now with reference to Fig. 2 the method for making this tft array is described in conjunction with a TFT.Fig. 2 is the flow chart that is used to make according to the technology of the tft array of prior art.
As depicted in figs. 1 and 2, in square frame 11S, depositing metal layers above first substrate 10 is optionally removed this metal level then with formation grid line and grid 11, thereby is made grid 11 stretch out from grid line.Then, deposition gate insulation layer 12 above the upper surface of first substrate 10 that comprises grid 11.
Subsequently, in square frame 12S, sequential aggradation semiconductor layer 13 and metal level on the upper surface of gate insulation layer 12 are optionally removed semiconductor layer 13 and metal level then to form data wire (not shown) and source electrode 14a and drain electrode 14b.Semiconductor layer 13 has the stepped construction that comprises following amorphous silicon layer 13a and last doped layer 13b.Because semiconductor layer 13 is arranged on the below of source electrode 14a and drain electrode 14b, therefore semiconductor layer 13 and metal level composition together when forming source electrode 14a and drain electrode 14b.Optionally diffraction exposure technology is carried out in the zone that limits between source electrode 14a and drain electrode 14b, thereby removed the doped layer 13b of metal level and semiconductor layer 13 from this zone.The remainder of semiconductor layer 13 is defined as channel region.
On the upper surface of the gate insulation layer 12 that comprises data wire, source electrode 14a and drain electrode 14b, passivation layer 15 is set then.In square frame 13S, form the passivation layer hole subsequently to expose the part upper surface of drain electrode 14b.Thereafter, deposit transparent electrode material above the entire upper surface of passivation layer 15 covers the passivation layer hole thereby fill out by transparent electrode material.At square frame 14S, optionally remove transparent electrode material then to form pixel electrode 16.
But, have some shortcomings according to the above-mentioned tft array substrate of prior art.In order to form tft array substrate and to be positioned at TFT transistor array on the tft array substrate, must adopting at least, the four-wheel mask process forms grid line, form semiconductor layer and data wire, formation passivation layer hole and form pixel electrode.
These masks that required film composition is adopted are very expensive.And, use mask at every turn, must carry out various technologies such as the photoresist film etching deposit film after deposition mask to be patterned, coating photoresist film, exposure, develop this photoresist film and the employing development.After finishing etch process, also must carry out such as the additional process that cleans.For this reason, use mask to cause cost increase, processing time to increase and reduced productivity ratio.
Summary of the invention
The invention provides a kind of thin-film transistor array base-plate and manufacture method thereof, it has eliminated one or more technical problems of being brought by the limitation of prior art and shortcoming basically.Can adopt the mask process that reduces number of times to make thin-film transistor array base-plate.
Other advantages of the present invention, purpose and a feature part will be illustrated at following specification, and a part becomes apparent when studying hereinafter for those of ordinary skill in the art or understands by implementing the present invention.Purpose of the present invention and other advantages can be realized and acquisition by the structure that particularly points out in written specification and claims and accompanying drawing.
In first scheme, a kind of thin-film transistor array base-plate comprises intersected with each other to limit the grid line and the data wire of the pixel region on the substrate.With a plurality of thin-film transistors of the adjacent setting in crosspoint of each grid line and a data wire, source electrode that each thin-film transistor comprises the grid that stretches out from grid line, stretch out from data wire and the drain electrode adjacent with source electrode.A plurality of pixel electrodes on pixel region are adjacent with drain electrode.A plurality of transparent electrode patterns and the adjacent setting of data wire.Source electrode stretches out from data wire.
In alternative plan, a kind of thin-film transistor array base-plate comprises many grid lines and many data wires that intersect with described many grid lines.Many grid lines wherein one with many data wires wherein one intersect on substrate, to form pixel region.Be basically parallel to grid line many common wires are set.Adjacent with the crosspoint of grid line and data wire a plurality of thin-film transistors are set, wherein each thin-film transistor comprise the grid that stretches out from grid line, the source electrode that stretches out from data wire and the drain electrode adjacent with source electrode.On at least one of described drain electrode, a plurality of first storage electrodes are set.Be arranged on a plurality of pixel electrodes that extend from one first storage electrode in each pixel region.Designing a plurality of transparent electrode patterns makes it contact separately and with source electrode with first storage electrode.At each pixel region a plurality of public electrodes and described public electrode and pixel electrode being set is arranged alternately.
In third party's case, a kind of manufacture method of thin-film transistor array base-plate is included in and forms grid line and grid on the substrate.Deposition grid metal level, semiconductor cambium layer and data metal layer on the surface of the substrate that comprises grid line and grid.Remove at least a portion data metal layer, semiconductor cambium layer and gate insulation layer, extend thereby make data wire be basically perpendicular to grid line.At the surface of the substrate that comprises data wire deposit transparent electrode layer.Remove at least a portion transparent electrode layer, data metal layer and semiconductor cambium layer to desired depth.
In cubic case, a kind of manufacture method of thin-film transistor array base-plate is included in and forms grid line, grid and grid welding disk pattern on the substrate.Above the upper surface of substrate, deposit gate insulation layer, semiconductor cambium layer and data metal layer.Optionally remove at least a portion data metal layer, semiconductor cambium layer and gate insulation layer and be basically perpendicular to the data wire that grid line extends with formation.Semiconductor cambium layer zone keeps.Deposit transparent electrode layer above the upper surface of substrate.Remove transparent electrode layer, data metal layer and semiconductor cambium layer to desired depth, thereby semiconductor layer and source electrode, drain electrode are set in each semiconductor cambium layer zone.
In the 5th scheme, a kind of manufacture method of thin-film transistor array base-plate is included in grid line and the common wire that extends along same direction substantially is set on the substrate.Public electrode, grid and grid welding disk pattern also are set on substrate.On the surface of the substrate that comprises grid line, common wire, public electrode, grid and grid welding disk pattern, deposit gate insulation layer, semiconductor cambium layer and data metal layer.Optionally remove at least a portion data metal layer, semiconductor layer cambium layer and gate insulation layer and be basically perpendicular to the data wire that grid line extends with formation.Form the zone by optionally removing the formation semiconductor layer.At the surface of the substrate that comprises data wire deposit transparent electrode layer.Remove at least a portion transparent electrode layer, data metal layer and semiconductor cambium layer to desired depth.The removal of at least a portion transparent electrode layer makes to form at semiconductor layer and forms semiconductor layer, source electrode and drain electrode in the zone.
By studying following accompanying drawing and detailed description, other system of the present invention, method, feature and advantage will or become apparent to those skilled in the art.The present invention be intended to protect all be contained in the specification, comprise within the scope of the present invention, by every other system, method, feature and advantage following claim protection and that limit by following claim.All the elements in this part should not be considered the restriction for these claims.Below with reference to further scheme of execution mode discussion and advantage.
Should be understood that above-mentioned general description that the present invention is carried out and following detailed description are exemplary with indicative, and aim to provide as the described further explanation of the present invention of claims.
Description of drawings
Comprise the accompanying drawing that is used to provide the further understanding of the present invention and incorporated composition the application part, it shows embodiments of the present invention, and is used from explanation principle of the present invention with specification one.In the accompanying drawings:
Figure 1 shows that the sectional view of thin-film transistor (TFT) array base palte according to prior art;
Figure 2 shows that flow chart according to the manufacture method of the tft array substrate of prior art;
Figure 3 shows that the flow chart of method that is used to form the tft array of tft array substrate according to an execution mode;
Figure 4 shows that plane graph according to the tft array substrate of first execution mode;
Figure 5 shows that line I-I ', the II-II ' along Fig. 4, the cross-sectional view of III-III ';
Fig. 6 A to Fig. 6 C is depicted as the plane graph of making the treatment step of tft array substrate according to first execution mode;
Fig. 7 A to Fig. 7 E is depicted as the sectional view of making the treatment step of tft array substrate according to first execution mode;
Figure 8 shows that plane graph according to the tft array substrate of second execution mode;
Figure 9 shows that the cross-sectional view of IV-IV ', V-V ', VI-VI ' and VII-VII ' line along Fig. 8;
Figure 10 A to Figure 10 D is depicted as the plane graph of making the treatment step of tft array substrate according to second execution mode;
Figure 11 shows that the schematic diagram that forms the method for passivation layer on according to the tft array substrate of execution mode; And
Figure 12 shows that the schematic diagram that forms the other method of passivation layer on according to the tft array substrate of execution mode.
Embodiment
Below embodiments of the present invention will be described.These execution modes are in the LCD testing fixture and adopt the LCD inspection method of this testing fixture relevant, embodiment shown in the drawings.As far as possible, in whole accompanying drawing, use same Reference numeral for identical or similar parts.Here, phrase " is connected to " meaning that is defined as or indirect connection direct by one or more intermediate member.These intermediate members can not only comprise hardware but also comprise software based on parts.
Figure 3 shows that the flow chart of method that is used to form the tft array of thin-film transistor (TFT) array base palte according to an execution mode.As shown in Figure 3, according to the tft array substrate manufacture method, in square frame 100S, first mask that is used to form grid line and grid obtains tft array.In square frame 110S, adopt second mask to form semiconductor layer and data line layer.In square frame 120S, adopt the raceway groove in the 3rd mask formation pixel electrode and the semiconductor layer.
According to an execution mode of tft array substrate manufacture method, on data line layer, directly be provided with or the formation pixel electrode, and between data line layer and pixel electrode layer, do not insert passivation layer.Therefore, do not need to adopt in addition the technology that forms the passivation layer hole.Reduced the mask number of times that in manufacturing process, adopts like this.When the composition pixel electrode, limit raceway groove.Therefore do not need to adopt diffraction exposure technology required when in traditional handicraft, forming raceway groove, thereby reduced the number of times of exposure technology.Above-mentioned tft array substrate manufacture method is described and the structure of the tft array that forms according to this manufacture method below with reference to various execution modes as described below.
First execution mode of the present invention relates to a kind of tft array substrate of in-plain switching (IPS) mode LCD that the three-wheel mask forms and manufacture method of this tft array substrate of adopting.Figure 4 shows that plane graph according to the tft array substrate of first embodiment of the invention.Figure 5 shows that line I-I ', the II-II ' along Fig. 4, the cross-sectional view of III-III '.Here, line I-I ' extend past TFT, line II-II ' extend past holding capacitor and common wire, and line III-III ' extend past data pads.
In following explanation, will be defined as according to the core of the tft array substrate of an execution mode and carry out the viewing area that image shows, and will partly be defined as the welding disking area that applies certain drive signal around the tft array substrate of viewing area.In the viewing area, limit a plurality of pixel regions.
As shown in Figure 4 and Figure 5, according to the tft array substrate of first execution mode, in the viewing area, first substrate 100 comprises many grid lines 101 and many data wires 102, and the cross section of its grid line 101 and data wire 102 on substrate 100 limits pixel region.In the viewing area, substrate 100 also comprises all a plurality of TFT of the cross part office between grid line 101 and data wire 102, and each TFT comprises the grid 101a that stretches out from a grid line 101.Source electrode 102a stretches out from data wire 102 the cross part office between grid line 101 and data wire 102.The drain electrode 102b stretch out from data wire 102 in the cross part office between grid line 101 and data wire 102, the while with source electrode 102a separately.Substrate also is included in the common wire 111 that viewing area and each grid line 101 be arranged in parallel.One of the first storage electrode 111a and common wire 111 are whole to be provided with, and is arranged in the pixel region, and its width is greater than the width of common wire simultaneously.Public electrode 111b all is arranged in one of pixel region, makes this public electrode 111b to point shape from one first storage electrode 111a bifurcated.In other words, public electrode 111b extends out from one of first storage electrode 111a separately.Public electrode 111b is basically perpendicular to grid line 101 and common wire 111.
Pixel electrode 103 is arranged alternately with public electrode 111b, and the second storage electrode 103a is set with a pixel electrode 103 becomes integral body, simultaneously by the local covering in the zone that one first storage electrode 111a is set.
Substrate 100 also comprises welding disking area.In welding disking area, an end of a grid line 101 in a zone that limits the grid pad is provided with grid welding disk pattern 121.One end of a data wire 102 in a zone that limits data pads is provided with data pads pattern 122.Stacked data pattern layer 117a and the grid pad end 123 of being provided with above each grid welding disk pattern 121.Data pads end 133 is set above each data pads pattern 122.Grid pad end 123 and data pads end 133 are made of the transparent electrode material that is positioned at one deck with pixel electrode 103.
Transparent electrode pattern 103b is set contacts with drain electrode 102b with the source electrode 102a of each TFT, this source electrode 102a and drain electrode 102b are positioned at the below of transparent electrode pattern 103b.The drain electrode 102b of stored pattern 102c and each TFT is one-body molded.Thereby each second storage electrode 103a is formed on a stored pattern 102c upward contacts with each other them.
This data pattern layer 117a and a stored pattern 102c become one simultaneously also to form data pattern layer 117a below a pixel electrode 103.Each transparent electrode pattern 103b is formed on the data wire 102.Transparent electrode pattern 103b is made of the material the same with pixel electrode 103.Simultaneously with reference to Fig. 4 and Fig. 5, can find in most of zone of data wire to be formed, pixel electrode and holding capacitor to be used to form the data metal layer of data wire and be used to form the transparent electrode layer of pixel electrode with lamination pattern form composition.
Transparent electrode pattern 103b can be set on data wire 102, and can not need to be arranged on the data pattern layer 117a of the below of pixel electrode 103.This can be used for the shape of the opening of second mask of composition data wire 102 or masked portion and be used for the opening of the 3rd mask of composition pixel electrode or the shape of masked portion realizes by change.Because the 3rd mask should limit raceway groove, so the 3rd mask should have the light transmission part (when the 3rd mask is made of the photoresist film with eurymeric photoresistance characteristic) corresponding to each channel part of semiconductor layer.When the 3rd mask was made of the photoresist film with minus photoresistance characteristic, this mask should have shading light part.When the 3rd mask that has a said structure when employing is carried out composition, limit a source electrode 102a and a drain electrode 102b respectively in data pattern layer 117a part corresponding to the semiconductor layer 104 of each TFT.Therefore, remove amorphous silicon layer 116a from channel region corresponding to semiconductor layer 104.
As mentioned above, directly above the data line layer behind the composition, form transparent electrode layer, and need not above the data line layer behind the composition, to form passivation layer.Can in the technology of etching transparent electrode layer, limit the raceway groove of semiconductor layer 104 like this.Therefore, can form source electrode 102a in each TFT zone, drain electrode 102b, transparent electrode pattern 103b and the second storage electrode 103a simultaneously.
As shown in Figure 5, not only on grid line 101, grid 101a, the first storage electrode 111a and grid welding disk pattern 121 but also on the data pads zone, form gate insulation layer 114a.Stacked semiconductor layer 104 above gate insulation layer 114a.Semiconductor layer 104 has the amorphous silicon layer of comprising 115a and doped layer (n +Layer) 116a or 126 stepped construction.Doped layer 126 can comprise the first doped layer 126a and the second doped layer 126b, removes described two doped layers at channel region.In order to expose the predetermined portions of grid welding disk pattern 121, from remove data pattern layer 117a, doped layer 116a, amorphous silicon layer 115a and the gate insulation layer 114a of preset width corresponding to the zone of the predetermined portions of each grid welding disk pattern 121.The transparent electrode material that employing is used for the expose portion at least of covering gate welding disk pattern 121 forms each grid pad end 123.
Each first storage electrode 111a and the stored pattern 102c and the second storage electrode 103a that are formed on first storage electrode 111a top form holding capacitor together, and stored pattern 102c contacts with the second storage electrode 103a.Between the first storage electrode 111a and stored pattern 102c, insert gate insulation layer 114a.In one embodiment, use oxide that passivation layer 125 is set above the superiors of substrate 100.
Although not shown, can color filter array be set at the second substrate (not shown) towards substrate 100.Second substrate comprises and is formed for covering except that the black matrix layer of pixel region with exterior domain and TFT.Color filter layer is arranged in the pixel region at least, and above the upper surface that comprises second substrate of deceiving matrix layer and color filter layer cover layer is set.Substrate 100 can engage with second substrate under the state of sealing fluid crystal layer between the substrate 100 and second substrate.
Fig. 6 A to Fig. 6 C is depicted as the plane graph of making the treatment step of tft array substrate according to first execution mode.Fig. 7 A to Fig. 7 E is depicted as the sectional view of making the treatment step of tft array substrate according to first execution mode.
Shown in Fig. 6 A and Fig. 7 A, deposition grid metal level above the entire upper surface of substrate 100 at first.The entire upper surface of grid metal level above apply first photoresist film (not shown) thereafter.Adopt the first mask (not shown) that this first photoresist film is carried out exposure and developing process then, thus this first photoresist film of composition.Subsequently, adopt the photoresist film behind this composition to carry out composition technology.Selective removal grid metal level, thereby form many grid line 101, many edges of extending and be basically parallel to the common wire 111 that each grid line 101 extends, and to point shape from a grid line 101 or the public electrode 111b that common wire 111 bifurcateds come out along a direction.In other words, public electrode 111b can extend separately from a grid line 101, a common wire 111 or first a storage electrode 111a.Public electrode 111b is basically perpendicular to grid line 101 and common wire 111.
Compare with other parts of common wire 111, every common wire 111 limits the first storage electrode 111a thus in the partial width increase corresponding to pixel region.The first storage electrode 111a and the second storage electrode 103a and insert the first storage electrode 111a and the second storage electrode 103a between insulating barrier form holding capacitor (shown in Fig. 6 C).The second storage electrode 103a is with to be arranged on one-body molded pixel electrode and the common wire 111 of making of pixel electrode on the common wire 111 (representing with " 103 " in Fig. 7 C) overlapping.Common wire 111, the first storage electrode 111a and public electrode 111b are an integral body.
In above-mentioned composition technology, the part that grid line 101 from each pixel region also is set is stretched out grid 101a.Simultaneously, form grid welding disk pattern 121 at every grid line 101.Subsequently, shown in Fig. 7 A, sequential aggradation gate insulation layer 114, amorphous silicon layer 115, doped layer (n above the entire upper surface of the substrate 100 that comprises element 101,101a, 111,111a and 111b +Layer) 116 and data metal layer 117.
Shown in Fig. 6 B and 7B, above the entire upper surface of data metal layer 117, apply the second photoresist film (not shown).Adopt the second mask (not shown) that this second photoresist film is carried out exposure and developing process then, thus this second photoresist film of composition.Subsequently, the photoresist film behind the employing composition is carried out composition technology, thereby optionally removes data metal layer 117, thereby forms data pattern layer 117a.Adopt data pattern layer 117a as mask, dry etching is arranged on the doped layer 116 and the amorphous silicon layer 115 of the below of data pattern layer 117a, and the etch-gate insulating barrier 114 subsequently.According to this technology, form dopant patterns layer 116a, amorphous silicon pattern layer 115a, gate insulation patterned layer 114a, it has basically and the same width of data pattern layer 117a.Perhaps, width can be similar with data pattern layer 117a (considering the side taper).
Data pattern layer 117a can be arranged on the zone of data wire to be formed, the zone that comprises the semiconductor layer of source electrode and drain electrode to be formed, around zone and each data pads zone of each grid welding disking area.The data pattern layer 117a that is arranged in each data pads zone partly is called data pads pattern 122.
In the etch process that adopts second mask, form the data wire 102 that extends perpendicular to grid line 101, thus and qualification pixel region.At an end of every data wire 102, promptly in each data pads zone, form data pads pattern 122 simultaneously.In addition, forming pattern in each TFT zone makes this pattern stretch out from a data wire 102.In addition, another pattern being set in each holding capacitor zone makes the part of this pattern and a part that is arranged at the public electrode 111b in holding capacitor zone be arranged alternately.In above-mentioned technology, expose the predetermined portions of the upper surface that is arranged on the grid welding disk pattern 121 in each grid welding disking area.Also expose the upper surface of every common wire 111.
Shown in Fig. 7 C, deposit transparent electrode layer above the data pattern layer 117a that comprises data pads pattern 122.Can above the upper surface of transparent electrode layer, apply the 3rd photoresist film (not shown) then.Adopt the 3rd mask (not shown) that the 3rd photoresist film is carried out exposure and developing process, thus composition the 3rd photoresist film.Subsequently, the 3rd photoresist film behind the employing composition is carried out composition technology.Optionally remove transparent electrode layer, thereby form transparent electrode pattern 103b and pixel electrode 103 on the data pattern layer 117a in each pixel region.At channel region, be arranged on the grid pad end 123 on the partial data patterned layer 117a on each grid welding disk pattern 121 and be positioned on each data pads pattern 122 and on the zone of the data pads end 133 of data pads pattern 122, can not form transparent electrode pattern 103b and pixel electrode 103.The part and the above-mentioned part that is formed on the public electrode 111b in the pixel region that are arranged on the data pattern layer 117a in each pixel region are arranged alternately, and be simultaneously overlapping with the first storage electrode 111a part that is arranged on pixel region.
In order to protect the surface of grid line and common wire 111, can cover grid line and the common wire 111 that is in exposed state by another transparent electrode pattern that forms when the composition transparent electrode layer.This transparent electrode pattern is not shown in the accompanying drawings.
Adopt transparent electrode pattern 103b and pixel electrode 103 as mask, shown in Fig. 6 C and 7D, according to the partial data patterned layer 117a and the doped layer 116a of etch process removal corresponding to each channel region.After finishing etch process, can be defined as both sides the source electrode 102a and the drain electrode 102b of each interval simultaneously that is arranged on channel region with staying partial data patterned layer 117a on each grid 101a.Part doped layer 126 (126a and 126b) and the amorphous silicon layer integral body of staying the below of partial data patterned layer 117a are defined as semiconductor layer 104.In this embodiment, source electrode 102a has U type shape, and the raceway groove that is limited between source electrode 102a and the drain electrode 102b also has U type shape.This shape is used to protect the channel region area of increase.In alternate embodiments, channel region can have such as L shaped or "-" shape.
Shown in Fig. 7 E, can pass through O 2 Plasma treatment substrate 100 is to form passivation layer (not shown) (for example, " 125 " among Fig. 9), and this passivation layer is by the oxide (SiO that is positioned at the element top that forms on the substrate 100 2) constitute.The design passivation layer is isolated with the opening channel part and the external environment of protection semiconductor layer 104.In one embodiment, passivation layer 125 thickness are about 200 to 500 dusts.By single substrate is loaded in the vacuum chamber, then this substrate is carried out the oxygen plasma body technology and form this passivation layer.Alternatively, can be loaded in the reacting furnace by the box or the similar devices that will transport a plurality of substrates, then a plurality of substrates be carried out oxygen plasma body technology and thermal oxidation technology formation passivation layer.Above passivation layer 125, form the alignment films (not shown) then.Grind this oriented film then.
As mentioned above, adopt the manufacture method of three-wheel mask acquisition according to the tft array substrate of first execution mode.In the manufacture method of tft array substrate, it is not requisite forming passivation layer between data line layer and pixel electrode.Therefore, the passivation layer hole formation technology that relates in 4-wheel mask process becomes in the present embodiment and there is no need.Form pixel electrode and make them contact, and adopt the shape of pixel electrode to limit each channel region with data line layer.Therefore, can under the situation that does not adopt other diffraction exposure technologys, adopt aforesaid three-wheel mask to form tft array.
Second execution mode of the present invention relates to tft array substrate and the manufacture method thereof that is used for twisted-nematic (TN) mode LCD, adopts the three-wheel mask to form this tft array substrate here.
Figure 8 shows that plane graph, Figure 9 shows that along the sectional view of line IV-IV ', V-V ', VI-VI ' and the VII-VII ' of Fig. 8 according to the tft array substrate of second execution mode.Here, line IV-IV ' extend past TFT, line V-V ' extend past holding capacitor, line VI-VI ' extend past grid pad, and line VII-VII ' extend past data pads.
As Fig. 8 and shown in Figure 9, in the viewing area, comprise many grid lines 101 and many data wires 102 according to the tft array substrate of second embodiment of the invention, the cross section of grid line 101 and data wire 102 limits pixel region on substrate 100.In this viewing area, substrate 100 also comprises a plurality of TFT.TFT comprises grid 101a, source electrode 102a and drain electrode 102b, wherein grid 101a stretches out from a grid line 101 of the cross part office between grid line 101 and data wire 102, source electrode 102a stretches out from the data wire 102 of the cross part office between grid line 101 and the data wire 102, and drain electrode 102b stretches out while and source electrode 102a each interval from the data wire 102 of the cross part office between grid line 101 and data wire 102.Substrate 100 also comprises: be formed on a pixel electrode 103 in the pixel region in the viewing area, make this pixel electrode 103 under the contacted situation of upper surface of pixel electrode 103 and the drain electrode 102b of TFT in presumptive area be arranged on the grid line relevant with pixel electrode 103 on a grid line overlapping; And the layer that all is formed on and forms data wire is positioned at the stored pattern 102c on one deck, its be arranged on pixel electrode 103 and and the overlapping last grid line of pixel electrode between with as interlayer.
Substrate 100 also comprises in welding disking area: the grid welding disk pattern 121 that forms of an end of a grid line 101 in a zone that limits the grid pad respectively; And the data pads pattern 122 that forms of an end of a data wire 102 in limiting a zone of data pads respectively.Stacked data pattern layer 117a and the grid pad end 123 of being provided with above each grid welding disk pattern 121.Above each data pads pattern 122, form data pads end 133.Grid pad end 123 and data pads end 133 are made of the transparent electrode material that is positioned at one deck with pixel electrode 103.
As shown in Figure 9, form the source electrode 102a of transparent electrode pattern 103b with the TFT that covers independent data wire 102 and be associated with data wire 102.On the upper surface of pixel region drain electrode 102a, form each pixel electrode 103.In Fig. 8, transparent electrode pattern is not shown.Forming transparent electrode pattern 103b on every data wire 102 can be not necessarily.Therefore, only need on source electrode 102a and drain electrode 102a and pixel region, to provide transparent electrode pattern 103b and pixel electrode 103.This is used for the shape of the opening of second mask of composition data wire 102 and shaded portions and is used for the opening of composition pixel electrode the 3rd mask and the shape of shaded portions realizes by change.
Because the 3rd mask should limit raceway groove, so the 3rd mask has the light transmission part (when the 3rd mask is made of the photoresist film with eurymeric photoresistance characteristic) corresponding to each channel part of semiconductor layer.When the 3rd mask was made of the photoresist film with minus photoresistance characteristic, this mask can have shading light part.When the 3rd mask that has a said structure when employing is carried out composition, partly limit a source electrode 102a and a drain electrode 102b at data pattern layer 117a corresponding to the semiconductor layer 104 of each TFT.Remove amorphous silicon layer 116a from channel region corresponding to semiconductor layer 104.
In the said structure according to second execution mode, holding capacitor comprises by last first storage electrode that grid line limited that is associated with pixel region.Limit second storage electrode by stored pattern stacked together and pixel electrode 103, this second storage electrode and a last grid line are overlapping simultaneously.Limit dielectric layer by gate insulation layer 114a, amorphous silicon layer 115a and the doped layer 126c that is inserted between first and second storage electrodes.Above the superiors of substrate 100, passivation layer 125 is set.
In order to obtain the raceway groove of semiconductor layer to be limited in the technology of etching transparent electrode layer 104, directly above the data line layer behind the composition, form transparent electrode layer, and above the data wire behind the composition, do not form passivation layer.Therefore, can be formed on source electrode 102a in each TFT zone, drain electrode 102b, transparent electrode pattern 103b and the second storage electrode 103a simultaneously.
As shown in Figure 9, not only form gate insulation layer 114a at grid line 101, grid 101a and grid welding disk pattern 121 but also on the data pads zone.Stacked semiconductor layer 104 on gate insulation layer 114a.Semiconductor layer 104 has the amorphous silicon layer of comprising 115a and doped layer (n +Layer) 116a or 126 stepped construction.Doped layer 126 can comprise the first doped layer 126a and the second doped layer 126b, removes described two doped layers at channel region.
As shown in Figure 9, can adopt transparent electrode material on grid welding disk pattern 121, directly to form each grid pad end 123, make grid pad end 123 contact with the upper surface of grid welding disk pattern 121.Alternatively, in order to expose the predetermined portions of grid welding disk pattern 121, from zone, remove data pattern layer 117a, doped layer 116a, amorphous silicon layer 15a and the gate insulation layer 114a of preset width corresponding to the part of each grid welding disk pattern 121.Adopt transparent electrode material to form the expose portion that each grid pad end 123 makes its covering gate welding disk pattern 121.
Form color filter array at the second substrate (not shown) towards substrate 100.Second substrate comprise be formed for covering except that pixel region with the black matrix of exterior domain and TFT, pixel region color filter layer is set and comprising black matrix and color filter layer second substrate entire upper surface above the cover layer that forms.Substrate 100 can engage with second substrate under the state of sealing fluid crystal layer between the substrate 100 and second substrate.
The technology of making tft array substrate according to second embodiment of the invention below will be described.Figure 10 A to Figure 10 D is depicted as the plane graph of making the treatment step of tft array substrate according to second execution mode.
Shown in Figure 10 A,, at first above the upper surface of substrate 100, deposit the grid metal level according to this method.Adopt the first mask (not shown) optionally to remove the grid metal level with grid 101a that forms many grid lines 101 that extend along a direction, stretches out from the part of grid line 101 at each pixel region and the grid welding disk pattern 121 that is provided with at each grid line 101.
Sequential aggradation gate insulation layer 114a, amorphous silicon layer 115a, doped layer (n above the upper surface of the substrate 100 that comprises element 101,101a and 121 +Layer) 116a and data pattern layer 117a.
Shown in Figure 10 B, thereby adopt optionally etching data metal layer of the second mask (not shown) 117 to form data pattern layer 117a.Adopt data pattern layer 117a as mask, dry etching is arranged on the doped layer 116 and the amorphous silicon layer 115 of data pattern layer 117a below, and the etch-gate insulating barrier 114 subsequently.According to this technology, form dopant patterns layer 116a, amorphous silicon pattern layer 115a and gate insulation patterned layer 114a, it has basically and the similar width of data pattern layer 117a.
Data pattern layer 117a can be arranged on the zone of data wire to be formed, zone and each data pads zone that comprises the semiconductor layer of source electrode and drain electrode to be formed.The data pattern layer 117a that is arranged in each data pads zone partly is called data pads pattern 122.
Shown in Figure 10 C, deposit transparent electrode layer above the data pattern layer 117a that comprises data pads pattern 122.Adopt the 3rd mask (not shown) optionally to remove transparent electrode layer, thereby on data pattern layer 117a, form transparent electrode pattern 103b and pixel electrode 103.At channel region, at the grid pad end 123 on each grid welding disk pattern 121 and be positioned on each data pads pattern 122 and on the data pads end 133 of data pads pattern 122, do not form transparent electrode pattern 103b and pixel electrode 103.
In order to protect the surface of grid line 101, can cover the grid line 101 that is in exposed state by formed another transparent electrode pattern when the composition transparent electrode layer.Omit in the accompanying drawings this transparent electrode pattern is shown.
Adopt pixel electrode 103, transparent electrode pattern 103b and partial data patterned layer 117a as mask, according to the doped layer 116a of etch process removal corresponding to each channel region.The partial data patterned layer 117a that will stay after finishing etch process on each grid 101a is defined as both sides and the source electrode 102a of each interval and the 102b that drains that is arranged on channel region.Part doped layer 126 (126a and 126b) and the amorphous silicon layer integral body of staying partial data patterned layer 117a below are defined as semiconductor layer 104.In this embodiment, source electrode 102a has U type shape, and the raceway groove between source electrode 102a and drain electrode 102b also has U type shape.This shape is used to guarantee the channel region area that increases.Certainly, channel region can have other shapes such as L shaped or "-" shape.
Shown in Figure 10 D, can pass through O 2 Plasma treatment substrate 100 is to form by oxide (SiO 2) the oxide layer (not shown) that constitutes, this oxide layer is positioned at the top of the element that forms on the substrate 100.This oxide layer can be used as passivation layer 125.Especially, can protect the opening channel part of semiconductor layer 104 and external environment to isolate by oxide layer.
Form the passivation layer 125 that thickness is about 200 to 500 dusts.By single substrate is loaded in the vacuum chamber, the oxygen plasma body technology to this substrate carry out desired forms this passivation layer then.Alternatively, can be loaded in the reacting furnace by the box or the similar devices that will transport a plurality of substrates, then a plurality of substrates be carried out oxygen plasma body technology and thermal oxidation technology formation passivation layer.Above passivation layer 125, form the alignment films (not shown), and grind this alignment films.
Adopt the manufacture method of three-wheel mask acquisition according to the tft array substrate of second execution mode.In the manufacture method of tft array substrate, it is not requisite forming passivation layer between data line layer and pixel electrode.Therefore, can skip the passivation layer hole that relates in the 4-wheel mask process and form technology.Form pixel electrode in addition and make them contact, and adopt the shape of pixel electrode to limit each channel region with data line layer.Therefore, can under the situation that does not adopt extra diffraction exposure technology, adopt aforesaid three-wheel mask to form tft array.
Below use description to form the technology or the method for the passivation layer of the uppermost surface top that is located at the array that forms on the substrate 100.Figure 11 shows that at the method schematic diagram that on tft array substrate, forms passivation layer according to an execution mode.
Method shown in Figure 11 is used to form the vacuum chamber 200 of passivation layer.Therefore, the substrate 100 such as the present embodiment tft array substrate that at first will be formed with tft array is loaded in the vacuum chamber 200, and wherein this tft array comprises TFT, pixel electrode etc.Then with oxygen (O 2) feeding vacuum chamber 200.Substrate 100 is carried out the oxygen plasma body technology, thereby form passivation layer 125 with predetermined thickness in the surface of substrate 100.In this embodiment, vacuum chamber 200 is that unit carries out processing substrate with a substrate.
Figure 12 shows that at the other method schematic diagram that on tft array substrate, forms passivation layer according to execution mode.Method shown in Figure 12 adopts reacting furnace to form passivation layer.Therefore, the substrate 100 that is formed with the tft array that comprises TFT and pixel electrode etc. at first is installed in a plurality of boxes or other equipment.Then box is loaded in the reacting furnace 300.Supply oxygen in to the situation downhill reaction stove 300 of substrate 100 heating.By 100 heating form passivation layer 125 in the surface of each substrate 100 to substrate.Basically when forming passivation layer 125, carry out heat treatment and annealing in process to improve the quality of passivation layer 125, this passivation layer 125 is oxide layers.In this embodiment, thus the amount of oxygen that can reduce the passivation layer 125 that is used to form on the substrate 100 reduces the gas cost.Also can in general annealing furnace, carry out this method.As mentioned above, plasma causes seldom or can not cause infringement.Also passivation layer 125 can be grown to bigger thickness.
Tft array substrate and manufacture method thereof according to described execution mode can have following effect.The first, with after forming data wire, deposition is used to form the material of pixel electrode on data line layer, and does not insert the passivation layer as interlayer between data line layer and pixel electrode layer in the composition data line layer.When the composition pixel electrode layer when forming pixel electrode, also define the raceway groove of semiconductor layer simultaneously.Therefore, adopt the three-wheel mask just can be completed into tft array substrate.Owing to during forming raceway groove, do not carry out the diffraction exposure technology, therefore can reduce the exposure technology number of times, and simplify the shape of the printing opacity/shading light part of mask.
The second, can also simplify whole manufacturing process by the mask number of times that minimizing is used in the manufacturing process, and therefore improve the productivity ratio that is associated with large-scale production.The 3rd, above-mentioned tft array substrate and manufacture method thereof are applicable to the LCD of arbitrary patterns, for example copline (IPS) pattern, twisted-nematic (TN) pattern and vertical arrangement (VA) pattern.
Obviously those skilled in the art can carry out various improvement and distortion to the present invention without departing from the spirit and scope of the present invention.Therefore, the present invention is intended to cover all and falls into modification and distortion in claims and the equivalent scope thereof.
Here be used to provide overall understanding for the description of execution mode for different execution mode structures.Do not wish that this description is as adopting the structure described here or device and the whole elements of system and the complete description of feature of method.Many other execution modes will be readily apparent to persons skilled in the art when of the present invention browsing.Can adopt and derive other execution modes from the present invention, make without departing from the spirit and scope of the present invention and can substitute and change structure of the present invention and logic.In addition, described accompanying drawing only is representational and is not to describe in proportion.Can amplify some ratio in the accompanying drawing, and dwindle other ratios in the accompanying drawing.Therefore, think that described disclosure and accompanying drawing are only for illustrative rather than restrictive.
Only purpose considers that one or more execution mode in the disclosure is called term " invention " separately and/or generally speaking for convenience, and does not wish the application's scope at will is defined as concrete arbitrarily invention or creates notion.And, although described concrete execution mode here, it should be understood that to be used to realize that the arrangement mode of identical or similar purpose all can substitute described embodiment after any.The disclosure is used to cover arbitrarily or all subsequently the modification and distortion of various execution modes.When reading this specification, the combination of above-mentioned execution mode and other execution modes of not specifically noting here are apparent for a person skilled in the art.
In order to meet 37C.F.R.﹠amp; 1.72 requirement spy (b) provides summary of the present invention, should understand this summary is not scope and the implication that is used to explain or limit claims.In addition, in above-mentioned detailed description, various execution modes can be incorporated into together or are described with independent execution mode for simplifying purpose of the present disclosure.The present invention should be interpreted as reflecting the intention of execution mode requirement required for protection than the more technical characterictic of in each claim, quoting.On the contrary, reflected in following claim that subject matter relates to the feature of all features that are less than any disclosed execution mode.Therefore, following claim is attached in the detail specifications, and each claim itself limits its desired separately theme.
Above-mentioned disclosed theme is thought illustrative rather than restrictive, and appended claims is intended to cover all modifications, improvement and other execution modes that falls in the spirit and scope of the present invention.Therefore, in order to maximize allowed by law scope, determine scope of the present invention by the explanation that allows the most widely of following claim and equivalent thereof, and should not be subjected to the restriction and the qualification of above-mentioned detailed description.Although disclose different execution mode of the present invention, can realize more execution modes within the scope of the invention for those skilled in the art.Therefore, limit the present invention according to appended claims and equivalent thereof.

Claims (37)

1, a kind of thin-film transistor array base-plate comprises:
Intersected with each other to limit the grid line and the data wire of the pixel region on the substrate;
With a plurality of thin-film transistors of the adjacent setting in crosspoint of each grid line and a data wire, source electrode that each thin-film transistor comprises the grid that stretches out from grid line, stretch out from data wire and the drain electrode adjacent with this source electrode;
A plurality of pixel electrodes on described pixel region, described pixel electrode is adjacent with this drain electrode; And
With a plurality of transparent electrode patterns that data wire is adjacent, wherein said source electrode stretches out from this data wire.
2, thin-film transistor array base-plate according to claim 1 is characterized in that, at least one of described a plurality of thin-film transistors also comprises the semiconductor layer that is arranged between this grid and described source electrode and the drain electrode, and described semiconductor layer comprises this grid.
3, thin-film transistor array base-plate according to claim 2 is characterized in that, at least one of described a plurality of thin-film transistors also comprises the gate insulation layer that is arranged between this grid line and this semiconductor layer.
4, thin-film transistor array base-plate according to claim 3 is characterized in that, described semiconductor layer of composition and gate insulation layer make it have essentially identical width.
5, thin-film transistor array base-plate according to claim 1 is characterized in that, also comprises:
Be formed on the passivation layer of the surface of this substrate, this substrate comprises described grid line, data wire, thin-film transistor and pixel electrode layer.
6, thin-film transistor array base-plate according to claim 5 is characterized in that, described passivation layer is an oxide layer, and thickness is about 200 to 500 dusts.
7, thin-film transistor array base-plate according to claim 1 is characterized in that, described pixel electrode and transparent electrode pattern are arranged on same one deck.
8, thin-film transistor array base-plate according to claim 1 is characterized in that, also comprises:
Be arranged essentially parallel to described grid line and be arranged on common wire on the pixel region.
9, thin-film transistor array base-plate according to claim 8 is characterized in that, also comprises:
From a plurality of public electrodes that a common wire bifurcated comes out, at least one of described public electrode has the part that the pixel electrode with pixel electrode layer is arranged alternately.
10, thin-film transistor array base-plate according to claim 9, it is characterized in that, each described pixel electrode has and is provided for the storage electrode overlapping with the drain electrode of a thin-film transistor, and described pixel electrode comes out with bifurcated in the storage electrode of finger shape from pixel region.
11, thin-film transistor array base-plate according to claim 1 is characterized in that, also comprises:
Be arranged on the grid welding disk pattern of an end of a described grid line; And
Be arranged on a grid pad end on the described grid welding disk pattern, described grid pad end and pixel electrode layer are arranged on on one deck.
12, thin-film transistor array base-plate according to claim 1 is characterized in that, also comprises:
Be arranged on the data pads pattern of an end of a described data wire;
Be arranged on a data pads end on the described data pads pattern, described data pads end and pixel electrode layer are arranged on on one deck.
13, a kind of thin-film transistor array base-plate comprises:
Many grid lines;
With many data wires that described many grid lines intersect, described many grid lines wherein one with described many data wires wherein one intersect on substrate, to form pixel region;
Be basically parallel to many common wires that grid line is provided with;
With a plurality of thin-film transistors of the adjacent setting in crosspoint of described grid line and data wire, wherein each thin-film transistor comprise the grid that stretches out from grid line, the source electrode that stretches out from data wire and the drain electrode adjacent with this source electrode;
A plurality of first storage electrodes, at least one of wherein said a plurality of first storage electrodes is arranged at least one of described drain electrode;
In each pixel region, extend a plurality of pixel electrodes that are provided with from described first storage electrode;
With this first storage electrode separately and with the contacted a plurality of transparent electrode patterns of this source electrode; And
The a plurality of public electrodes that in each pixel region and with described pixel electrode, are arranged alternately.
14, thin-film transistor array base-plate according to claim 13 is characterized in that, described grid line and common wire are arranged on same one deck.
15, thin-film transistor array base-plate according to claim 13, it is characterized in that, at least one of described common wire comprises second storage electrode that is arranged in described pixel region, and the width of described second storage electrode is greater than the width of this at least one common wire.
16, thin-film transistor array base-plate according to claim 15 is characterized in that, second storage electrode of a part from this pixel region that is formed on the public electrode in each pixel region extends.
17, thin-film transistor array base-plate according to claim 13 is characterized in that, described first storage electrode, pixel electrode and transparent electrode pattern are positioned at same one deck.
18, a kind of manufacture method of thin-film transistor array base-plate comprises:
On substrate, form grid line and grid;
On the surface of the substrate that comprises described grid line and grid, deposit gate insulation layer, semiconductor cambium layer and data metal layer;
Remove at least a portion data metal layer, semiconductor cambium layer and gate insulation layer, extend thereby make data wire be basically perpendicular to grid line;
At the surface of the substrate that comprises data wire deposit transparent electrode layer; And
Remove at least a portion transparent electrode layer, data metal layer and semiconductor cambium layer to desired depth.
19, method according to claim 18 is characterized in that, carries out described removal at least a portion transparent electrode layer, data metal layer and the semiconductor cambium layer step to desired depth from the channel region that forms the zone corresponding to semiconductor layer.
20, method according to claim 19 is characterized in that, also comprises:
The predetermined portions of composition pixel region forms source electrode and drain electrode to form semiconductor layer on the semiconductor cambium layer on data metal layer, and forms the pixel electrode that is connected with described drain electrode on transparency electrode.
21, method according to claim 18 is characterized in that, after removing at least a portion data metal layer, semiconductor cambium layer and gate insulation layer, semiconductor layer forms the zone to be kept.
22, method according to claim 18 is characterized in that, also comprises:
Surface at the substrate that comprises described pixel electrode forms passivation layer.
23, method according to claim 22 is characterized in that, carries out the step of described formation passivation layer in vacuum chamber, reacting furnace or its combination by at least one oxygen plasma body technology.
24, method according to claim 19 is characterized in that, described semiconductor cambium layer comprises the stepped construction that contains amorphous silicon layer and be arranged on the doped layer of this amorphous silicon layer top.
25, method according to claim 24 is characterized in that, when the semiconductor cambium layer is removed to desired depth, from removing this doped layer corresponding to the zone of raceway groove.
26, method according to claim 18 is characterized in that, also comprises:
When forming grid line, form common wire that is basically parallel to grid line and the public electrode that extends from every common wire.
27, method according to claim 26 is characterized in that, described pixel electrode and described public electrode are arranged alternately.
28, method according to claim 18 is characterized in that, also comprises:
End at every grid line when forming this grid line forms the grid welding disk pattern; And
When forming described pixel electrode, form the grid pad end that is connected with this grid welding disk pattern, make this grid pad end and pixel electrode be positioned at same one deck.
29, method according to claim 18 is characterized in that, also comprises:
End at every data wire when forming this data wire forms the data pads pattern; And
When forming described pixel electrode, on this data pads pattern, form the data pads end, make this data pads end and described pixel electrode be positioned at same one deck.
30, a kind of manufacture method of thin-film transistor array base-plate comprises:
On substrate, form grid line, grid and grid welding disk pattern;
Above the upper surface of this substrate, deposit gate insulation layer, semiconductor cambium layer and data metal layer;
Optionally remove at least a portion data metal layer, semiconductor cambium layer and gate insulation layer and be basically perpendicular to the data wire that described grid line extends with formation, semiconductor cambium layer zone keeps;
Deposit transparent electrode layer above the upper surface of this substrate; And
Remove described transparent electrode layer, data metal layer and semiconductor cambium layer to desired depth, thereby semiconductor layer and source electrode, drain electrode are set in each semiconductor cambium layer zone.
31, method according to claim 30, it is characterized in that the step of removing described transparent electrode layer is used for forming pixel electrode at each pixel region, forming and each grid welding disk pattern contacted grid pad end and formation and the contacted data pads end of each data pads pattern.
32, method according to claim 30 is characterized in that, also comprises:
Surface at this substrate forms passivation layer.
33, method according to claim 32 is characterized in that, carries out the step that forms this passivation layer by at least one oxygen plasma body technology in vacuum chamber, reacting furnace or its combination.
34, a kind of manufacture method of thin-film transistor array base-plate comprises:
Substantially the grid line and the common wire that extend along same direction are set on substrate;
Public electrode, grid and grid welding disk pattern are set on this substrate;
On the surface of the substrate that comprises described grid line, common wire, public electrode, grid and grid welding disk pattern, deposit gate insulation layer, semiconductor cambium layer and data metal layer;
Optionally remove at least a portion data metal layer, semiconductor layer cambium layer and gate insulation layer and be basically perpendicular to the data wire that described grid line extends, wherein form the zone by optionally removing the formation semiconductor layer with formation;
At the surface of the substrate that comprises data wire deposit transparent electrode layer; And
Remove at least a portion transparent electrode layer, data metal layer and semiconductor cambium layer to desired depth, wherein the removal of at least a portion transparent electrode layer makes to form at each semiconductor layer and forms semiconductor layer, source electrode and drain electrode in the zone.
35, method according to claim 34, it is characterized in that, the removal of at least a portion transparent electrode layer forms pixel electrode, forms the grid pad end that is connected with each grid welding disk pattern in each pixel region, and forms the data pads end that is connected with each data pads pattern.
36, method according to claim 34 is characterized in that, also comprises:
Surface at this substrate forms passivation layer.
37, method according to claim 36 is characterized in that, carries out the step that forms described passivation layer by at least one oxygen plasma body technology, vacuum chamber, reacting furnace or its combination.
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