CN106328587A - Array substrate and manufacturing method thereof and liquid crystal display panel - Google Patents
Array substrate and manufacturing method thereof and liquid crystal display panel Download PDFInfo
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- CN106328587A CN106328587A CN201610735560.0A CN201610735560A CN106328587A CN 106328587 A CN106328587 A CN 106328587A CN 201610735560 A CN201610735560 A CN 201610735560A CN 106328587 A CN106328587 A CN 106328587A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 title claims abstract description 34
- 239000004973 liquid crystal related substance Substances 0.000 title abstract description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 108
- 239000002184 metal Substances 0.000 claims abstract description 108
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims description 22
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- 238000001459 lithography Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000002161 passivation Methods 0.000 description 9
- 239000007788 liquid Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides a manufacturing method of an array substrate. The method comprises the following steps of sequentially manufacturing a first metal layer, an insulating layer, an active layer and a second metal layer on the substrate; manufacturing a transparent conductive film on the substrate and covering the second metal layer by the transparent conductive film; coating the transparent conductive film with a third photoresist and covering a third mask on the third photoresist to photoetch a pattern on the third photoresist, wherein the projection of the second metal layer on the third photoresist is included in the pattern; and etching the transparent conductive film to form a transparent electrode layer and covering the second metal layer by the transparent electrode layer. According to the manufacturing method provided by the invention, the manufacturing cost of the array substrate is reduced, the manufacturing procedure of the array substrate is simplified and the production efficiency is improved. The array substrate and a liquid crystal display panel provided by the invention are relatively low in manufacturing cost.
Description
Technical field
The present invention relates to a kind of technical field of liquid crystal display, especially relate to structure and the making side thereof of a kind of array base palte
Method, display panels.
Background technology
Manufacture field at TFT-LCD, by reducing Mask number and photoetching process number of times, with reduce manufacturing cost and
The purpose of the raising equipment productivity, is a kind of trend all the time.TFT-LCD manufacturing process, from initial 7-Mask Making programme, is sent out
Open up 5-Mask and the 4-Mask production technology that the most each LCD manufacturer volume production uses, and have been developed over 3-Mask at present
Technology.
Existing 3-Mask technology, utilizes the photoresist lift off in semiconductor integrated circuit (Lift-off) technique to complete
The definition of bright pixel electrode pattern.Refer to Fig. 1 a, first pass through the first mask plate (Mask) and make gate line layer 11 (M1) by lithography,
Insulating barrier (scheming unnumbered) and data line layer 14 (M2) is made by lithography by the second mask plate；Passivation is formed again in data line layer 14
Layer 15；Then the 3rd mask plate etching photoresist layer 16 on passivation layer 15 is used；Through photoresist via on passivation layer 15
Form via 17；Then on photoresist layer 16 and other regions, form layer of transparent conductive layer 18；Refer to Fig. 1 b, finally shell
From the transparency conducting layer 18 of photoresist layer 16 and upper deposition thereof, form specific TFT structure.
Although above-mentioned 3 mask plates complete the battle array that the making of array base palte completes relative to 4 mask plates and 5 mask plates
Row substrate manufacture technique is simple, but its processing technology and final structure are the most more complicated.Therefore, improvement array base palte is needed badly
Structure and manufacture method to improve production efficiency.
Summary of the invention
It is an object of the invention to provide the making side of a kind of array base palte simplifying production process, raising production efficiency
Method, and the array structure produced by the method is simple.
Another object of the present invention is to the array base palte providing a kind of aforementioned production method to produce.
Another object of the present invention is to provide the display panels of a kind of above-mentioned array base palte.
To achieve these goals, the following technical scheme of embodiment of the present invention offer:
The present invention provides the manufacture method of a kind of array base palte, comprises the steps:
Substrate makes the first metal layer, insulating barrier, active layer and the second metal level successively；
Making transparent conductive film on the substrate, described transparent conductive film covers described second metal level；
Described transparent conductive film coats the 3rd photoresist, described 3rd photoresist hides the 3rd mask plate,
To make pattern by lithography on described 3rd photoresist, wherein, described second metal level projection bag on described 3rd photoresist
It is contained in described pattern；
Performing etching described transparent conductive film, to form transparent electrode layer, wherein, described transparent electrode layer covers institute
State the second metal level.
Wherein, described transparent electrode layer is completely covered described second metal level.
Wherein, described making successively on substrate in the first metal layer, insulating barrier, active layer and the second metal level step is wrapped
Include: sputter the first metal film layer on the substrate；Described first metal film layer coats the first photoresist；Described
The first mask plate is hidden, to make pattern by lithography on described first photoresist on first photoresist；To described first metallic film
Layer performs etching, to form described the first metal layer.
Wherein, described making successively on substrate in the first metal layer, insulating barrier, active layer and the second metal level step is wrapped
Include: on described active layer, sputter the second metal film layer；Described second metal film layer coats the second photoresist；Institute
State and on the second photoresist, hide the second mask plate, to make pattern by lithography on described second photoresist；To described second metal foil
Film layer performs etching, to form described second metal level.
Wherein, the described transparent electrode layer that makes on the substrate, described transparent electrode layer covers described second metal level
In step, form described transparent conductive film on the substrate including using physical vaporous deposition.
Wherein, described active layer includes be cascading amorphous silicon layer and doped layer；Described make successively on substrate
The first metal layer, insulating barrier, active layer and the second metal level step include: deposited by chemical gaseous phase on described insulating barrier
Method sequentially forms amorphous silicon layer and doped layer.
The present invention provides a kind of array base palte, including the first metal layer being cascadingly set on substrate, insulating barrier, has
Active layer, the second metal level and transparent electrode layer, described transparent electrode layer directly overlays on described second metal level.
Wherein, described transparent electrode layer is completely covered described second metal level.
Wherein, described active layer includes be cascading amorphous silicon layer and doped layer, and described doped layer is between described non-
Between crystal silicon layer and described second metal level.
The present invention provides a kind of display panels, uses the array base palte described in above-mentioned any one.
The embodiment of the present invention has the advantage that or beneficial effect:
In the manufacture method of the array base palte of the present invention, when making transparent electrode layer so that transparent electrode layer is with described
Second metal level directly contacts, and eliminates the manufacturing process of passivation layer.Transparent electrode layer is coated with described second metal completely simultaneously
It is oxidized that layer is prevented from described second metal level, serves the protective effect of passivation layer.The manufacture method of the present invention reduces
The cost of manufacture of array base palte, simplifies the manufacturing process of array base palte, improves production efficiency.The array base palte of the present invention and
Display panels manufacturing cost is relatively low.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to
Other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 a-Fig. 1 b is prior art array substrate manufacturing method schematic diagram.
Fig. 2-Fig. 3 is array substrate manufacturing method schematic diagram of the present invention.
Fig. 4 is the array base-plate structure schematic diagram that the manufacture method shown in Fig. 2-Fig. 3 is made.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Base
Embodiment in the present invention, it is all that those of ordinary skill in the art are obtained on the premise of not making creative work
Other embodiments, broadly falls into the scope of protection of the invention.
Additionally, the explanation of following embodiment is with reference to additional diagram, the spy implemented in order to illustrate the present invention may be used to
Determine embodiment.The direction term being previously mentioned in the present invention, such as, " on ", D score, "front", "rear", "left", "right", " interior ",
" outward ", " side " etc., be only the direction with reference to annexed drawings, and therefore, the direction term of use is in order to more preferably, more clearly say
Bright and understand the present invention rather than instruction or infer the device of indication or element must have specific orientation, with specific side
Position structure and operation, be therefore not considered as limiting the invention.
In describing the invention, it should be noted that unless otherwise clearly defined and limited, term " is installed ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be fixing connection, it is also possible to be detachably connected, or connect integratedly
Connect；Can be to be mechanically connected；Can be to be joined directly together, it is also possible to be indirectly connected to by intermediary, in can being two elements
The connection in portion.For the ordinary skill in the art, above-mentioned term tool in the present invention can be understood with concrete condition
Body implication.
Additionally, in describing the invention, except as otherwise noted, " multiple " are meant that two or more.If this
Occurring the term of " operation " in description, it refers not only to independent operation, when cannot clearly distinguish with other operation, as long as
The effect desired by this operation that can realize then is also included within this term.It addition, in this specification with "～" the numerical value model that represents
Enclose refer to using "～" before and after the scope that is included as minima and maximum of numerical value recorded.In the accompanying drawings, structure
Similar or identical is indicated by the same numeral.
The manufacture method of the array base palte that the present invention provides mainly comprises the steps:
S301: make the first metal layer, insulating barrier, active layer and the second metal level on substrate successively.
Referring to Fig. 2, concrete, described substrate 20 can be transparent glass substrate.First sputter on described substrate 20
First metal film layer；Preferably, described first metal film layer is the monofilm of Cr, W, Ti, Ta, Mo, Al or Cu, or Cr,
The composite membrane that W, Ti, Ta, Mo, Al and Cu combination in any is constituted.Then, described first metal film layer coats the first light
Photoresist also hides the first mask plate, and to make pattern on described first photoresist by lithography, described first metal film layer is exposed to
Gap between pattern, and etch the first metal film layer by etching liquid and etch described the first metal layer 21.
It is understood that described first photoresist needs to remove after forming described the first metal layer 21.Photoresist
Minimizing technology is prior art, and here is omitted.
It is understood that gate line and gate electrode are formed by described the first metal layer 21.
Then on described the first metal layer 21, form insulating barrier 22.Preferably, described insulating barrier 22 can use and generally make
With materials such as silicon oxide, silicon nitride, silicon oxynitrides.Described insulating barrier 22 is formed with active layer 23.Concrete, it is formed with active layer
The process of 23 specifically includes: sequentially form amorphous silicon layer 231 and doping on described insulating barrier 22 by chemical vapour deposition technique
Layer 232.Described doped layer 222 can include indium gallium zinc oxide (English: indiumgalliumzincoxide, be called for short:
IGZO) material.It is to say, described active layer 23 includes amorphous silicon layer 231 and the doped layer 232 being cascading, described
Amorphous silicon layer 231 is between described insulating barrier 22 and described doped layer 232.
Described active layer 23 sputters the second metal film layer, described second metal film layer coats the second photoetching
Glue, hides the second mask plate on described second photoresist, forms pattern, described second metal on described second photoresist
Thin layer exposes and the gap of described pattern, is performed etching described second metal film layer by etching liquid, etches described
Second metal level 24 (including source electrode line (not shown), source electrode 241 and drain electrode 242).It is understood that described second
Metal film layer is the monofilm of Cr, W, Ti, Ta, Mo, Al or Cu, or Cr, W, Ti, Ta, Mo, Al and Cu combination in any is constituted
Composite membrane.
It is understood that described second photoresist needs to remove after forming described second metal level 24.Photoresist
Minimizing technology is prior art, and here is omitted.
It is understood that source electrode line, source electrode 241 and drain electrode 242 are formed by described second metal level 24.
It is understood that during described second metal film layer is performed etching by etching liquid, also can have described
Active layer 23 performs etching so that form the pattern similar to described second metal level 24 on described active layer 23.
S302: make transparent conductive film on the substrate, described transparent conductive film covers described second metal level.
Referring to Fig. 3, concrete, described transparent conductive film 251 can be by tin indium oxide (ITO), stannum oxide (TO), oxygen
Change indium stannum zinc (ITZO) or indium zinc oxide (IZO) is formed.Preferably, physical vaporous deposition is used to be formed on the substrate
Described transparent conductive film 251.Described transparent conductive film 251 covers described second metal level 24.It is to say, it is described transparent
Conductive film 251 directly contacts with described second metal level 24.
S303: coat the 3rd photoresist on described transparent conductive film 251, hides the 3rd on described 3rd photoresist
Mask plate, to make pattern by lithography on described 3rd photoresist, wherein, described second metal level is on described 3rd photoresist
Projection is contained in described pattern.
After forming pattern on described 3rd photoresist, described transparent conductive film 251 has part can be exposed to the described 3rd
Gap on photoetching agent pattern, in order in following step, described transparent conductive film 251 is performed etching.Arrange described
The projection on described 3rd photoresist of two metal levels 24 is contained in described pattern, is to ensure that below the 3rd photoetching agent pattern
Transparent conductive film 251 etching after formed transparent electrode layer 25 can by second metal level cover.
Preferably, described first mask plate, described second mask plate and described 3rd mask plate can be intermediate tone mask
Version or gray tone mask plate.
S304: described transparent conductive film 251 is performed etching, to form transparent electrode layer, wherein, described transparency electrode
Layer covers described second metal level.
Incorporated by reference to refering to Fig. 4, concrete, the gap of etching liquid pattern on photoresist enters transparent conductive film 251, right
Described transparent conductive film 251 performs etching, and etches described transparent electrode layer 25.Transparent due to above the second metal level 24
Conductive film 251 is covered by the pattern on the 3rd photoresist, described transparent electrode layer 25 energy that the most etched liquid etches
Enough coverings are on described second metal level 24.
It is understood that described 3rd mask plate upper part pattern is similar to the pattern on described second mask plate.Change
For it, just light tight to region with described second metal level on described 3rd mask plate.
It is understood that after forming described transparent electrode layer 25, after needing to remove described 3rd photoresist, just can enter
Row subsequent handling, because it is unrelated with inventive point, here is omitted.
In the manufacture method of the array base palte of the present invention, when making transparent electrode layer so that transparent electrode layer is with described
Second metal level directly contacts, and eliminates the manufacturing process of passivation layer, and the manufacture method of the present invention reduces the system of array base palte
Make cost, simplify the manufacturing process of array base palte, improve production efficiency.
Preferably, described transparent electrode layer 25 can be completely covered described second metal level 24.Transparent electrode layer 25 is complete
Being coated with described second metal level 24, to be prevented from described second metal level 24 oxidized, serves the protective effect of passivation layer.
Please continue to refer to Fig. 4, the present invention also provides for a kind of array base palte 200, mainly includes substrate 20, the first metal layer
21, insulating barrier 22, active layer the 23, second metal level 24 and transparent electrode layer 25.Described the first metal layer 21 is arranged at described base
On plate 20；Described insulating barrier 21 covers on described the first metal layer 21.Described active layer 23 is located on described insulating barrier 22.
Described second metal level 24 is formed on described active layer 23.Described transparent electrode layer 25 covers described second metal level 24.
In the array base palte of the present invention, transparent electrode layer directly contacts with described second metal level, eliminates passivation layer
Manufacturing process, saves manufacturing cost.
Preferably, described transparent electrode layer 25 is completely covered described second metal level 24.Transparent electrode layer is coated with institute completely
Stating the second metal level 24, to be prevented from described second metal level 24 oxidized, serves the protective effect of passivation layer, it is to avoid described
Second metal level 24 is oxidized.
Preferably, described active layer 23 includes amorphous silicon layer 231 and the doped layer 232 being cascading, described doping
Layer 232 is between described amorphous silicon layer 231 and described second metal level 24.
It is understood that source electrode line, source electrode 241 and drain electrode 242 are formed by described second metal level 24.Gate line
Formed by described the first metal layer 21 with gate electrode.
The present invention also provides for a kind of display panels, including above-mentioned array base palte 200.This display panels is permissible
Be applied to include but not limited to for: Electronic Paper, LCD TV, mobile phone, DPF, panel computer etc. are any has display
The product of function or parts.
In the description of this specification, reference term " embodiment ", " some embodiments ", " example ", " specifically show
Example " or the description of " some examples " etc. means to combine this embodiment or example describes specific features, structure, material or feature
It is contained at least one embodiment or the example of the present invention.In this manual, the schematic representation of above-mentioned term is differed
Surely identical embodiment or example are referred to.And, the specific features of description, structure, material or feature can be any one
Individual or multiple embodiment or example combine in an appropriate manner.
Embodiments described above, is not intended that the restriction to this technical scheme protection domain.Any in above-mentioned enforcement
Amendment, equivalent and the improvement etc. made within the spirit of mode and principle, should be included in the protection model of this technical scheme
Within enclosing.
Claims (10)
1. the manufacture method of an array base palte, it is characterised in that comprise the steps:
Substrate makes the first metal layer, insulating barrier, active layer and the second metal level successively；
Making transparent conductive film on the substrate, described transparent conductive film covers described second metal level；
On described transparent conductive film coat the 3rd photoresist, on described 3rd photoresist hide the 3rd mask plate, with
Making pattern by lithography on described 3rd photoresist, wherein, the projection on described 3rd photoresist of described second metal level is contained in
Described pattern；
Performing etching described transparent conductive film, to form transparent electrode layer, wherein, described transparent electrode layer covers described the
Two metal levels.
2. the manufacture method of array base palte as claimed in claim 1, it is characterised in that described transparent electrode layer is completely covered institute
State the second metal level.
3. the manufacture method of array base palte as claimed in claim 1, it is characterised in that described make first on substrate successively
Metal level, insulating barrier, active layer and the second metal level step include: sputter the first metal film layer on the substrate；?
The first photoresist is coated on described first metal film layer；Described first photoresist hides the first mask plate, with described
Pattern is made by lithography on first photoresist；Described first metal film layer is performed etching, to form described the first metal layer.
4. the manufacture method of array base palte as claimed in claim 1, it is characterised in that described make first on substrate successively
Metal level, insulating barrier, active layer and the second metal level step include: sputter the second metal film layer on described active layer；
Described second metal film layer coats the second photoresist；Described second photoresist hides the second mask plate, with in institute
State and make pattern by lithography on the second photoresist；Described second metal film layer is performed etching, to form described second metal level.
5. the manufacture method of array base palte as claimed in claim 1, it is characterised in that described make on the substrate transparent
Electrode layer, described transparent electrode layer covers in described second metal level step, including using physical vaporous deposition at described base
Described transparent conductive film is formed on plate.
6. the manufacture method of array base palte as claimed in claim 1, it is characterised in that described active layer includes stacking gradually and sets
Put amorphous silicon layer and doped layer；Described the first metal layer, insulating barrier, active layer and the second metal level of making successively on substrate walks
Suddenly include: on described insulating barrier, sequentially form amorphous silicon layer and doped layer by chemical vapour deposition technique.
7. an array base palte, it is characterised in that include the first metal layer being cascadingly set on substrate, insulating barrier, have
Active layer, the second metal level and transparent electrode layer, described transparent electrode layer directly overlays on described second metal level.
8. as claimed in claim 7 array base palte, it is characterised in that described active layer include being cascading amorphous silicon layer and
Doped layer, described doped layer is between described amorphous silicon layer and described second metal level.
9. array base palte as claimed in claim 7, it is characterised in that described transparent electrode layer is completely covered described second metal
Layer.
10. a display panels, it is characterised in that include the array base palte described in claim 7-9 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610735560.0A CN106328587A (en) | 2016-08-26 | 2016-08-26 | Array substrate and manufacturing method thereof and liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610735560.0A CN106328587A (en) | 2016-08-26 | 2016-08-26 | Array substrate and manufacturing method thereof and liquid crystal display panel |
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|---|---|
| CN106328587A true CN106328587A (en) | 2017-01-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610735560.0A Pending CN106328587A (en) | 2016-08-26 | 2016-08-26 | Array substrate and manufacturing method thereof and liquid crystal display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971976A (en) * | 2017-05-15 | 2017-07-21 | 深圳市华星光电技术有限公司 | Array base palte and preparation method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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