TWI437942B - Circuit board and manufacturing method thereof - Google Patents

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board having a buried circuit layer and a surface circuit layer, and a method of fabricating the same.

In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and better-functioning electronic products constantly innovating and designing towards light, thin, short and small trends. A circuit board having conductive lines is usually disposed in these electronic products.

Generally, in the production of a circuit board, a substrative process can be utilized to fabricate a circuit layer in a circuit board. However, in the process of the reduction process, if the thickness of the conductive layer forming the wiring layer is too thick, the etching time is too long, so that the etching liquid may stagnate into a pool shape between the line patterns to affect the etching ability. In addition, in the etching process, if the thickness of the conductive layer is too thick, a long etching time is often required, so that the etching liquid will have a serious side etching effect on the sidewall of the wiring pattern, thereby affecting the quality and reliability of the circuit, and is disadvantageous. In the production of fine lines. On the other hand, if the thickness of the conductive layer is reduced in order to avoid the above problem, the heat capacity of the formed structure is insufficient, and thus it is impossible to provide a good heat dissipation capability.

In addition, in the current manufacturing process of the buried circuit, after forming a conductive layer on the dielectric layer and the trench in the dielectric layer by electroplating, etching is performed to remove unnecessary conductive Layer formation Buried line. However, after etching, it is often easy to expose the surface of the dielectric layer in the trench, thus affecting subsequent processes.

In addition, when a thin line is formed by a semi-additive process (SAP), the contact area between the line and the dielectric layer is often too small, and the peeling strength of the thin line is insufficient, and the self-dielectric layer is easily peeled off. This reduces the reliability of the board.

Moreover, when a via hole for connecting two circuit layers is generally formed, an opening is usually formed in the dielectric layer, and then a conductive material layer is filled in the opening. However, in the process of filling the conductive material layer into the opening, the conductive layer material is often not easily filled because the aspect ratio of the opening is too large.

The invention provides a method for fabricating a circuit board for fabricating a circuit board having both a buried circuit layer and a surface circuit layer.

The present invention further provides a wiring board having both a buried wiring layer and a surface wiring layer.

The invention provides a method for manufacturing a circuit board, and the manufacturing method comprises the following steps. First, a dielectric layer is formed on the substrate, wherein an internal wiring layer has been formed on the substrate, and the dielectric layer covers the internal wiring layer. Then, a first trench, a second trench, and an opening are formed in the dielectric layer, wherein the opening is located below the first trench and communicates with the first trench, and the opening exposes a portion of the internal wiring layer. Subsequently, a patterned conductive layer is formed on the dielectric layer. The patterned conductive layer covers a portion of the dielectric layer and fills the first trench, the second trench, and the opening to form a first wiring layer, a second wiring layer, and a via hole, respectively. The middle via is electrically connected to the first circuit layer and the inner circuit layer.

A method of fabricating a circuit board according to an embodiment of the invention, wherein the first circuit layer comprises a first buried circuit layer and a first surface circuit layer. The first buried wiring layer is located in the first trench, and the first surface wiring layer is located on the dielectric layer and the first buried wiring layer. The boundary of the first buried wiring layer is located within the boundary of the first surface wiring layer. The second circuit layer includes a second buried wiring layer and a second surface wiring layer. The second buried wiring layer is located in the second trench, and the second surface wiring layer is located on the dielectric layer and the second buried wiring layer. The boundary of the second buried wiring layer is located within the boundary of the second surface wiring layer.

A method of fabricating a circuit board according to an embodiment of the present invention, wherein after forming the first trench, the second trench, and the opening, and before forming the patterned conductive layer, further comprising the dielectric layer and the opening exposed An active layer is formed on a portion of the inner wiring layer.

A method of fabricating a wiring board according to an embodiment of the invention, wherein the method of forming a patterned conductive layer comprises the following steps. First, a bottom conductive layer is formed on the active layer. Then, a conductive material layer is formed on the bottom conductive layer, wherein the conductive material layer fills the first trench, the second trench, and the opening. Next, a patterned photoresist layer is formed, and the patterned photoresist layer covers the conductive material layer located above the first trench and the second trench and around the first trench and around the second trench. Then, the patterned photoresist layer is used as a mask to remove a portion of the conductive material layer and a portion of the bottom conductive layer. Thereafter, the patterned photoresist layer is removed.

A method of fabricating a wiring board according to an embodiment of the invention, wherein the method of forming a patterned conductive layer comprises the following steps. First, a bottom conductive layer is formed on the active layer. Then, a patterned photoresist layer is formed on the bottom conductive layer. The patterned photoresist layer exposes the first trench, the second trench, and a bottom conductive layer around the first trench and around the second trench. Next, a conductive material layer is formed on the bottom conductive layer exposed by the patterned photoresist layer, wherein the conductive material layer fills the first trench, the second trench, and the opening. Next, the patterned photoresist layer and the bottom conductive layer underlying the patterned photoresist layer are removed.

According to the method of fabricating a circuit board according to an embodiment of the invention, the dielectric layer contains a plurality of activated particles, and a part of the activated particles are exposed when the first trench, the second trench, and the opening are formed.

A method of fabricating a wiring board according to an embodiment of the invention, wherein the method of forming a patterned conductive layer comprises the following steps. First, a bottom conductive layer is formed on the dielectric layer. Then, a conductive material layer is formed on a portion of the inner wiring layer exposed on the bottom conductive layer and the opening, wherein the conductive material layer fills the first trench, the second trench, and the opening. Next, a patterned photoresist layer is formed, and the patterned photoresist layer covers the conductive material layer located above the first trench and the second trench and around the first trench and around the second trench. Then, the patterned photoresist layer is used as a mask to remove a portion of the conductive material layer and a portion of the bottom conductive layer. Thereafter, the patterned photoresist layer is removed.

A method of fabricating a wiring board according to an embodiment of the invention, wherein the method of forming a patterned conductive layer comprises the following steps. First, a bottom conductive layer is formed on the dielectric layer. Then, a patterned photoresist layer is formed on the bottom conductive layer, and the patterned photoresist layer exposes the first trench, the second trench, and the bottom conductive layer around the first trench and around the second trench. Then, a conductive material layer is formed on the bottom conductive layer exposed on the patterned photoresist layer and a portion of the inner wiring layer, wherein the conductive material layer fills the first trench, the second trench, and the opening. Next, the patterned photoresist layer and the bottom conductive layer underlying the patterned photoresist layer are removed.

The invention further provides a circuit board comprising a substrate, an inner circuit layer, a dielectric layer, a first circuit layer, a second circuit layer and a via. The inner wiring layer is disposed on the substrate. The dielectric layer is disposed on the substrate and covers the internal wiring layer. The first circuit layer includes a first buried wiring layer and a first surface wiring layer. The first buried wiring layer is buried in the dielectric layer. The first surface wiring layer is disposed on the dielectric layer and the first buried wiring layer. The second circuit layer includes a second buried wiring layer and a second surface wiring layer. The second buried wiring layer is buried in the dielectric layer. The second surface wiring layer is disposed on the dielectric layer and the second buried wiring layer. The via hole is disposed in the dielectric layer and electrically connected to the first buried circuit layer and the internal circuit layer.

A circuit board according to an embodiment of the invention, wherein a boundary of the first buried wiring layer is located within a boundary of the first surface wiring layer, and a boundary of the second buried wiring layer is located within a boundary of the second surface wiring layer.

The circuit board according to the embodiment of the invention further includes an active layer. The active layer is disposed between the dielectric layer and the first wiring layer, between the dielectric layer and the second wiring layer, between the dielectric layer and the via, and between the internal wiring layer and the via.

The circuit board according to the embodiment of the invention further includes a bottom conductive layer. The bottom conductive layer is disposed on the active layer.

A circuit board according to an embodiment of the invention, wherein the dielectric layer contains a plurality of activated particles.

The circuit board according to the embodiment of the invention further includes a bottom conductive layer, The bottom conductive layer is disposed between the dielectric layer and the first wiring layer, between the dielectric layer and the second wiring layer, and between the dielectric layer and the via hole.

Based on the above, in the present invention, the patterned conductive layer covers part of the dielectric layer and fills the first trench and the second trench, so that the overall thickness of the first circuit layer and the second circuit layer can be increased, thereby improving the circuit layers. Heat capacity to provide good heat dissipation. In addition, since the contact area between the first circuit layer and the second circuit layer and the dielectric layer is increased, the adhesion of the circuit layer to the dielectric layer can be increased to prevent the circuit layer from being peeled off from the dielectric layer and causing the circuit board. The problem of reduced reliability. Moreover, since the first trench communicates with the opening for forming the via hole, the aspect ratio of the opening is reduced, and thus the conductive material layer can easily fill the opening in a subsequent process to form a good quality. Via hole.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to FIG. 1E are schematic cross-sectional views showing a method of fabricating a circuit board according to a first embodiment of the present invention. First, referring to FIG. 1A, a dielectric layer 106 is formed on the substrate 102. The substrate 102 is, for example, a dielectric substrate. Further, an internal wiring layer 104 has been formed on the substrate 102. Dielectric layer 106 covers substrate 102 and internal wiring layer 104. The material of the dielectric layer 106 is, for example, polypropylene (PP), polyimide (PI), ABF film (Ajinomoto build-up film) or liquid crystal polymer (LCP).

Then, referring to FIG. 1B, a first trench 108a, a second trench 108b, and an opening 110 are formed in the dielectric layer 106. The opening 110 is located below the first trench 108a and communicates with the first trench 108a. Additionally, the opening 110 exposes a portion of the inner wiring layer 104. The first trench 108a, the second trench 108b, and the opening 110 are formed by, for example, laser drilling or mechanical drilling. In addition, the first trench 108a, the second trench 108b, and the opening 110 are formed by, for example, forming a first trench 108a and a second trench 108b in the dielectric layer 106, and then forming a dielectric layer under the first trench 108a. An opening 110 is formed in 106. However, the invention is not limited thereto. In other embodiments, the opening 110 may be formed in the dielectric layer 106 to form the first trench 108a and the second trench 108b.

In the present embodiment, since the opening 110 is located below the first trench 108a and communicates with the first trench 108a, the aspect ratio of the opening 110 can be reduced, and thus the conductive material can be easily replaced in a subsequent process. The opening 110 is filled to form a good quality conductive structure.

Next, referring to FIG. 1C, an active layer 112 is formed on the portion of the internal wiring layer 104 exposed on the dielectric layer 106 and the opening 110. In the present embodiment, the formation method of the active layer 112 is formed, for example, by chemical deposition. The material of the active layer 112 is, for example, a transition metal complex. Subsequently, a bottom conductive layer 114 is formed on the active layer 112 through the active layer 112. The bottom conductive layer 114 can serve as a seed layer for subsequent electroplating processes.

Referring to FIG. 1D, a conductive material layer 116 is formed on the bottom conductive layer 114. The conductive material layer 116 fills the first trench 108a, the second trench 108b, and the opening 110. The conductive material layer 116 is, for example, a copper layer. Conductive material The formation of the material layer 116 is performed, for example, by using the bottom conductive layer 114 as a seed layer. Next, a patterned photoresist layer 118 is formed on the conductive material layer 116. In the present embodiment, the patterned photoresist layer 118 includes a first portion 118a and a second portion 118b, wherein the first portion 118a covers the conductive material layer 116 above and around the first trench 108a, and the second portion 118b covers the second trench. A layer of conductive material 116 over and around 108b. Further, the boundary of the first trench 108a is located within the boundary of the first portion 118a, so that the first trench 108a may be prevented from being excessively removed during the process of removing the conductive material layer 116 by patterning the photoresist layer 118 as a mask. The conductive material layer 116 is removed and exposed. Similarly, the boundary of the second trench 108b is located within the boundary of the second portion 118b, so that the second trench 108b may be prevented from being excessively removed during the process of removing the conductive material layer 116 by patterning the photoresist layer 118 as a mask. The conductive material layer 116 is removed and exposed.

Then, referring to FIG. 1E , the patterned photoresist layer 118 is used as a mask to remove a portion of the conductive material layer 116 and a portion of the bottom conductive layer 114 to form a first wiring layer 122 , a second wiring layer 124 , and via holes 126 . The via hole 126 is connected to the first circuit layer 122 and the bottom conductive layer 114. Thereafter, the patterned photoresist layer 118 is removed to complete the fabrication of the circuit board 100.

Further, the first wiring layer 122 includes a first buried wiring layer 122a and a first surface wiring layer 122b. The first buried wiring layer 122a is buried in the dielectric layer 106. In addition, the first surface wiring layer 122b is disposed on the dielectric layer 106 and the first buried wiring layer 122a, and the boundary of the first buried wiring layer 122a is located within the boundary of the first surface wiring layer 122b. Second line The circuit layer 124 includes a second buried wiring layer 124a and a second surface wiring layer 124b. The second buried wiring layer 124a is buried in the dielectric layer 106. In addition, the second surface wiring layer 124b is disposed on the dielectric layer 106 and the second buried wiring layer 124a, and the boundary of the second buried wiring layer 124a is located within the boundary of the second surface wiring layer 124b.

In this embodiment, since the first circuit layer 122 is composed of the first surface wiring layer 122b and the first buried wiring layer 122a, it can have a large thickness, and thus has a high heat capacity to provide good heat dissipation. ability. Similarly, since the second wiring layer 124 is composed of the second surface wiring layer 124b and the second buried wiring layer 124a, it can have a large thickness, and thus has a high heat capacity to provide good heat dissipation capability.

In addition, since the bottom conductive layer 114 is formed on the top surface of the dielectric layer 106 and the surface of the trench (the first trench 108a and the second trench 108b), the wiring layer is improved (the first wiring layer 122 and the second wiring layer 124). The area of overlap with the dielectric layer 106 is such that the wiring layer is not easily peeled off from the dielectric layer 106. In this way, the reliability of the circuit board 100 can be effectively improved.

2A-2D are schematic cross-sectional views showing a method of fabricating a circuit board according to a second embodiment of the present invention. The manufacturing method of the second embodiment is similar to that of the first embodiment, and therefore the same members are given the same reference numerals.

First, referring to FIG. 2A, a dielectric layer 206 is formed on the substrate 102, wherein the internal wiring layer 104 has been formed on the substrate 102. In the present embodiment, the dielectric layer 206 contains a plurality of activating particles 212, wherein the activating particles 212 are, for example, uniformly dispersed in the dielectric layer 206. The material of the activated particles 212 is, for example, a transition metal complex.

Next, referring to FIG. 2B, a first trench 108a, a second trench 108b, and an opening 110 are formed in the dielectric layer 206. In the present embodiment, during the formation of the first trench 108a, the second trench 108b, and the opening 110, the activated particles 212 in the dielectric layer 206 are simultaneously exposed.

Next, referring to FIG. 2C, a bottom conductive layer 214 is formed on the dielectric layer 206 through the activated particles 212. The bottom conductive layer 214 can serve as a seed layer for the subsequent electroplating process. In the present embodiment, since the inner wiring layer 104 does not have the activated particles 212, the bottom conductive layer 214 is formed only on the surface of the dielectric layer 206 and is not formed on the inner wiring layer 104.

Next, a fabrication flow as shown in FIGS. 1D and 1E is performed to form the wiring board 200 as shown in FIG. 2D.

3A-3B are schematic cross-sectional views showing a method of fabricating a circuit board according to a third embodiment of the present invention. The manufacturing method of the third embodiment is similar to that of the first embodiment, and therefore the same members are given the same reference numerals.

First, the production flow as shown in FIGS. 1A to 1C is performed. Next, referring to FIG. 3A, a patterned photoresist layer 318 is formed on the bottom conductive layer 114, wherein the patterned photoresist layer 318 exposes the first trench 108a, the second trench 108b, and the first trench 108a and the second trench The bottom conductive layer 114 around 108b, that is, the area where the circuit layer is to be formed later.

Next, a conductive material layer 316 is formed on the bottom conductive layer 114 exposed by the patterned photoresist layer 318, wherein the conductive material layer 316 fills the first trench 308a, the second trench 308b, and the opening 310, and the conductive material layer 316 is covered. A bottom conductive layer 114 is disposed around the first trench 308a and around the second trench 308b.

Next, referring to FIG. 3B, the patterned photoresist layer 318 and the bottom conductive layer 114 under the patterned photoresist layer 318 are removed to form the patterned conductive layer 120, and the fabrication of the wiring board 300 is completed.

4A-4B are schematic cross-sectional views showing a method of fabricating a circuit board according to a fourth embodiment of the present invention. The manufacturing method of the fourth embodiment is similar to that of the second embodiment, and therefore the same members are given the same reference numerals.

First, the production flow as shown in FIGS. 2A to 2C is performed. Next, referring to FIG. 4A, a patterned photoresist layer 318 is formed on the bottom conductive layer 214, wherein the patterned photoresist layer 318 exposes the first trench 108a, the second trench 108b, and the first trench 108a and the second trench The bottom conductive layer 214 around 108b, that is, the area where the circuit layer is to be formed later.

Next, a conductive material layer 416 is formed on the bottom conductive layer 214 exposed on the patterned photoresist layer 318 and a portion of the inner wiring layer 104. The conductive material layer 416 fills the first trench 108a, the second trench 108b, and the opening 110. And the conductive material layer 316 covers the bottom conductive layer 114 around the first trench 308a and around the second trench 308b.

Next, referring to FIG. 4B, the patterned photoresist layer 318 and the bottom conductive layer 214 under the patterned photoresist layer 318 are removed to form the patterned conductive layer 220, and the fabrication of the wiring board 400 is completed.

In summary, the wiring layer of the present invention is composed of an buried wiring layer located in the dielectric layer and a surface wiring layer on the surface of the dielectric layer, and thus can have a large thickness to increase heat capacity, thereby providing good Cooling capacity.

Further, in the present invention, due to the overlap between the wiring layer and the dielectric layer The area is increased, so that the problem that the circuit layer is degraded from the dielectric layer and the reliability of the circuit board is lowered can be avoided.

Furthermore, since the trench for forming the buried wiring layer communicates with the opening for forming the via hole, the aspect ratio of the opening is reduced, and thus the conductive material layer can be easily filled in a subsequent process. Holes to form good quality vias.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400‧‧‧ circuit boards

102‧‧‧Substrate

104‧‧‧Internal circuit layer

106, 206‧‧‧ dielectric layer

108a‧‧‧First ditches

108b‧‧‧Second ditches

110‧‧‧Opening

112‧‧‧Active layer

212‧‧‧Activated Particles

114, 214‧‧‧ bottom conductive layer

116, 216, 316, 416‧‧‧ conductive material layer

118, 318‧‧‧ patterned photoresist layer

120, 220‧‧‧ patterned conductive layer

122‧‧‧First circuit layer

122a‧‧‧First buried circuit layer

122b‧‧‧First surface circuit layer

124‧‧‧Second circuit layer

124a‧‧‧Second buried circuit layer

124b‧‧‧Second surface circuit layer

126‧‧‧through holes

1A to FIG. 1E are schematic cross-sectional views showing a method of fabricating a circuit board according to a first embodiment of the present invention.

2A-2D are schematic cross-sectional views showing a method of fabricating a circuit board according to a second embodiment of the present invention.

3A-3B are schematic cross-sectional views showing a method of fabricating a circuit board according to a third embodiment of the present invention.

4A-4B are schematic cross-sectional views showing a method of fabricating a circuit board according to a fourth embodiment of the present invention.

100‧‧‧ circuit board

102‧‧‧Substrate

104‧‧‧Internal circuit layer

106‧‧‧Dielectric layer

108a‧‧‧First ditches

108b‧‧‧Second ditches

110‧‧‧Opening

112‧‧‧Active layer

114‧‧‧ bottom conductive layer

120‧‧‧ patterned conductive layer

122‧‧‧First circuit layer

122a‧‧‧First buried circuit layer

122b‧‧‧First surface circuit layer

124‧‧‧Second circuit layer

124a‧‧‧Second buried circuit layer

124b‧‧‧Second surface circuit layer

126‧‧‧through holes

Claims (12)

A method for fabricating a circuit board, comprising: forming a dielectric layer on a substrate, wherein an internal wiring layer is formed on the substrate, and the dielectric layer covers the internal circuit layer; forming a first layer in the dielectric layer a trench, a second trench, and an opening, wherein the opening is located below the first trench and communicates with the first trench, and the opening exposes a portion of the internal wiring layer; forming a layer on the dielectric layer And patterning the conductive layer, the patterned conductive layer covers a portion of the dielectric layer, and fills the first trench, the second trench, and the opening to form a first circuit layer, a second circuit layer, and a a via hole, wherein the via hole is electrically connected to the first circuit layer and the internal circuit layer, the first circuit layer includes a first buried circuit layer and a first surface circuit layer, where the first buried circuit layer is located In the first trench, the first surface circuit layer is located on the dielectric layer and the first buried circuit layer, and a boundary of the first buried circuit layer is located in a boundary of the first surface circuit layer. The second circuit layer includes a second buried a road layer and a second surface circuit layer, the second buried circuit layer is located in the second trench, the second surface circuit layer is located on the dielectric layer and the second buried circuit layer, and the second inner The boundary of the buried wiring layer is located within the boundary of the second surface wiring layer. The method for fabricating a circuit board according to claim 1, wherein the dielectric layer is further included after forming the first trench, the second trench, and the opening, and before forming the patterned conductive layer. An active layer is formed on the inner wiring layer on a portion exposed to the opening. The method for fabricating a circuit board according to claim 2, wherein the method for forming the patterned conductive layer comprises: forming a bottom conductive layer on the active layer; forming a conductive material layer on the bottom conductive layer, The conductive material layer fills the first trench, the second trench, and the opening; forming a patterned photoresist layer, the patterned photoresist layer covering the first trench and the second trench and located at the first trench and the second trench a layer of conductive material around the first trench and around the second trench; removing the portion of the conductive material layer and a portion of the bottom conductive layer by using the patterned photoresist layer as a mask; and removing the patterned photoresist layer . The method for fabricating a circuit board according to claim 2, wherein the method for forming the patterned conductive layer comprises: forming a bottom conductive layer on the active layer; forming a patterned photoresist on the bottom conductive layer a layer, the patterned photoresist layer exposing the first trench, the second trench, and the bottom conductive layer around the first trench and the second trench; the bottom exposed by the patterned photoresist layer Forming a conductive material layer on the conductive layer, wherein the conductive material layer fills the first trench, the second trench, and the opening; and removing the patterned photoresist layer and the underlying the patterned photoresist layer Bottom conductive layer. The method for fabricating a circuit board according to claim 1, wherein the dielectric layer contains a plurality of activated particles, and the first A portion of the activated particles are exposed during the trench, the second trench, and the opening. The method for fabricating a circuit board according to claim 5, wherein the method for forming the patterned conductive layer comprises: forming a bottom conductive layer on the dielectric layer; and exposing the opening on the bottom conductive layer Forming a conductive material layer on the inner circuit layer, wherein the conductive material layer fills the first trench, the second trench and the opening; forming a patterned photoresist layer, the patterned photoresist layer covers The conductive material layer is located above the first trench and the second trench and around the first trench and around the second trench; and the patterned photoresist layer is used as a mask to remove part of the conductive material layer and part The bottom conductive layer; and removing the patterned photoresist layer. The method for fabricating a circuit board according to claim 5, wherein the method for forming the patterned conductive layer comprises: forming a bottom conductive layer on the dielectric layer; forming a patterned light on the bottom conductive layer a patterned photoresist layer exposing the first trench, the second trench, and the bottom conductive layer around the first trench and the second trench; the exposed photoresist layer is exposed Forming a conductive material layer on the bottom conductive layer and a portion of the inner circuit layer, wherein the conductive material layer fills the first trench, the second trench, and the opening; and removing the patterned photoresist layer and the pattern The bottom conductive layer under the photoresist layer. A circuit board comprising: a substrate; an internal circuit layer disposed on the substrate; a dielectric layer disposed on the substrate and covering the internal circuit layer; and a first circuit layer including a first buried circuit And a first surface wiring layer, wherein the first buried wiring layer is buried in the dielectric layer, the first surface wiring layer is disposed on the dielectric layer and the first buried wiring layer, and the a boundary of the first buried circuit layer is located within a boundary of the first surface circuit layer; a second circuit layer includes a second buried circuit layer and a second surface circuit layer, wherein the second buried circuit layer Buried in the dielectric layer, the second surface wiring layer is disposed on the dielectric layer and the second buried wiring layer, and a boundary of the second buried wiring layer is located within a boundary of the second surface wiring layer And a via hole disposed in the dielectric layer and electrically connected to the first buried circuit layer and the internal circuit layer. The circuit board of claim 8, further comprising an active layer disposed between the dielectric layer and the first circuit layer, between the dielectric layer and the second circuit layer, and the dielectric Between the layer and the via hole and between the inner circuit layer and the via hole. The circuit board of claim 9, further comprising a bottom conductive layer disposed on the active layer. The circuit board of claim 8, wherein the dielectric layer contains a plurality of activated particles. The circuit board of claim 11, further comprising a bottom conductive layer disposed between the dielectric layer and the first circuit layer, between the dielectric layer and the second circuit layer, and the dielectric layer Between the electrical layer and the via.