TWI436464B - Semiconductor package, substrate, and manufacturing method of substrate - Google Patents

Description

Semiconductor package, substrate and substrate manufacturing method

The present invention relates to a semiconductor package, a substrate, and a method of fabricating a substrate.

Integrated circuit (IC) packaging technology plays an important role in the electronics industry. As lightweight, compactness, and high efficiency have become typical requirements for consumer electronics and communications products, chip packages must provide excellent electrical characteristics, small overall volume, and large amounts of I/O. The substrate used for wafer packaging typically has a plurality of metal layers that can be electrically connected to one another by the use of traces and/or vias. As the size of the chip package is reduced, these lines and vias for connecting multiple metal layers can be made smaller and more closely spaced, which increases the cost and complexity of the integrated circuit packaging process. Therefore, there is a need to develop a substrate which has a thin appearance, is manufactured by a less complicated process, is suitable for mass production, and can be produced with high production yield. There is also a need to develop a corresponding package including the substrate, and a method of manufacturing the substrate and the corresponding package.

The present invention provides a semiconductor package having a substrate having a small volume.

The present invention provides a substrate having a small volume.

The present invention provides a substrate manufacturing method which can produce a substrate having a small volume.

The invention relates to a semiconductor package comprising a substrate and a wafer. The substrate includes two outer layers, two solder mask layers, a plurality of inner layers, and a patterned conductive layer. The outer layers each include an outer patterned conductive layer. The solder resist layers are respectively on the surface of the outer layer, and each solder resist layer exposes a portion of each of the outer patterned conductive layers to define a plurality of contact pads. The inner layers overlap each other and are electrically connected to the middle of the outer layers, and the inner layer respectively has an inner patterned conductive layer, a plurality of inner conductive pillars, an inner dielectric layer and a middle patterned conductive layer. The inner conductive pillars are respectively located on the inner patterned conductive layer, and the inner dielectric layer is located between the inner patterned conductive layer and the inner conductive pillars and exposes the upper surface of the inner conductive pillars. The medium patterned conductive layer is located on an upper surface of the plurality of inner layers and is connected to the outer layer above the inner layer. The wafer is electrically connected to at least a portion of the contact pads.

The invention relates to a substrate comprising two outer layers, two solder mask layers, a plurality of inner layers and a medium patterned conductive layer. The outer layers each include an outer patterned conductive layer. The solder resist layers are respectively on the surface of the outer layer, and each solder resist layer exposes a portion of each of the outer patterned conductive layers to define a plurality of contact pads. The inner layers overlap each other and are electrically connected to the middle of the outer layers, and the inner layer respectively has an inner patterned conductive layer, a plurality of inner conductive pillars, an inner dielectric layer and a middle patterned conductive layer. The inner conductive pillars are respectively located on the inner patterned conductive layer, and the inner dielectric layer is located between the inner patterned conductive layer and the inner conductive pillars and exposes the upper surface of the inner conductive pillars. The medium patterned conductive layer is located on an upper surface of the plurality of inner layers and is connected to the outer layer above the inner layer.

The present invention relates to a substrate manufacturing method comprising providing a carrier having an upper surface forming a plurality of inner layers overlapping and electrically connected to each other on the upper surface. Forming each inner layer includes forming an inner patterned conductive layer to form a plurality of inner conductive pillars on the inner patterned conductive layer, forming an inner dielectric layer between the inner patterned conductive layer and the inner conductive pillar, and removing the inner dielectric The upper surface of the electrical layer exposes the upper surface of the inner conductive pillar. Next, a patterned conductive layer is formed on the upper surface of the inner layer, and the carrier is removed to expose the inner patterned conductive layer. Forming an outer layer having an outer patterned conductive layer on the inner patterned conductive layer and the middle patterned conductive layer, respectively, and finally forming a solder resist layer on the surfaces of the two outer layers, respectively, and each solder resist layer exposes each outer pattern One portion of the conductive layer is defined to define a plurality of contact pads.

Based on the above, in the present invention, the conductive pillars in the dielectric layer can be used to reduce the package size and package area, and further reduce the cost and complexity of the packaging process.

The above described features and advantages of the present invention will be more apparent from the following description.

1A through 1U are schematic cross-sectional views showing a method of fabricating a substrate having a plurality of dielectric layers in accordance with various embodiments of the present invention. First, referring to FIG. 1A, a carrier 110 is provided that includes an upper surface 110a and a lower surface 110b relative to the upper surface 110a. In the present embodiment, the manufacturing processes described below are simultaneously applied to the upper surface 110a and the lower surface 110b of the carrier 110 to increase production efficiency.

Referring to FIG. 1B, an inner patterned conductive layer 111a is formed on the upper surface 110a of the carrier 110. In this embodiment, an inner patterned conductive layer 111b is formed on the lower surface 110a of the carrier 110. The inner patterned conductive layers 111a, 111b may be formed by an additive process, a semi-additive process, or a subtractive process, and the inner patterned conductive layers 111a, 111b respectively comprise A plurality of contact pads and a plurality of lines, and the contact pads and lines can be formed substantially simultaneously in a conventional manner.

In the above, a plurality of inner conductive pillars 121a are formed to internally pattern the conductive layer 111a. In this embodiment, a plurality of inner conductive pillars 121b are additionally formed to internally pattern the conductive layer 111b. The inner conductive pillars 121a, 121b may be formed in the same manner as the inner patterned conductive layers 111a, 111b, such as an additive method, a semi-additive method, or a subtractive method. In addition, the inner conductive pillars 121a, 121b can also be made in different ways.

Referring to FIG. 1C, an inner dielectric layer 131a is formed between the inner patterned conductive layer 111a and the inner conductive pillar 121a, so that the inner patterned conductive layer 111a and the inner conductive pillar 121a are buried in the inner dielectric layer 131a. In this embodiment, an inner dielectric layer 131b is formed between the inner patterned conductive layer 111b and the inner conductive pillar 121b, so that the inner patterned conductive layer 111b and the inner conductive pillar 121b are buried in the inner dielectric layer 131b. in. In the present embodiment, the material of the laminated inner dielectric layers 131a, 131b comprises a fiber-reinforced resin material, such as a prepreg material, comprising a plurality of fibers 190a, 190b. To increase the structural strength of the inner dielectric layers 131a, 131b. As shown in FIG. 1C, the fibers 190a located around the inner conductive pillars 121a are pushed by the direction in which the inner conductive pillars 121a extend vertically, so that the fibers 190a are arranged in a direction away from the inner patterned conductive layer 111a. Similarly, the fibers 190b located around the inner conductive pillars 121b are pushed by the direction in which the inner conductive pillars 121b extend vertically, so that the fibers 190b are arranged in a direction away from the inner patterned conductive layer 111b.

Next, referring to FIG. 1D, the exposed portion above the inner dielectric layer 131a is removed to expose the inner conductive pillar 121a, and the exposed portion below the inner dielectric layer 131b is removed to expose the inner conductive pillar 121b. Thus, an inner layer is formed on each of the upper and lower surfaces of the carrier 110. The exposed portions of the inner dielectric layers 131a, 131b can be removed by digging, grinding or other material removal techniques. As shown in FIG. 1D, the exposed faces of the inner conductive posts 121a, 121b are substantially coplanar with the exposed faces of the inner dielectric layers 131a, 131b, respectively.

Next, another inner layer is formed on the inner layer formed in the above steps. Referring to FIG. 1E, an inner patterned conductive layer 112a is first formed on the exposed faces of the inner dielectric layer 131a and the inner conductive pillars 121a, and is connected to the inner conductive pillars 121a. In this embodiment, an inner patterned conductive layer 112b is formed on the exposed surface of the inner dielectric layer 131b and the inner conductive pillar 121b, and is connected to the inner conductive pillar 121b. The inner patterned conductive layers 112a, 112b may be formed by an additive method, a semi-additive method, or a subtractive method. The inner patterned conductive layers 112a, 112b respectively comprise a plurality of contact pads and a plurality of lines, and the contact pads and the lines can be formed substantially simultaneously in the same manufacturing method.

In the above, a plurality of inner conductive pillars 122a are formed to internally pattern the conductive layer 112a. In the embodiment, a plurality of inner conductive pillars 122b are further formed to internally pattern the conductive layer 112b. The inner conductive pillars 122a, 122b can be formed in the same manner as the inner patterned conductive layers 112a, 112b, such as an additive method, a semi-additive method, or a subtractive method. In addition, the inner conductive posts 122a, 122b can also be made in different ways.

Referring to FIG. 1F, an inner dielectric layer 132a is formed between the inner patterned conductive layer 112a and the inner conductive pillars 122a, so that the inner patterned conductive layer 112a and the inner conductive pillars 122a are buried in the inner dielectric layer 132a. In this embodiment, an inner dielectric layer 132b is formed between the inner patterned conductive layer 112b and the inner conductive pillar 122b, so that the inner patterned conductive layer 112b and the inner conductive pillar 122b are buried in the inner dielectric layer 132b. in. The material of the laminated inner dielectric layers 132a, 132b comprises a fiber reinforced resin material, such as a prepreg material having fibers (not shown), and the fibers located around the inner conductive pillars 122a, 122b are received by the inner conductive pillars 122a. The pushing of the 122b in the vertical extension direction causes the fibers to be arranged away from the inner patterned conductive layers 112a, 112b.

Next, referring to FIG. 1G, the exposed portion of the inner dielectric layer 132a is removed to expose the inner conductive pillars 122a. In the present embodiment, the exposed portion below the inner dielectric layer 132b is additionally removed to expose the inner conductive pillar 122b. As such, the upper and lower sides of the carrier 110 each form another inner layer of the substrate. The exposed portions of the inner dielectric layers 132a, 132b can be removed by digging, grinding or other material removal techniques. As shown in FIG. 1G, the exposed faces of the inner conductive posts 122a, 122b are substantially coplanar with the exposed faces of the inner dielectric layers 132a, 132b, respectively.

Next, referring to FIG. 1H, a medium patterned conductive layer 113a is formed on the exposed surface of the inner dielectric layer 132a and the inner conductive pillar 122a, and is connected to the inner conductive pillar 122a. In this embodiment, a medium patterned conductive layer 113b is formed on the exposed surface of the inner dielectric layer 132b and the inner conductive pillar 122b, and is connected to the inner conductive pillar 122b. The medium patterned conductive layers 113a, 113b may be formed by an additive method, a semi-additive method, or a subtractive method. The medium patterned conductive layers 113a, 113b respectively comprise a plurality of contact pads and a plurality of lines, and the contact pads and the lines can be formed substantially simultaneously in the same manufacturing method.

Next, referring to FIG. 1I, the carrier 110 is removed, or the carrier 110 is separated from the inner patterned conductive layer 111a and the inner dielectric layer 131a to expose the inner patterned conductive layer 111a. In this embodiment, the carrier 110 is also separated from the inner patterned conductive layer 111b and the inner dielectric layer 131b to expose the inner patterned conductive layer 111b. As shown in FIG. 1I, the inner patterned conductive layers 111a, 111b are The exposed faces are substantially coplanar with the exposed faces of the inner dielectric layers 131a, 131b, respectively. Thus, two substrates having a plurality of dielectric layers are formed, and the following manufacturing method will be described with reference to the substrate described above.

1A through 1I, previously described, are common steps in various embodiments of a substrate fabrication method having a plurality of dielectric layers. In the following various embodiments, the manufacturing flow of the first embodiment is illustrated in FIGS. 1A to 1N. The manufacturing flow of the second embodiment is illustrated in FIGS. 1A to 1I and the following FIGS. 10A to 1R. The manufacturing flow of the third embodiment is illustrated in FIGS. 1A to 1I and the following FIGS. 1S to 1U.

Referring to FIG. 1J, in the first embodiment, a plurality of outer conductive pillars 123 are formed on the intermediate patterned conductive layer 113a. In this embodiment, a plurality of outer conductive pillars 124 are additionally formed on the inner patterned conductive layer 111a. The outer conductive pillars 123, 124 can be made by an additive method, a semi-additive method, or a subtractive method.

Next, referring to FIG. 1K, an outer dielectric layer 133 is formed between the intermediate patterned conductive layer 113a and the outer conductive pillar 123, so that the medium patterned conductive layer 113a and the outer conductive pillar 123 are buried in the outer dielectric layer 133. in. In the above, an outer dielectric layer 134 is formed between the patterned conductive layer 111a and the outer conductive pillars 124 such that the patterned conductive layer 111a and the outer conductive pillars 124 are buried in the outer dielectric layer 134. The material of the outer dielectric layers 133, 134 includes a fiber-reinforced resin material, such as a prepreg material, which has fibers (not shown), and the fibers located around the outer conductive pillars 123, 124 are vertically extended by the outer conductive pillars 123, 124. The pushing of the directions causes the fibers to be arranged in a direction away from the inner patterned conductive layers 113a, 111a.

Referring to FIG. 1L, the exposed portion above the outer dielectric layer 133 is removed to expose the outer conductive pillars 123. In the present embodiment, the exposed portion outside the outer dielectric layer 134 is additionally removed to expose the outer conductive pillars 124. The exposed portions of the outer dielectric layers 133, 134 can be removed by routing, grinding, or other material removal techniques. As shown in FIG. 1L, the exposed faces of the outer conductive posts 123, 124 are substantially coplanar with the exposed faces of the outer dielectric layers 133, 134, respectively.

Next, referring to FIG. 1M, an outer patterned conductive layer 114 is formed on the outer dielectric layer 133 and the outer conductive pillar 123, and the outer patterned conductive layer 114 is connected to the outer conductive pillar 123. In the present embodiment, an outer patterned conductive layer 115 is formed on the outer dielectric layer 134 and the outer conductive pillars 124, and the outer patterned conductive layer 115 is connected to the outer conductive pillars 124. Thus, the upper two outer layers of the first embodiment of the substrate of the present invention are formed. The outer patterned conductive layers 114, 115 may be formed by an additive method, a semi-additive method, or a subtractive method. The outer patterned conductive layers 114, 115 respectively comprise a plurality of contact pads and a plurality of lines, and the contact pads and the lines can be formed substantially simultaneously in the same manufacturing method.

Referring to FIG. 1N, a solder resist layer 141 is formed on the outer dielectric layer 133 and at least a portion of the patterned conductive layer 114. The portion of the patterned conductive layer 114 is not exposed by the solder resist layer 141, and is exposed to the outside. Define multiple contact pads. In this embodiment, a solder resist layer 142 is further formed on the outer dielectric layer 134 and at least a portion of the patterned conductive layer 115. The portion of the patterned conductive layer 115 is not exposed by the solder resist layer 141. To define multiple contact pads. As such, the substrate package structure 100 is completed.

In the second embodiment of the present invention, referring to FIG. 10, a plurality of semiconductive pillars 123' are formed on the patterned conductive layer 113a. In this embodiment, a plurality of semiconductive pillars 124' are additionally formed on the inner patterned conductive layer 111a. The semiconductive pillars 123', 124' are similar to the conductive pillars 123, 124 in FIG. 1J except that the heights of the semiconductive pillars 123', 124' are lower than the heights of the outer conductive pillars 123, 124, respectively.

Next, as shown in FIG. 1K, an outer dielectric layer 133 is formed between the patterned conductive layer 113a and the semiconductive pillar 123', so that the medium patterned conductive layer 113a and the semiconductive pillar 123' are buried. In the outer dielectric layer 133. Similarly, an outer dielectric layer 134 is formed between the inner patterned conductive layer 111a and the semiconductive pillars 124' such that the inner patterned conductive layer 111a and the semiconductive pillars 124' are buried in the outer dielectric layer 133. The material of the outer dielectric layers 133, 134 includes a fiber-reinforced resin material such as a prepreg. In the above, a first conductive layer 150, such as a copper foil, is disposed on the outer dielectric layer 133. Similarly, a first conductive layer 151, such as a copper foil, is disposed over the outer dielectric layer 134.

Referring to FIG. 1P, a plurality of openings 153 extending from the first conductive layer 150 to the outer dielectric layer 133 are formed. The opening 153 exposes at least a portion of the surface of the semiconductive post 123'. In one embodiment of the invention, the opening 153 can be obtained by laser drilling. A metal material is then disposed on the first conductive layer 150 and the semiconductive pillars 123' to form a second conductive layer 152, such as a sublayer. The same process is also applied to the bottom of the substrate, that is, on the semiconductive pillars 124' and the outer dielectric layer 134.

Referring to FIG. 1Q, an outer patterned conductive layer 114 is formed on the second conductive layer 152 and connected to the semiconductive pillar 123'. The outer patterned conductive layer 114 can be made by an additive method, a semi-additive method, or a subtractive method. The outer patterned conductive layer 114 includes a plurality of contact pads and a plurality of lines, and the contact pads and the lines can be formed substantially simultaneously in the same manufacturing method. The same process is also applied to the bottom of the substrate to form the outer patterned conductive layer 115.

Referring to FIG. 1R, the conductive layers 150, 152 of the portion of the outer patterned conductive layer 114 are removed. This step can be achieved by a subtractive method. Thus, the lower two outer layers of the second embodiment of the substrate of the present invention are formed. Next, a solder mask layer 141 is formed on the outer dielectric layer 133 and at least a portion of the outer patterned conductive layer 114. A portion of the outer patterned conductive layer 114 that is not covered by the solder mask layer 141 is exposed to define a plurality of contact pads. The same process is also applied to the bottom of the substrate to form a plurality of contact pads by a portion of the outer patterned conductive layer 114 exposed by the solder resist layer 141. As such, the substrate package structure 100' is fabricated.

In the third embodiment, referring to FIG. 1S, an outer dielectric layer 133 is formed between the patterned conductive layers 113a, so that the medium patterned conductive layer 113a is buried in the outer dielectric layer 133. In the present embodiment, unlike FIG. 1J and FIG. 1K, the semiconductive pillars 123 are not formed on the patterned conductive layer 113a. Similarly, an outer dielectric layer 134 is formed between the inner patterned conductive layers 111a such that the inner patterned conductive layer 111a is buried in the outer dielectric layer 133. The material of the outer dielectric layers 133, 134 includes a fiber-reinforced resin material such as a prepreg. A first conductive layer 150, such as a copper foil, is then disposed over the outer dielectric layer 133. Similarly, a first conductive layer 151 such as a copper foil is disposed on the outer dielectric layer 134.

Referring to FIG. 1T, a plurality of openings 163 extending from the first conductive layer 150 to the outer dielectric layer 133 are formed. The opening 163 exposes at least a portion of the surface of the patterned conductive layer 113a. In an embodiment of the invention, the opening 163 may be obtained by laser drilling. A metal material is then disposed on the first conductive layer 150 and the medium patterned conductive layer 113a to form a second conductive layer 152, such as a sub-layer. The same process is also applied to the bottom of the substrate, that is, the outer dielectric layer 133 and the inner patterned conductive layer 111a.

Next, an outer patterned conductive layer 114 is formed on the second conductive layer 152 and electrically connected to the medium patterned conductive layer 113a. The outer patterned conductive layer 114 can be formed by an additive method, a semi-additive method, and a subtractive method. to make. The outer patterned conductive layer 114 includes a plurality of contact pads and a plurality of lines, and the contact pads and the lines can be formed substantially simultaneously in the same manufacturing method. The same process is also applied to the bottom of the substrate to form the outer patterned conductive layer 115.

Referring to FIG. 1U, corresponding to the conductive layer 150, 152 of the portion of the outer patterned conductive layer 114, this step can be achieved by a subtractive method. Next, a solder mask layer 141 is formed on the outer dielectric layer 133 and at least a portion of the outer patterned conductive layer 114. A portion of the outer patterned conductive layer 114 that is not covered by the solder mask layer 141 is exposed to define a plurality of contact pads. The same process is also applied to the bottom of the substrate to form a plurality of contact pads by a portion of the outer patterned conductive layer 115 exposed by the solder resist layer 141. As such, the substrate package structure 100" is fabricated.

Although not shown in the package structure of FIG. 1A to FIG. 1U, it is expected that the dielectric layer may further comprise at least one set of sub-conductive pillars, such as outer conductive pillars in the outer layer of the substrate, to have conductive pillars of different diameters. Section (or more generally, a conductive via section).

2A is a schematic cross-sectional view showing a semiconductor package structure according to a first embodiment of the present invention. After the substrate package structure 100 is completed as shown in FIGS. 1A to 1N, the semiconductor package structure shown in FIG. 2A can also be fabricated therefrom. Referring to FIG. 2A, a wafer 200 is disposed on a contact pad of the substrate package structure 100, and the wafer 200 is electrically connected to the substrate package structure 100 by a flip chip technique (or wire bonding technology), and a plurality of solder balls are disposed (not drawn Shown on the contact pad on the other side of the substrate package structure 100.

2B is a cross-sectional view showing a semiconductor package structure according to a second embodiment of the present invention. After the substrate package structure 100' is completed as shown in FIGS. 1A to 1I and FIGS. 1O to 1R, the semiconductor package structure shown in FIG. 2B can also be fabricated therefrom. Referring to FIG. 2B, a wafer 200 is disposed on the contact pads of the substrate package structure 100', and the wafer 200 is electrically connected to the substrate package structure 100' by flip chip technology (or wire bonding technology), and a plurality of solder balls are disposed ( Not shown) on the contact pads on the other side of the substrate package structure 100'.

2C is a cross-sectional view showing a semiconductor package structure according to a third embodiment of the present invention. After the substrate package structure 100" is completed as shown in FIG. 1A to FIG. 1I and FIG. 1S to FIG. 1U, the semiconductor package structure shown in FIG. 2C can also be fabricated. Referring to FIG. 2C, a wafer 200 is disposed. On the contact pad of the substrate package structure 100", and electrically connecting the wafer 200 to the substrate package structure 100" by flip chip technology (or wire bonding technology), and providing a plurality of solder balls (not shown) in the substrate package structure 100" On the other side of the contact pad.

In summary, in various embodiments of the substrate and the semiconductor package structure of the present invention, the conductive pillars can be used to reduce the package size and package area, and further reduce the cost and complexity of the packaging process. In other embodiments, the plurality of dielectric layers can have a plurality of buried conductive pillars to handle the plurality of electrical distributions to increase the strength of the structure and the reliability of the substrate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 100', 100"... substrate package structure

110. . . Carrier

110a. . . Upper surface

110b. . . lower surface

111a, 111b, 112a, 112b. . . Inner patterned conductive layer

113a, 113b. . . Medium patterned conductive layer

114, 115. . . External patterned conductive layer

121a, 121b, 122a, 122b. . . Inner conductive column

123, 124. . . External conductive column

123', 124'. . . Semiconductive column

131a, 131b, 132a, 132b. . . Internal dielectric layer

133, 134. . . External dielectric layer

141, 142. . . Solder mask

150, 151. . . First conductive layer

152. . . Second conductive layer

153, 163. . . Opening

190a, 190b. . . fiber

200. . . Wafer

1A through 1U are schematic cross-sectional views showing a method of fabricating a substrate having a plurality of dielectric layers in accordance with various embodiments of the present invention.

2A is a schematic cross-sectional view showing a semiconductor package structure according to a first embodiment of the present invention.

2B is a cross-sectional view showing a semiconductor package structure according to a second embodiment of the present invention.

2C is a cross-sectional view showing a semiconductor package structure according to a third embodiment of the present invention.

100'. . . Substrate package structure

114, 115. . . External patterned conductive layer

133, 134. . . External dielectric layer

141, 142. . . Solder mask

150. . . First conductive layer

152. . . Second conductive layer

200. . . Wafer

Claims (13)

A semiconductor package comprising: a substrate comprising: two outer layers each comprising an outer patterned conductive layer, a plurality of outer conductive pillars, and an outer dielectric layer; and two solder resist layers respectively on the surfaces of the two outer layers, and Each of the solder resist layers exposes a portion of the corresponding outer patterned conductive layer to define a plurality of contact pads; a plurality of inner layers are located in the middle of the two outer layers and are electrically connected thereto, and the inner layers respectively have: Internally patterned conductive layer; a plurality of inner conductive pillars on the inner patterned conductive layer; and an inner dielectric layer between the inner patterned conductive layer and the inner conductive pillars and exposing the inner conductive pillars In the upper surface, the inner dielectric layer comprises a fiber-reinforced resin material, wherein fibers surrounding the inner conductive pillars are pushed by the inner conductive pillars in a direction perpendicular to the direction of the inner conductive pillars And a patterned conductive layer on an upper surface of the inner layers, connected to the outer layer above the inner layers; and a wafer electrically connected to at least a portion of the contact pads, wherein the outer conductive pillars Are respectively located on the patterned conductive layer and the patterned conductive layer within the upper and lower surfaces of the plurality of inner layer, and The outer dielectric layers are respectively located between the outer conductive pillars and expose the upper surfaces of the outer conductive pillars, and the outer patterned conductive layers are respectively located on the outer dielectric layers and the outer conductive pillars, and The solder resist layers are respectively located on each of the outer dielectric layers and at least a portion of each of the outer patterned conductive layers. The semiconductor package of claim 1, wherein the wafer is flip-chip bonded to at least a portion of the contact pads. The semiconductor package of claim 1, wherein the wafer is wire bonded to at least a portion of the contact pads. A semiconductor package comprising: a substrate comprising: two outer layers each comprising an outer patterned conductive layer, a plurality of semiconductive pillars, an outer dielectric layer, a first conductive layer, a plurality of openings, and a second conductive layer a layer; two solder masks respectively on the surfaces of the two outer layers, and each of the solder resist layers exposing a portion of the corresponding outer patterned conductive layer to define a plurality of contact pads; a plurality of inner layers located at the outer layers And electrically connected to the middle layer, the inner layers respectively have: an inner patterned conductive layer; a plurality of inner conductive pillars on the inner patterned conductive layer; and an inner dielectric layer located inside the patterned conductive Between the layer and the inner conductive pillars and exposing the upper surfaces of the inner conductive pillars; a patterned conductive layer on an upper surface of the inner layers and connected to the outer layer above the inner layers; and a wafer electrically connected to at least a portion of the contact pads, wherein the semiconductive pillars are respectively located The intermediate patterned conductive layer and the inner patterned conductive layer on the lower surface of the inner layer respectively cover the middle patterned conductive layer, the inner patterned conductive layer and the semiconductive pillars Each of the first conductive layers is respectively located on a portion of the outer dielectric layers, and the openings are respectively extended from the first conductive layer to the outer dielectric layer, the openings exposing at least a portion of the semiconductive pillar surfaces And each of the second conductive layers is respectively located on the first conductive layer and the semi-conductive pillars, and the outer patterned conductive layers are respectively located on the second conductive layers, and the solder resist layers are respectively located at the respective An outer dielectric layer and at least a portion of the outer patterned conductive layer. A semiconductor package comprising: a substrate comprising: two outer layers respectively including an outer patterned conductive layer, an outer dielectric layer, a first conductive layer, a plurality of openings, and a second conductive layer; and two solder resist layers Respectively located on the surfaces of the two outer layers, and each of the solder resist layers exposes a portion of the corresponding outer patterned conductive layer to define a plurality of contact pads; a plurality of inner layers located in the middle of the outer layers and electrically connected thereto Connecting, the inner layers respectively have: an inner patterned conductive layer; a plurality of inner conductive pillars on the inner patterned conductive layer; and an inner dielectric layer between the inner patterned conductive layer and the inner conductive pillars and exposing the upper conductive pillars; and a patterned conductive layer on an upper surface of the inner layers and connected to the outer layer above the inner layers; and a wafer electrically connected to at least a portion of the contact pads, wherein each of the outer dielectric layers respectively covers The first conductive layer and the inner patterned conductive layer are respectively located on a portion of the outer dielectric layers, and the openings are respectively extended from the first conductive layer to the outer dielectric layer. The openings expose at least a portion of the medium patterned conductive layer and the inner patterned conductive layer, and each of the second conductive layers is located in the middle patterned conductive layer, the inner patterned conductive layer, and the first conductive layers The outer patterned conductive layers are respectively disposed on the second conductive layers, and the solder resist layers are respectively located on the outer dielectric layers and at least a portion of the outer patterned conductive layers. A substrate comprising: two outer layers respectively comprising an outer patterned conductive layer, a plurality of outer conductive pillars, and an outer dielectric layer; two solder resist layers respectively located on surfaces of the two outer layers, and each of the solder resist layers Exposing a portion of the corresponding outer patterned conductive layer to define a plurality of contact pads; a plurality of inner layers, located in the middle of the two outer layers and electrically connected thereto, the inner layers respectively having: an inner patterned conductive layer; a plurality of inner conductive pillars on the inner patterned conductive layer; and an inner layer An electric layer between the inner patterned conductive layer and the inner conductive pillars and exposing the upper surfaces of the inner conductive pillars, the inner dielectric layer comprising a fiber-reinforced resin material, wherein the inner conductive pillars are located around the inner conductive pillars The fibers are pushed by the inner conductive pillars in a direction perpendicular to the direction in which they are arranged away from the inner patterned conductive layer; and a patterned conductive layer is located on an upper surface of the inner layers and above the inner layers The outer conductive pillars are respectively located on the middle patterned conductive layer and the inner patterned conductive layer on the lower surface of the inner layers, and the outer dielectric layers are respectively located on the outer conductive pillars And exposing the upper surfaces of the outer conductive pillars, the outer patterned conductive layers are respectively located on the outer dielectric layers and the outer conductive pillars, and the solder resist layers are respectively located on the outer dielectric layers And at least some of the outer patterning Electric layer. A substrate comprising: two outer layers respectively comprising an outer patterned conductive layer, a plurality of semiconductive pillars, an outer dielectric layer, a first conductive layer, a plurality of openings, and a second conductive layer; and two solder resist layers Respectively located on the surfaces of the two outer layers, and each of the solder resist layers exposes a portion of the corresponding outer patterned conductive layer to define a plurality of contact pads; a plurality of inner layers, located in the middle of the two outer layers and electrically connected thereto, the inner layers respectively having: an inner patterned conductive layer; a plurality of inner conductive pillars on the inner patterned conductive layer; and an inner layer An electrical layer between the inner patterned conductive layer and the inner conductive pillars and exposing the upper surface of the inner conductive pillars; and a patterned conductive layer on an upper surface of the inner layers, and the plurality of inner conductive pillars The outer layer is connected to the upper layer, wherein the semiconductive pillars are respectively located on the middle patterned conductive layer and the inner patterned conductive layer on the lower surface of the inner layers, and the outer dielectric layers respectively cover the middle pattern The conductive layer, the inner patterned conductive layer and the semiconductive pillars, each of the first conductive layers being respectively located on a portion of the outer dielectric layers, wherein the openings are respectively extended from the first conductive layer to the external dielectric layer The electrically conductive layer, the openings are exposed to at least a portion of the semiconductive pillar surfaces, and each of the second conductive layers is respectively located on the first conductive layer and the semiconductive pillars, wherein the outer patterned conductive layers are respectively located The solder resist layer on the second conductive layer Located on each of the outer dielectric layer and at least an outer portion of the patterned conductive layer. A substrate comprising: two outer layers respectively including an outer patterned conductive layer, an outer dielectric layer, a first conductive layer, a plurality of openings, and a second conductive layer; two solder resist layers respectively located on the outer layers And a surface of each of the outer patterned conductive layers is exposed to define a plurality of surfaces a contact pad; a plurality of inner layers located in the middle of the two outer layers and electrically connected thereto, the inner layers respectively having: an inner patterned conductive layer; a plurality of inner conductive pillars on the inner patterned conductive layer; An inner dielectric layer between the inner patterned conductive layer and the inner conductive pillars and exposing the upper surface of the inner conductive pillars; and a patterned conductive layer on an upper surface of the inner layers Connecting the outer layer above the inner layer, wherein each of the outer dielectric layers respectively covers the middle patterned conductive layer and the inner patterned conductive layer, and each of the first conductive layers is respectively located on a portion of the outer dielectric layers Each of the openings extends from the first conductive layer to the outer dielectric layer, the openings exposing at least a portion of the middle patterned conductive layer and the inner patterned conductive layer, and each of the second conductive layers is located On the patterned conductive layer, the inner patterned conductive layer and the first conductive layers, the outer patterned conductive layers are respectively located on the second conductive layers, and the solder resist layers are respectively located in the outer conductive layers. Electrical layer and at least a portion of the outer patterned conductive layer . A substrate manufacturing method comprising: providing a carrier having an upper surface; forming a plurality of inner layers overlapping and electrically connected to each other on the upper surface, wherein each of the inner layers comprises: forming an inner patterned conductive layer ; Forming a plurality of inner conductive pillars on the inner patterned conductive layer; forming an inner dielectric layer between the inner patterned conductive layer and the inner conductive pillars; and removing an upper surface of the inner dielectric layer to expose Forming a top surface of the inner conductive pillar; forming a patterned conductive layer on the upper surface of the inner layer; removing the carrier to expose the inner patterned conductive layer; forming an outer patterned conductive layer The two outer layers are respectively disposed on the inner patterned conductive layer and the middle patterned conductive layer; and two solder resist layers are formed on the surfaces of the two outer layers, and each of the solder resist layers exposes the corresponding outer patterned conductive One of the layers defines a plurality of contact pads. The substrate manufacturing method of claim 9, further comprising: forming a plurality of inner layers overlapping and electrically connected to each other on a lower surface of the carrier; and forming a patterned conductive layer on the other a lower surface of the inner layer; the carrier is removed to expose an inner patterned conductive layer; and an outer layer having an outer patterned conductive layer is formed on the inner patterned conductive layer and the intermediate patterned conductive layer And separately forming two solder mask layers on the surfaces of the two outer layers, and each of the solder resist layers exposing a portion of the corresponding first outer patterned conductive layer to define a plurality of contact pads. The substrate manufacturing method according to claim 9, wherein Forming the outer layers further includes: forming a plurality of outer conductive pillars on the middle patterned conductive layer and the inner patterned conductive layer on the lower surface of the inner layers; forming two outer dielectric layers respectively Between the conductive pillars; removing the upper surface of the outer dielectric layer to expose the upper surface of the outer conductive pillars; and forming two outer patterned conductive layers on the outer dielectric layers and the outer conductive pillars . The substrate manufacturing method of claim 9, wherein the forming the outer layer further comprises: forming a plurality of semiconductive pillars respectively on the lower surface of the inner layer, the patterned conductive layer and the inner patterned conductive layer Forming two outer dielectric layers respectively between the patterned conductive layer, the inner patterned conductive layer and the semiconductive pillars; forming two first conductive layers on the outer dielectric layers; forming Extending from each of the first conductive layers to a plurality of openings of the outer dielectric layer, the openings exposing at least a portion of the semiconductive pillar surfaces; forming two second conductive layers respectively on the first conductive layers and the Forming the outer patterned conductive layers on the second conductive layers; and removing the first and second conductive layers of the portions corresponding to the positions of the outer patterned conductive layers. The substrate manufacturing method according to claim 9, wherein Forming the outer layers further includes: forming two outer dielectric layers respectively between the patterned conductive layer and the inner patterned conductive layer; forming two first conductive layers respectively on the outer dielectric layers; forming Each of the first conductive layers extends to a plurality of openings of the outer dielectric layer, the openings exposing at least a portion of the middle patterned conductive layer and the inner patterned conductive layer; forming two second conductive layers respectively in the middle pattern a conductive layer, the inner patterned conductive layer and the first conductive layers; forming the outer patterned conductive layers on each of the second conductive layers; and removing the positions of the outer patterned conductive layers Part of the first conductive layer and the second conductive layer.